tjh.dev / kernel
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kernel / drivers / ata / ahci.c
at v5.5-rc7 1892 lines 63 kB view raw
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ahci.c - AHCI SATA support 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/pci.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <linux/interrupt.h> 25#include <linux/dma-mapping.h> 26#include <linux/device.h> 27#include <linux/dmi.h> 28#include <linux/gfp.h> 29#include <linux/msi.h> 30#include <scsi/scsi_host.h> 31#include <scsi/scsi_cmnd.h> 32#include <linux/libata.h> 33#include <linux/ahci-remap.h> 34#include <linux/io-64-nonatomic-lo-hi.h> 35#include "ahci.h" 36 37#define DRV_NAME "ahci" 38#define DRV_VERSION "3.0" 39 40enum { 41 AHCI_PCI_BAR_STA2X11 = 0, 42 AHCI_PCI_BAR_CAVIUM = 0, 43 AHCI_PCI_BAR_ENMOTUS = 2, 44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4, 45 AHCI_PCI_BAR_STANDARD = 5, 46}; 47 48enum board_ids { 49 /* board IDs by feature in alphabetical order */ 50 board_ahci, 51 board_ahci_ign_iferr, 52 board_ahci_mobile, 53 board_ahci_nomsi, 54 board_ahci_noncq, 55 board_ahci_nosntf, 56 board_ahci_yes_fbs, 57 58 /* board IDs for specific chipsets in alphabetical order */ 59 board_ahci_al, 60 board_ahci_avn, 61 board_ahci_mcp65, 62 board_ahci_mcp77, 63 board_ahci_mcp89, 64 board_ahci_mv, 65 board_ahci_sb600, 66 board_ahci_sb700, /* for SB700 and SB800 */ 67 board_ahci_vt8251, 68 69 /* 70 * board IDs for Intel chipsets that support more than 6 ports 71 * *and* end up needing the PCS quirk. 72 */ 73 board_ahci_pcs7, 74 75 /* aliases */ 76 board_ahci_mcp_linux = board_ahci_mcp65, 77 board_ahci_mcp67 = board_ahci_mcp65, 78 board_ahci_mcp73 = board_ahci_mcp65, 79 board_ahci_mcp79 = board_ahci_mcp77, 80}; 81 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 83static void ahci_remove_one(struct pci_dev *dev); 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88static void ahci_mcp89_apple_enable(struct pci_dev *pdev); 89static bool is_mcp89_apple(struct pci_dev *pdev); 90static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 91 unsigned long deadline); 92#ifdef CONFIG_PM 93static int ahci_pci_device_runtime_suspend(struct device *dev); 94static int ahci_pci_device_runtime_resume(struct device *dev); 95#ifdef CONFIG_PM_SLEEP 96static int ahci_pci_device_suspend(struct device *dev); 97static int ahci_pci_device_resume(struct device *dev); 98#endif 99#endif /* CONFIG_PM */ 100 101static struct scsi_host_template ahci_sht = { 102 AHCI_SHT("ahci"), 103}; 104 105static struct ata_port_operations ahci_vt8251_ops = { 106 .inherits = &ahci_ops, 107 .hardreset = ahci_vt8251_hardreset, 108}; 109 110static struct ata_port_operations ahci_p5wdh_ops = { 111 .inherits = &ahci_ops, 112 .hardreset = ahci_p5wdh_hardreset, 113}; 114 115static struct ata_port_operations ahci_avn_ops = { 116 .inherits = &ahci_ops, 117 .hardreset = ahci_avn_hardreset, 118}; 119 120static const struct ata_port_info ahci_port_info[] = { 121 /* by features */ 122 [board_ahci] = { 123 .flags = AHCI_FLAG_COMMON, 124 .pio_mask = ATA_PIO4, 125 .udma_mask = ATA_UDMA6, 126 .port_ops = &ahci_ops, 127 }, 128 [board_ahci_ign_iferr] = { 129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), 130 .flags = AHCI_FLAG_COMMON, 131 .pio_mask = ATA_PIO4, 132 .udma_mask = ATA_UDMA6, 133 .port_ops = &ahci_ops, 134 }, 135 [board_ahci_mobile] = { 136 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), 137 .flags = AHCI_FLAG_COMMON, 138 .pio_mask = ATA_PIO4, 139 .udma_mask = ATA_UDMA6, 140 .port_ops = &ahci_ops, 141 }, 142 [board_ahci_nomsi] = { 143 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), 144 .flags = AHCI_FLAG_COMMON, 145 .pio_mask = ATA_PIO4, 146 .udma_mask = ATA_UDMA6, 147 .port_ops = &ahci_ops, 148 }, 149 [board_ahci_noncq] = { 150 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), 151 .flags = AHCI_FLAG_COMMON, 152 .pio_mask = ATA_PIO4, 153 .udma_mask = ATA_UDMA6, 154 .port_ops = &ahci_ops, 155 }, 156 [board_ahci_nosntf] = { 157 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), 158 .flags = AHCI_FLAG_COMMON, 159 .pio_mask = ATA_PIO4, 160 .udma_mask = ATA_UDMA6, 161 .port_ops = &ahci_ops, 162 }, 163 [board_ahci_yes_fbs] = { 164 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), 165 .flags = AHCI_FLAG_COMMON, 166 .pio_mask = ATA_PIO4, 167 .udma_mask = ATA_UDMA6, 168 .port_ops = &ahci_ops, 169 }, 170 /* by chipsets */ 171 [board_ahci_al] = { 172 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI), 173 .flags = AHCI_FLAG_COMMON, 174 .pio_mask = ATA_PIO4, 175 .udma_mask = ATA_UDMA6, 176 .port_ops = &ahci_ops, 177 }, 178 [board_ahci_avn] = { 179 .flags = AHCI_FLAG_COMMON, 180 .pio_mask = ATA_PIO4, 181 .udma_mask = ATA_UDMA6, 182 .port_ops = &ahci_avn_ops, 183 }, 184 [board_ahci_mcp65] = { 185 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | 186 AHCI_HFLAG_YES_NCQ), 187 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, 188 .pio_mask = ATA_PIO4, 189 .udma_mask = ATA_UDMA6, 190 .port_ops = &ahci_ops, 191 }, 192 [board_ahci_mcp77] = { 193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), 194 .flags = AHCI_FLAG_COMMON, 195 .pio_mask = ATA_PIO4, 196 .udma_mask = ATA_UDMA6, 197 .port_ops = &ahci_ops, 198 }, 199 [board_ahci_mcp89] = { 200 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), 201 .flags = AHCI_FLAG_COMMON, 202 .pio_mask = ATA_PIO4, 203 .udma_mask = ATA_UDMA6, 204 .port_ops = &ahci_ops, 205 }, 206 [board_ahci_mv] = { 207 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | 208 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), 209 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 210 .pio_mask = ATA_PIO4, 211 .udma_mask = ATA_UDMA6, 212 .port_ops = &ahci_ops, 213 }, 214 [board_ahci_sb600] = { 215 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | 216 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | 217 AHCI_HFLAG_32BIT_ONLY), 218 .flags = AHCI_FLAG_COMMON, 219 .pio_mask = ATA_PIO4, 220 .udma_mask = ATA_UDMA6, 221 .port_ops = &ahci_pmp_retry_srst_ops, 222 }, 223 [board_ahci_sb700] = { /* for SB700 and SB800 */ 224 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), 225 .flags = AHCI_FLAG_COMMON, 226 .pio_mask = ATA_PIO4, 227 .udma_mask = ATA_UDMA6, 228 .port_ops = &ahci_pmp_retry_srst_ops, 229 }, 230 [board_ahci_vt8251] = { 231 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), 232 .flags = AHCI_FLAG_COMMON, 233 .pio_mask = ATA_PIO4, 234 .udma_mask = ATA_UDMA6, 235 .port_ops = &ahci_vt8251_ops, 236 }, 237 [board_ahci_pcs7] = { 238 .flags = AHCI_FLAG_COMMON, 239 .pio_mask = ATA_PIO4, 240 .udma_mask = ATA_UDMA6, 241 .port_ops = &ahci_ops, 242 }, 243}; 244 245static const struct pci_device_id ahci_pci_tbl[] = { 246 /* Intel */ 247 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ 248 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ 249 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ 250 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ 251 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ 252 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ 253 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ 254 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ 255 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ 256 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ 257 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ 258 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ 259 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ 260 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ 261 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ 262 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ 263 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ 264 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ 265 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ 266 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ 267 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ 268 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ 269 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ 270 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ 271 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ 272 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ 273 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ 274 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ 275 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ 276 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ 277 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ 278 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ 279 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ 280 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ 281 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ 282 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ 283 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ 284 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ 285 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ 286 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ 287 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ 288 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */ 289 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */ 290 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */ 291 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */ 292 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */ 293 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */ 294 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */ 295 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */ 296 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */ 297 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */ 298 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */ 299 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */ 300 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */ 301 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */ 302 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */ 303 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */ 304 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */ 305 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ 306 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ 307 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ 308 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ 309 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ 310 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ 311 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ 312 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ 313 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ 314 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ 315 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ 316 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ 317 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ 318 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ 319 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ 320 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ 321 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ 322 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ 323 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ 324 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ 325 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ 326 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ 327 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ 328 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ 329 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ 330 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ 331 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ 332 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ 333 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ 334 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ 335 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ 336 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ 337 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ 338 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ 339 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ 340 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ 341 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ 342 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ 343 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ 344 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ 345 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ 346 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ 347 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ 348 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ 349 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ 350 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ 351 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ 352 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ 353 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ 354 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ 355 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ 356 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ 357 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ 358 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ 359 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ 360 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ 361 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ 362 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ 363 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ 364 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ 365 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ 366 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ 367 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ 368 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ 369 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ 370 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ 371 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ 372 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ 373 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ 374 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ 375 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ 376 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ 377 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ 378 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ 379 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ 380 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ 381 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ 382 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ 383 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ 384 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ 385 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ 386 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ 387 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ 388 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ 389 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ 390 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ 391 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/ 392 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ 393 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/ 394 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ 395 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ 396 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/ 397 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/ 398 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ 399 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ 400 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/ 401 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/ 402 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ 403 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ 404 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ 405 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ 406 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ 407 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ 408 409 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 410 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 411 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, 412 /* JMicron 362B and 362C have an AHCI function with IDE class code */ 413 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, 414 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, 415 /* May need to update quirk_jmicron_async_suspend() for additions */ 416 417 /* ATI */ 418 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ 419 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ 420 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ 421 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ 422 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ 423 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ 424 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ 425 426 /* Amazon's Annapurna Labs support */ 427 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031), 428 .class = PCI_CLASS_STORAGE_SATA_AHCI, 429 .class_mask = 0xffffff, 430 board_ahci_al }, 431 /* AMD */ 432 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ 433 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ 434 /* AMD is using RAID class only for ahci controllers */ 435 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 436 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, 437 438 /* VIA */ 439 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ 440 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ 441 442 /* NVIDIA */ 443 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ 444 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ 445 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ 446 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ 447 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ 448 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ 449 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ 450 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ 451 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ 452 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ 453 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ 454 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ 455 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ 456 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ 457 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ 458 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ 459 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ 460 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ 461 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ 462 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ 463 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ 464 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ 465 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ 466 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ 467 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ 468 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ 469 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ 470 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ 471 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ 472 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ 473 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ 474 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ 475 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ 476 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ 477 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ 478 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ 479 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ 480 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ 481 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ 482 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ 483 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ 484 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ 485 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ 486 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ 487 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ 488 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ 489 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ 490 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ 491 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ 492 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ 493 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ 494 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ 495 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ 496 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ 497 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ 498 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ 499 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ 500 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ 501 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ 502 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ 503 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ 504 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ 505 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ 506 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ 507 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ 508 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ 509 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ 510 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ 511 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ 512 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ 513 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ 514 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ 515 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ 516 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ 517 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ 518 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ 519 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ 520 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ 521 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ 522 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ 523 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ 524 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ 525 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ 526 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ 527 528 /* SiS */ 529 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 530 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ 531 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ 532 533 /* ST Microelectronics */ 534 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ 535 536 /* Marvell */ 537 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ 538 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ 539 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), 540 .class = PCI_CLASS_STORAGE_SATA_AHCI, 541 .class_mask = 0xffffff, 542 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ 543 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), 544 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ 545 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, 546 PCI_VENDOR_ID_MARVELL_EXT, 0x9170), 547 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ 548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), 549 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), 551 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ 552 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), 553 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ 554 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), 555 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 556 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), 557 .driver_data = board_ahci_yes_fbs }, 558 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ 559 .driver_data = board_ahci_yes_fbs }, 560 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 561 .driver_data = board_ahci_yes_fbs }, 562 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), 563 .driver_data = board_ahci_yes_fbs }, 564 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */ 565 .driver_data = board_ahci_yes_fbs }, 566 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */ 567 .driver_data = board_ahci_yes_fbs }, 568 569 /* Promise */ 570 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 571 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ 572 573 /* Asmedia */ 574 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ 575 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ 576 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ 577 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ 578 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */ 579 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */ 580 581 /* 582 * Samsung SSDs found on some macbooks. NCQ times out if MSI is 583 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 584 */ 585 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, 586 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, 587 588 /* Enmotus */ 589 { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, 590 591 /* Generic, PCI class code for AHCI */ 592 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 593 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, 594 595 { } /* terminate list */ 596}; 597 598static const struct dev_pm_ops ahci_pci_pm_ops = { 599 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume) 600 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend, 601 ahci_pci_device_runtime_resume, NULL) 602}; 603 604static struct pci_driver ahci_pci_driver = { 605 .name = DRV_NAME, 606 .id_table = ahci_pci_tbl, 607 .probe = ahci_init_one, 608 .remove = ahci_remove_one, 609 .driver = { 610 .pm = &ahci_pci_pm_ops, 611 }, 612}; 613 614#if IS_ENABLED(CONFIG_PATA_MARVELL) 615static int marvell_enable; 616#else 617static int marvell_enable = 1; 618#endif 619module_param(marvell_enable, int, 0644); 620MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 621 622static int mobile_lpm_policy = -1; 623module_param(mobile_lpm_policy, int, 0644); 624MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets"); 625 626static void ahci_pci_save_initial_config(struct pci_dev *pdev, 627 struct ahci_host_priv *hpriv) 628{ 629 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { 630 dev_info(&pdev->dev, "JMB361 has only one port\n"); 631 hpriv->force_port_map = 1; 632 } 633 634 /* 635 * Temporary Marvell 6145 hack: PATA port presence 636 * is asserted through the standard AHCI port 637 * presence register, as bit 4 (counting from 0) 638 */ 639 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 640 if (pdev->device == 0x6121) 641 hpriv->mask_port_map = 0x3; 642 else 643 hpriv->mask_port_map = 0xf; 644 dev_info(&pdev->dev, 645 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); 646 } 647 648 ahci_save_initial_config(&pdev->dev, hpriv); 649} 650 651static void ahci_pci_init_controller(struct ata_host *host) 652{ 653 struct ahci_host_priv *hpriv = host->private_data; 654 struct pci_dev *pdev = to_pci_dev(host->dev); 655 void __iomem *port_mmio; 656 u32 tmp; 657 int mv; 658 659 if (hpriv->flags & AHCI_HFLAG_MV_PATA) { 660 if (pdev->device == 0x6121) 661 mv = 2; 662 else 663 mv = 4; 664 port_mmio = __ahci_port_base(host, mv); 665 666 writel(0, port_mmio + PORT_IRQ_MASK); 667 668 /* clear port IRQ */ 669 tmp = readl(port_mmio + PORT_IRQ_STAT); 670 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 671 if (tmp) 672 writel(tmp, port_mmio + PORT_IRQ_STAT); 673 } 674 675 ahci_init_controller(host); 676} 677 678static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 679 unsigned long deadline) 680{ 681 struct ata_port *ap = link->ap; 682 struct ahci_host_priv *hpriv = ap->host->private_data; 683 bool online; 684 int rc; 685 686 DPRINTK("ENTER\n"); 687 688 hpriv->stop_engine(ap); 689 690 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 691 deadline, &online, NULL); 692 693 hpriv->start_engine(ap); 694 695 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 696 697 /* vt8251 doesn't clear BSY on signature FIS reception, 698 * request follow-up softreset. 699 */ 700 return online ? -EAGAIN : rc; 701} 702 703static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 704 unsigned long deadline) 705{ 706 struct ata_port *ap = link->ap; 707 struct ahci_port_priv *pp = ap->private_data; 708 struct ahci_host_priv *hpriv = ap->host->private_data; 709 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 710 struct ata_taskfile tf; 711 bool online; 712 int rc; 713 714 hpriv->stop_engine(ap); 715 716 /* clear D2H reception area to properly wait for D2H FIS */ 717 ata_tf_init(link->device, &tf); 718 tf.command = ATA_BUSY; 719 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 720 721 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), 722 deadline, &online, NULL); 723 724 hpriv->start_engine(ap); 725 726 /* The pseudo configuration device on SIMG4726 attached to 727 * ASUS P5W-DH Deluxe doesn't send signature FIS after 728 * hardreset if no device is attached to the first downstream 729 * port && the pseudo device locks up on SRST w/ PMP==0. To 730 * work around this, wait for !BSY only briefly. If BSY isn't 731 * cleared, perform CLO and proceed to IDENTIFY (achieved by 732 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). 733 * 734 * Wait for two seconds. Devices attached to downstream port 735 * which can't process the following IDENTIFY after this will 736 * have to be reset again. For most cases, this should 737 * suffice while making probing snappish enough. 738 */ 739 if (online) { 740 rc = ata_wait_after_reset(link, jiffies + 2 * HZ, 741 ahci_check_ready); 742 if (rc) 743 ahci_kick_engine(ap); 744 } 745 return rc; 746} 747 748/* 749 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. 750 * 751 * It has been observed with some SSDs that the timing of events in the 752 * link synchronization phase can leave the port in a state that can not 753 * be recovered by a SATA-hard-reset alone. The failing signature is 754 * SStatus.DET stuck at 1 ("Device presence detected but Phy 755 * communication not established"). It was found that unloading and 756 * reloading the driver when this problem occurs allows the drive 757 * connection to be recovered (DET advanced to 0x3). The critical 758 * component of reloading the driver is that the port state machines are 759 * reset by bouncing "port enable" in the AHCI PCS configuration 760 * register. So, reproduce that effect by bouncing a port whenever we 761 * see DET==1 after a reset. 762 */ 763static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, 764 unsigned long deadline) 765{ 766 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 767 struct ata_port *ap = link->ap; 768 struct ahci_port_priv *pp = ap->private_data; 769 struct ahci_host_priv *hpriv = ap->host->private_data; 770 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 771 unsigned long tmo = deadline - jiffies; 772 struct ata_taskfile tf; 773 bool online; 774 int rc, i; 775 776 DPRINTK("ENTER\n"); 777 778 hpriv->stop_engine(ap); 779 780 for (i = 0; i < 2; i++) { 781 u16 val; 782 u32 sstatus; 783 int port = ap->port_no; 784 struct ata_host *host = ap->host; 785 struct pci_dev *pdev = to_pci_dev(host->dev); 786 787 /* clear D2H reception area to properly wait for D2H FIS */ 788 ata_tf_init(link->device, &tf); 789 tf.command = ATA_BUSY; 790 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 791 792 rc = sata_link_hardreset(link, timing, deadline, &online, 793 ahci_check_ready); 794 795 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || 796 (sstatus & 0xf) != 1) 797 break; 798 799 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", 800 port); 801 802 pci_read_config_word(pdev, 0x92, &val); 803 val &= ~(1 << port); 804 pci_write_config_word(pdev, 0x92, val); 805 ata_msleep(ap, 1000); 806 val |= 1 << port; 807 pci_write_config_word(pdev, 0x92, val); 808 deadline += tmo; 809 } 810 811 hpriv->start_engine(ap); 812 813 if (online) 814 *class = ahci_dev_classify(ap); 815 816 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 817 return rc; 818} 819 820 821#ifdef CONFIG_PM 822static void ahci_pci_disable_interrupts(struct ata_host *host) 823{ 824 struct ahci_host_priv *hpriv = host->private_data; 825 void __iomem *mmio = hpriv->mmio; 826 u32 ctl; 827 828 /* AHCI spec rev1.1 section 8.3.3: 829 * Software must disable interrupts prior to requesting a 830 * transition of the HBA to D3 state. 831 */ 832 ctl = readl(mmio + HOST_CTL); 833 ctl &= ~HOST_IRQ_EN; 834 writel(ctl, mmio + HOST_CTL); 835 readl(mmio + HOST_CTL); /* flush */ 836} 837 838static int ahci_pci_device_runtime_suspend(struct device *dev) 839{ 840 struct pci_dev *pdev = to_pci_dev(dev); 841 struct ata_host *host = pci_get_drvdata(pdev); 842 843 ahci_pci_disable_interrupts(host); 844 return 0; 845} 846 847static int ahci_pci_device_runtime_resume(struct device *dev) 848{ 849 struct pci_dev *pdev = to_pci_dev(dev); 850 struct ata_host *host = pci_get_drvdata(pdev); 851 int rc; 852 853 rc = ahci_reset_controller(host); 854 if (rc) 855 return rc; 856 ahci_pci_init_controller(host); 857 return 0; 858} 859 860#ifdef CONFIG_PM_SLEEP 861static int ahci_pci_device_suspend(struct device *dev) 862{ 863 struct pci_dev *pdev = to_pci_dev(dev); 864 struct ata_host *host = pci_get_drvdata(pdev); 865 struct ahci_host_priv *hpriv = host->private_data; 866 867 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { 868 dev_err(&pdev->dev, 869 "BIOS update required for suspend/resume\n"); 870 return -EIO; 871 } 872 873 ahci_pci_disable_interrupts(host); 874 return ata_host_suspend(host, PMSG_SUSPEND); 875} 876 877static int ahci_pci_device_resume(struct device *dev) 878{ 879 struct pci_dev *pdev = to_pci_dev(dev); 880 struct ata_host *host = pci_get_drvdata(pdev); 881 int rc; 882 883 /* Apple BIOS helpfully mangles the registers on resume */ 884 if (is_mcp89_apple(pdev)) 885 ahci_mcp89_apple_enable(pdev); 886 887 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 888 rc = ahci_reset_controller(host); 889 if (rc) 890 return rc; 891 892 ahci_pci_init_controller(host); 893 } 894 895 ata_host_resume(host); 896 897 return 0; 898} 899#endif 900 901#endif /* CONFIG_PM */ 902 903static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 904{ 905 const int dma_bits = using_dac ? 64 : 32; 906 int rc; 907 908 /* 909 * If the device fixup already set the dma_mask to some non-standard 910 * value, don't extend it here. This happens on STA2X11, for example. 911 * 912 * XXX: manipulating the DMA mask from platform code is completely 913 * bogus, platform code should use dev->bus_dma_limit instead.. 914 */ 915 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) 916 return 0; 917 918 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits)); 919 if (rc) 920 dev_err(&pdev->dev, "DMA enable failed\n"); 921 return rc; 922} 923 924static void ahci_pci_print_info(struct ata_host *host) 925{ 926 struct pci_dev *pdev = to_pci_dev(host->dev); 927 u16 cc; 928 const char *scc_s; 929 930 pci_read_config_word(pdev, 0x0a, &cc); 931 if (cc == PCI_CLASS_STORAGE_IDE) 932 scc_s = "IDE"; 933 else if (cc == PCI_CLASS_STORAGE_SATA) 934 scc_s = "SATA"; 935 else if (cc == PCI_CLASS_STORAGE_RAID) 936 scc_s = "RAID"; 937 else 938 scc_s = "unknown"; 939 940 ahci_print_info(host, scc_s); 941} 942 943/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is 944 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't 945 * support PMP and the 4726 either directly exports the device 946 * attached to the first downstream port or acts as a hardware storage 947 * controller and emulate a single ATA device (can be RAID 0/1 or some 948 * other configuration). 949 * 950 * When there's no device attached to the first downstream port of the 951 * 4726, "Config Disk" appears, which is a pseudo ATA device to 952 * configure the 4726. However, ATA emulation of the device is very 953 * lame. It doesn't send signature D2H Reg FIS after the initial 954 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. 955 * 956 * The following function works around the problem by always using 957 * hardreset on the port and not depending on receiving signature FIS 958 * afterward. If signature FIS isn't received soon, ATA class is 959 * assumed without follow-up softreset. 960 */ 961static void ahci_p5wdh_workaround(struct ata_host *host) 962{ 963 static const struct dmi_system_id sysids[] = { 964 { 965 .ident = "P5W DH Deluxe", 966 .matches = { 967 DMI_MATCH(DMI_SYS_VENDOR, 968 "ASUSTEK COMPUTER INC"), 969 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), 970 }, 971 }, 972 { } 973 }; 974 struct pci_dev *pdev = to_pci_dev(host->dev); 975 976 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && 977 dmi_check_system(sysids)) { 978 struct ata_port *ap = host->ports[1]; 979 980 dev_info(&pdev->dev, 981 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); 982 983 ap->ops = &ahci_p5wdh_ops; 984 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; 985 } 986} 987 988/* 989 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when 990 * booting in BIOS compatibility mode. We restore the registers but not ID. 991 */ 992static void ahci_mcp89_apple_enable(struct pci_dev *pdev) 993{ 994 u32 val; 995 996 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); 997 998 pci_read_config_dword(pdev, 0xf8, &val); 999 val |= 1 << 0x1b; 1000 /* the following changes the device ID, but appears not to affect function */ 1001 /* val = (val & ~0xf0000000) | 0x80000000; */ 1002 pci_write_config_dword(pdev, 0xf8, val); 1003 1004 pci_read_config_dword(pdev, 0x54c, &val); 1005 val |= 1 << 0xc; 1006 pci_write_config_dword(pdev, 0x54c, val); 1007 1008 pci_read_config_dword(pdev, 0x4a4, &val); 1009 val &= 0xff; 1010 val |= 0x01060100; 1011 pci_write_config_dword(pdev, 0x4a4, val); 1012 1013 pci_read_config_dword(pdev, 0x54c, &val); 1014 val &= ~(1 << 0xc); 1015 pci_write_config_dword(pdev, 0x54c, val); 1016 1017 pci_read_config_dword(pdev, 0xf8, &val); 1018 val &= ~(1 << 0x1b); 1019 pci_write_config_dword(pdev, 0xf8, val); 1020} 1021 1022static bool is_mcp89_apple(struct pci_dev *pdev) 1023{ 1024 return pdev->vendor == PCI_VENDOR_ID_NVIDIA && 1025 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && 1026 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 1027 pdev->subsystem_device == 0xcb89; 1028} 1029 1030/* only some SB600 ahci controllers can do 64bit DMA */ 1031static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 1032{ 1033 static const struct dmi_system_id sysids[] = { 1034 /* 1035 * The oldest version known to be broken is 0901 and 1036 * working is 1501 which was released on 2007-10-26. 1037 * Enable 64bit DMA on 1501 and anything newer. 1038 * 1039 * Please read bko#9412 for more info. 1040 */ 1041 { 1042 .ident = "ASUS M2A-VM", 1043 .matches = { 1044 DMI_MATCH(DMI_BOARD_VENDOR, 1045 "ASUSTeK Computer INC."), 1046 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), 1047 }, 1048 .driver_data = "20071026", /* yyyymmdd */ 1049 }, 1050 /* 1051 * All BIOS versions for the MSI K9A2 Platinum (MS-7376) 1052 * support 64bit DMA. 1053 * 1054 * BIOS versions earlier than 1.5 had the Manufacturer DMI 1055 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". 1056 * This spelling mistake was fixed in BIOS version 1.5, so 1057 * 1.5 and later have the Manufacturer as 1058 * "MICRO-STAR INTERNATIONAL CO.,LTD". 1059 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". 1060 * 1061 * BIOS versions earlier than 1.9 had a Board Product Name 1062 * DMI field of "MS-7376". This was changed to be 1063 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still 1064 * match on DMI_BOARD_NAME of "MS-7376". 1065 */ 1066 { 1067 .ident = "MSI K9A2 Platinum", 1068 .matches = { 1069 DMI_MATCH(DMI_BOARD_VENDOR, 1070 "MICRO-STAR INTER"), 1071 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), 1072 }, 1073 }, 1074 /* 1075 * All BIOS versions for the MSI K9AGM2 (MS-7327) support 1076 * 64bit DMA. 1077 * 1078 * This board also had the typo mentioned above in the 1079 * Manufacturer DMI field (fixed in BIOS version 1.5), so 1080 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. 1081 */ 1082 { 1083 .ident = "MSI K9AGM2", 1084 .matches = { 1085 DMI_MATCH(DMI_BOARD_VENDOR, 1086 "MICRO-STAR INTER"), 1087 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), 1088 }, 1089 }, 1090 /* 1091 * All BIOS versions for the Asus M3A support 64bit DMA. 1092 * (all release versions from 0301 to 1206 were tested) 1093 */ 1094 { 1095 .ident = "ASUS M3A", 1096 .matches = { 1097 DMI_MATCH(DMI_BOARD_VENDOR, 1098 "ASUSTeK Computer INC."), 1099 DMI_MATCH(DMI_BOARD_NAME, "M3A"), 1100 }, 1101 }, 1102 { } 1103 }; 1104 const struct dmi_system_id *match; 1105 int year, month, date; 1106 char buf[9]; 1107 1108 match = dmi_first_match(sysids); 1109 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || 1110 !match) 1111 return false; 1112 1113 if (!match->driver_data) 1114 goto enable_64bit; 1115 1116 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1117 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1118 1119 if (strcmp(buf, match->driver_data) >= 0) 1120 goto enable_64bit; 1121 else { 1122 dev_warn(&pdev->dev, 1123 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", 1124 match->ident); 1125 return false; 1126 } 1127 1128enable_64bit: 1129 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); 1130 return true; 1131} 1132 1133static bool ahci_broken_system_poweroff(struct pci_dev *pdev) 1134{ 1135 static const struct dmi_system_id broken_systems[] = { 1136 { 1137 .ident = "HP Compaq nx6310", 1138 .matches = { 1139 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1140 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), 1141 }, 1142 /* PCI slot number of the controller */ 1143 .driver_data = (void *)0x1FUL, 1144 }, 1145 { 1146 .ident = "HP Compaq 6720s", 1147 .matches = { 1148 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1149 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), 1150 }, 1151 /* PCI slot number of the controller */ 1152 .driver_data = (void *)0x1FUL, 1153 }, 1154 1155 { } /* terminate list */ 1156 }; 1157 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1158 1159 if (dmi) { 1160 unsigned long slot = (unsigned long)dmi->driver_data; 1161 /* apply the quirk only to on-board controllers */ 1162 return slot == PCI_SLOT(pdev->devfn); 1163 } 1164 1165 return false; 1166} 1167 1168static bool ahci_broken_suspend(struct pci_dev *pdev) 1169{ 1170 static const struct dmi_system_id sysids[] = { 1171 /* 1172 * On HP dv[4-6] and HDX18 with earlier BIOSen, link 1173 * to the harddisk doesn't become online after 1174 * resuming from STR. Warn and fail suspend. 1175 * 1176 * http://bugzilla.kernel.org/show_bug.cgi?id=12276 1177 * 1178 * Use dates instead of versions to match as HP is 1179 * apparently recycling both product and version 1180 * strings. 1181 * 1182 * http://bugzilla.kernel.org/show_bug.cgi?id=15462 1183 */ 1184 { 1185 .ident = "dv4", 1186 .matches = { 1187 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1188 DMI_MATCH(DMI_PRODUCT_NAME, 1189 "HP Pavilion dv4 Notebook PC"), 1190 }, 1191 .driver_data = "20090105", /* F.30 */ 1192 }, 1193 { 1194 .ident = "dv5", 1195 .matches = { 1196 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1197 DMI_MATCH(DMI_PRODUCT_NAME, 1198 "HP Pavilion dv5 Notebook PC"), 1199 }, 1200 .driver_data = "20090506", /* F.16 */ 1201 }, 1202 { 1203 .ident = "dv6", 1204 .matches = { 1205 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1206 DMI_MATCH(DMI_PRODUCT_NAME, 1207 "HP Pavilion dv6 Notebook PC"), 1208 }, 1209 .driver_data = "20090423", /* F.21 */ 1210 }, 1211 { 1212 .ident = "HDX18", 1213 .matches = { 1214 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1215 DMI_MATCH(DMI_PRODUCT_NAME, 1216 "HP HDX18 Notebook PC"), 1217 }, 1218 .driver_data = "20090430", /* F.23 */ 1219 }, 1220 /* 1221 * Acer eMachines G725 has the same problem. BIOS 1222 * V1.03 is known to be broken. V3.04 is known to 1223 * work. Between, there are V1.06, V2.06 and V3.03 1224 * that we don't have much idea about. For now, 1225 * blacklist anything older than V3.04. 1226 * 1227 * http://bugzilla.kernel.org/show_bug.cgi?id=15104 1228 */ 1229 { 1230 .ident = "G725", 1231 .matches = { 1232 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), 1233 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), 1234 }, 1235 .driver_data = "20091216", /* V3.04 */ 1236 }, 1237 { } /* terminate list */ 1238 }; 1239 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1240 int year, month, date; 1241 char buf[9]; 1242 1243 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) 1244 return false; 1245 1246 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1247 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1248 1249 return strcmp(buf, dmi->driver_data) < 0; 1250} 1251 1252static bool ahci_broken_lpm(struct pci_dev *pdev) 1253{ 1254 static const struct dmi_system_id sysids[] = { 1255 /* Various Lenovo 50 series have LPM issues with older BIOSen */ 1256 { 1257 .matches = { 1258 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1259 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"), 1260 }, 1261 .driver_data = "20180406", /* 1.31 */ 1262 }, 1263 { 1264 .matches = { 1265 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1266 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"), 1267 }, 1268 .driver_data = "20180420", /* 1.28 */ 1269 }, 1270 { 1271 .matches = { 1272 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1273 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"), 1274 }, 1275 .driver_data = "20180315", /* 1.33 */ 1276 }, 1277 { 1278 .matches = { 1279 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1280 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"), 1281 }, 1282 /* 1283 * Note date based on release notes, 2.35 has been 1284 * reported to be good, but I've been unable to get 1285 * a hold of the reporter to get the DMI BIOS date. 1286 * TODO: fix this. 1287 */ 1288 .driver_data = "20180310", /* 2.35 */ 1289 }, 1290 { } /* terminate list */ 1291 }; 1292 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1293 int year, month, date; 1294 char buf[9]; 1295 1296 if (!dmi) 1297 return false; 1298 1299 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); 1300 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); 1301 1302 return strcmp(buf, dmi->driver_data) < 0; 1303} 1304 1305static bool ahci_broken_online(struct pci_dev *pdev) 1306{ 1307#define ENCODE_BUSDEVFN(bus, slot, func) \ 1308 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) 1309 static const struct dmi_system_id sysids[] = { 1310 /* 1311 * There are several gigabyte boards which use 1312 * SIMG5723s configured as hardware RAID. Certain 1313 * 5723 firmware revisions shipped there keep the link 1314 * online but fail to answer properly to SRST or 1315 * IDENTIFY when no device is attached downstream 1316 * causing libata to retry quite a few times leading 1317 * to excessive detection delay. 1318 * 1319 * As these firmwares respond to the second reset try 1320 * with invalid device signature, considering unknown 1321 * sig as offline works around the problem acceptably. 1322 */ 1323 { 1324 .ident = "EP45-DQ6", 1325 .matches = { 1326 DMI_MATCH(DMI_BOARD_VENDOR, 1327 "Gigabyte Technology Co., Ltd."), 1328 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), 1329 }, 1330 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), 1331 }, 1332 { 1333 .ident = "EP45-DS5", 1334 .matches = { 1335 DMI_MATCH(DMI_BOARD_VENDOR, 1336 "Gigabyte Technology Co., Ltd."), 1337 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), 1338 }, 1339 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), 1340 }, 1341 { } /* terminate list */ 1342 }; 1343#undef ENCODE_BUSDEVFN 1344 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1345 unsigned int val; 1346 1347 if (!dmi) 1348 return false; 1349 1350 val = (unsigned long)dmi->driver_data; 1351 1352 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); 1353} 1354 1355static bool ahci_broken_devslp(struct pci_dev *pdev) 1356{ 1357 /* device with broken DEVSLP but still showing SDS capability */ 1358 static const struct pci_device_id ids[] = { 1359 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ 1360 {} 1361 }; 1362 1363 return pci_match_id(ids, pdev); 1364} 1365 1366#ifdef CONFIG_ATA_ACPI 1367static void ahci_gtf_filter_workaround(struct ata_host *host) 1368{ 1369 static const struct dmi_system_id sysids[] = { 1370 /* 1371 * Aspire 3810T issues a bunch of SATA enable commands 1372 * via _GTF including an invalid one and one which is 1373 * rejected by the device. Among the successful ones 1374 * is FPDMA non-zero offset enable which when enabled 1375 * only on the drive side leads to NCQ command 1376 * failures. Filter it out. 1377 */ 1378 { 1379 .ident = "Aspire 3810T", 1380 .matches = { 1381 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1382 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), 1383 }, 1384 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, 1385 }, 1386 { } 1387 }; 1388 const struct dmi_system_id *dmi = dmi_first_match(sysids); 1389 unsigned int filter; 1390 int i; 1391 1392 if (!dmi) 1393 return; 1394 1395 filter = (unsigned long)dmi->driver_data; 1396 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", 1397 filter, dmi->ident); 1398 1399 for (i = 0; i < host->n_ports; i++) { 1400 struct ata_port *ap = host->ports[i]; 1401 struct ata_link *link; 1402 struct ata_device *dev; 1403 1404 ata_for_each_link(link, ap, EDGE) 1405 ata_for_each_dev(dev, link, ALL) 1406 dev->gtf_filter |= filter; 1407 } 1408} 1409#else 1410static inline void ahci_gtf_filter_workaround(struct ata_host *host) 1411{} 1412#endif 1413 1414/* 1415 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected 1416 * as DUMMY, or detected but eventually get a "link down" and never get up 1417 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the 1418 * port_map may hold a value of 0x00. 1419 * 1420 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports 1421 * and can significantly reduce the occurrence of the problem. 1422 * 1423 * https://bugzilla.kernel.org/show_bug.cgi?id=189471 1424 */ 1425static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv, 1426 struct pci_dev *pdev) 1427{ 1428 static const struct dmi_system_id sysids[] = { 1429 { 1430 .ident = "Acer Switch Alpha 12", 1431 .matches = { 1432 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1433 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271") 1434 }, 1435 }, 1436 { } 1437 }; 1438 1439 if (dmi_check_system(sysids)) { 1440 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n"); 1441 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) { 1442 hpriv->port_map = 0x7; 1443 hpriv->cap = 0xC734FF02; 1444 } 1445 } 1446} 1447 1448#ifdef CONFIG_ARM64 1449/* 1450 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently. 1451 * Workaround is to make sure all pending IRQs are served before leaving 1452 * handler. 1453 */ 1454static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) 1455{ 1456 struct ata_host *host = dev_instance; 1457 struct ahci_host_priv *hpriv; 1458 unsigned int rc = 0; 1459 void __iomem *mmio; 1460 u32 irq_stat, irq_masked; 1461 unsigned int handled = 1; 1462 1463 VPRINTK("ENTER\n"); 1464 hpriv = host->private_data; 1465 mmio = hpriv->mmio; 1466 irq_stat = readl(mmio + HOST_IRQ_STAT); 1467 if (!irq_stat) 1468 return IRQ_NONE; 1469 1470 do { 1471 irq_masked = irq_stat & hpriv->port_map; 1472 spin_lock(&host->lock); 1473 rc = ahci_handle_port_intr(host, irq_masked); 1474 if (!rc) 1475 handled = 0; 1476 writel(irq_stat, mmio + HOST_IRQ_STAT); 1477 irq_stat = readl(mmio + HOST_IRQ_STAT); 1478 spin_unlock(&host->lock); 1479 } while (irq_stat); 1480 VPRINTK("EXIT\n"); 1481 1482 return IRQ_RETVAL(handled); 1483} 1484#endif 1485 1486static void ahci_remap_check(struct pci_dev *pdev, int bar, 1487 struct ahci_host_priv *hpriv) 1488{ 1489 int i, count = 0; 1490 u32 cap; 1491 1492 /* 1493 * Check if this device might have remapped nvme devices. 1494 */ 1495 if (pdev->vendor != PCI_VENDOR_ID_INTEL || 1496 pci_resource_len(pdev, bar) < SZ_512K || 1497 bar != AHCI_PCI_BAR_STANDARD || 1498 !(readl(hpriv->mmio + AHCI_VSCAP) & 1)) 1499 return; 1500 1501 cap = readq(hpriv->mmio + AHCI_REMAP_CAP); 1502 for (i = 0; i < AHCI_MAX_REMAP; i++) { 1503 if ((cap & (1 << i)) == 0) 1504 continue; 1505 if (readl(hpriv->mmio + ahci_remap_dcc(i)) 1506 != PCI_CLASS_STORAGE_EXPRESS) 1507 continue; 1508 1509 /* We've found a remapped device */ 1510 count++; 1511 } 1512 1513 if (!count) 1514 return; 1515 1516 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count); 1517 dev_warn(&pdev->dev, 1518 "Switch your BIOS from RAID to AHCI mode to use them.\n"); 1519 1520 /* 1521 * Don't rely on the msi-x capability in the remap case, 1522 * share the legacy interrupt across ahci and remapped devices. 1523 */ 1524 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1525} 1526 1527static int ahci_get_irq_vector(struct ata_host *host, int port) 1528{ 1529 return pci_irq_vector(to_pci_dev(host->dev), port); 1530} 1531 1532static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, 1533 struct ahci_host_priv *hpriv) 1534{ 1535 int nvec; 1536 1537 if (hpriv->flags & AHCI_HFLAG_NO_MSI) 1538 return -ENODEV; 1539 1540 /* 1541 * If number of MSIs is less than number of ports then Sharing Last 1542 * Message mode could be enforced. In this case assume that advantage 1543 * of multipe MSIs is negated and use single MSI mode instead. 1544 */ 1545 if (n_ports > 1) { 1546 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX, 1547 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1548 if (nvec > 0) { 1549 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) { 1550 hpriv->get_irq_vector = ahci_get_irq_vector; 1551 hpriv->flags |= AHCI_HFLAG_MULTI_MSI; 1552 return nvec; 1553 } 1554 1555 /* 1556 * Fallback to single MSI mode if the controller 1557 * enforced MRSM mode. 1558 */ 1559 printk(KERN_INFO 1560 "ahci: MRSM is on, fallback to single MSI\n"); 1561 pci_free_irq_vectors(pdev); 1562 } 1563 } 1564 1565 /* 1566 * If the host is not capable of supporting per-port vectors, fall 1567 * back to single MSI before finally attempting single MSI-X. 1568 */ 1569 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1570 if (nvec == 1) 1571 return nvec; 1572 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 1573} 1574 1575static void ahci_update_initial_lpm_policy(struct ata_port *ap, 1576 struct ahci_host_priv *hpriv) 1577{ 1578 int policy = CONFIG_SATA_MOBILE_LPM_POLICY; 1579 1580 1581 /* Ignore processing for non mobile platforms */ 1582 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE)) 1583 return; 1584 1585 /* user modified policy via module param */ 1586 if (mobile_lpm_policy != -1) { 1587 policy = mobile_lpm_policy; 1588 goto update_policy; 1589 } 1590 1591#ifdef CONFIG_ACPI 1592 if (policy > ATA_LPM_MED_POWER && 1593 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) { 1594 if (hpriv->cap & HOST_CAP_PART) 1595 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL; 1596 else if (hpriv->cap & HOST_CAP_SSC) 1597 policy = ATA_LPM_MIN_POWER; 1598 } 1599#endif 1600 1601update_policy: 1602 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER) 1603 ap->target_lpm_policy = policy; 1604} 1605 1606static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1607{ 1608 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev); 1609 u16 tmp16; 1610 1611 /* 1612 * Only apply the 6-port PCS quirk for known legacy platforms. 1613 */ 1614 if (!id || id->vendor != PCI_VENDOR_ID_INTEL) 1615 return; 1616 1617 /* Skip applying the quirk on Denverton and beyond */ 1618 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7) 1619 return; 1620 1621 /* 1622 * port_map is determined from PORTS_IMPL PCI register which is 1623 * implemented as write or write-once register. If the register 1624 * isn't programmed, ahci automatically generates it from number 1625 * of ports, which is good enough for PCS programming. It is 1626 * otherwise expected that platform firmware enables the ports 1627 * before the OS boots. 1628 */ 1629 pci_read_config_word(pdev, PCS_6, &tmp16); 1630 if ((tmp16 & hpriv->port_map) != hpriv->port_map) { 1631 tmp16 |= hpriv->port_map; 1632 pci_write_config_word(pdev, PCS_6, tmp16); 1633 } 1634} 1635 1636static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1637{ 1638 unsigned int board_id = ent->driver_data; 1639 struct ata_port_info pi = ahci_port_info[board_id]; 1640 const struct ata_port_info *ppi[] = { &pi, NULL }; 1641 struct device *dev = &pdev->dev; 1642 struct ahci_host_priv *hpriv; 1643 struct ata_host *host; 1644 int n_ports, i, rc; 1645 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; 1646 1647 VPRINTK("ENTER\n"); 1648 1649 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); 1650 1651 ata_print_version_once(&pdev->dev, DRV_VERSION); 1652 1653 /* The AHCI driver can only drive the SATA ports, the PATA driver 1654 can drive them all so if both drivers are selected make sure 1655 AHCI stays out of the way */ 1656 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1657 return -ENODEV; 1658 1659 /* Apple BIOS on MCP89 prevents us using AHCI */ 1660 if (is_mcp89_apple(pdev)) 1661 ahci_mcp89_apple_enable(pdev); 1662 1663 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1664 * At the moment, we can only use the AHCI mode. Let the users know 1665 * that for SAS drives they're out of luck. 1666 */ 1667 if (pdev->vendor == PCI_VENDOR_ID_PROMISE) 1668 dev_info(&pdev->dev, 1669 "PDC42819 can only drive SATA devices with this driver\n"); 1670 1671 /* Some devices use non-standard BARs */ 1672 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) 1673 ahci_pci_bar = AHCI_PCI_BAR_STA2X11; 1674 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) 1675 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; 1676 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) { 1677 if (pdev->device == 0xa01c) 1678 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; 1679 if (pdev->device == 0xa084) 1680 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5; 1681 } 1682 1683 /* acquire resources */ 1684 rc = pcim_enable_device(pdev); 1685 if (rc) 1686 return rc; 1687 1688 if (pdev->vendor == PCI_VENDOR_ID_INTEL && 1689 (pdev->device == 0x2652 || pdev->device == 0x2653)) { 1690 u8 map; 1691 1692 /* ICH6s share the same PCI ID for both piix and ahci 1693 * modes. Enabling ahci mode while MAP indicates 1694 * combined mode is a bad idea. Yield to ata_piix. 1695 */ 1696 pci_read_config_byte(pdev, ICH_MAP, &map); 1697 if (map & 0x3) { 1698 dev_info(&pdev->dev, 1699 "controller is in combined mode, can't enable AHCI mode\n"); 1700 return -ENODEV; 1701 } 1702 } 1703 1704 /* AHCI controllers often implement SFF compatible interface. 1705 * Grab all PCI BARs just in case. 1706 */ 1707 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); 1708 if (rc == -EBUSY) 1709 pcim_pin_device(pdev); 1710 if (rc) 1711 return rc; 1712 1713 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1714 if (!hpriv) 1715 return -ENOMEM; 1716 hpriv->flags |= (unsigned long)pi.private_data; 1717 1718 /* MCP65 revision A1 and A2 can't do MSI */ 1719 if (board_id == board_ahci_mcp65 && 1720 (pdev->revision == 0xa1 || pdev->revision == 0xa2)) 1721 hpriv->flags |= AHCI_HFLAG_NO_MSI; 1722 1723 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ 1724 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) 1725 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; 1726 1727 /* only some SB600s can do 64bit DMA */ 1728 if (ahci_sb600_enable_64bit(pdev)) 1729 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; 1730 1731 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; 1732 1733 /* detect remapped nvme devices */ 1734 ahci_remap_check(pdev, ahci_pci_bar, hpriv); 1735 1736 /* must set flag prior to save config in order to take effect */ 1737 if (ahci_broken_devslp(pdev)) 1738 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; 1739 1740#ifdef CONFIG_ARM64 1741 if (pdev->vendor == 0x177d && pdev->device == 0xa01c) 1742 hpriv->irq_handler = ahci_thunderx_irq_handler; 1743#endif 1744 1745 /* save initial config */ 1746 ahci_pci_save_initial_config(pdev, hpriv); 1747 1748 /* 1749 * If platform firmware failed to enable ports, try to enable 1750 * them here. 1751 */ 1752 ahci_intel_pcs_quirk(pdev, hpriv); 1753 1754 /* prepare host */ 1755 if (hpriv->cap & HOST_CAP_NCQ) { 1756 pi.flags |= ATA_FLAG_NCQ; 1757 /* 1758 * Auto-activate optimization is supposed to be 1759 * supported on all AHCI controllers indicating NCQ 1760 * capability, but it seems to be broken on some 1761 * chipsets including NVIDIAs. 1762 */ 1763 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) 1764 pi.flags |= ATA_FLAG_FPDMA_AA; 1765 1766 /* 1767 * All AHCI controllers should be forward-compatible 1768 * with the new auxiliary field. This code should be 1769 * conditionalized if any buggy AHCI controllers are 1770 * encountered. 1771 */ 1772 pi.flags |= ATA_FLAG_FPDMA_AUX; 1773 } 1774 1775 if (hpriv->cap & HOST_CAP_PMP) 1776 pi.flags |= ATA_FLAG_PMP; 1777 1778 ahci_set_em_messages(hpriv, &pi); 1779 1780 if (ahci_broken_system_poweroff(pdev)) { 1781 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; 1782 dev_info(&pdev->dev, 1783 "quirky BIOS, skipping spindown on poweroff\n"); 1784 } 1785 1786 if (ahci_broken_lpm(pdev)) { 1787 pi.flags |= ATA_FLAG_NO_LPM; 1788 dev_warn(&pdev->dev, 1789 "BIOS update required for Link Power Management support\n"); 1790 } 1791 1792 if (ahci_broken_suspend(pdev)) { 1793 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; 1794 dev_warn(&pdev->dev, 1795 "BIOS update required for suspend/resume\n"); 1796 } 1797 1798 if (ahci_broken_online(pdev)) { 1799 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; 1800 dev_info(&pdev->dev, 1801 "online status unreliable, applying workaround\n"); 1802 } 1803 1804 1805 /* Acer SA5-271 workaround modifies private_data */ 1806 acer_sa5_271_workaround(hpriv, pdev); 1807 1808 /* CAP.NP sometimes indicate the index of the last enabled 1809 * port, at other times, that of the last possible port, so 1810 * determining the maximum port number requires looking at 1811 * both CAP.NP and port_map. 1812 */ 1813 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); 1814 1815 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1816 if (!host) 1817 return -ENOMEM; 1818 host->private_data = hpriv; 1819 1820 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) { 1821 /* legacy intx interrupts */ 1822 pci_intx(pdev, 1); 1823 } 1824 hpriv->irq = pci_irq_vector(pdev, 0); 1825 1826 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) 1827 host->flags |= ATA_HOST_PARALLEL_SCAN; 1828 else 1829 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); 1830 1831 if (pi.flags & ATA_FLAG_EM) 1832 ahci_reset_em(host); 1833 1834 for (i = 0; i < host->n_ports; i++) { 1835 struct ata_port *ap = host->ports[i]; 1836 1837 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); 1838 ata_port_pbar_desc(ap, ahci_pci_bar, 1839 0x100 + ap->port_no * 0x80, "port"); 1840 1841 /* set enclosure management message type */ 1842 if (ap->flags & ATA_FLAG_EM) 1843 ap->em_message_type = hpriv->em_msg_type; 1844 1845 ahci_update_initial_lpm_policy(ap, hpriv); 1846 1847 /* disabled/not-implemented port */ 1848 if (!(hpriv->port_map & (1 << i))) 1849 ap->ops = &ata_dummy_port_ops; 1850 } 1851 1852 /* apply workaround for ASUS P5W DH Deluxe mainboard */ 1853 ahci_p5wdh_workaround(host); 1854 1855 /* apply gtf filter quirk */ 1856 ahci_gtf_filter_workaround(host); 1857 1858 /* initialize adapter */ 1859 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); 1860 if (rc) 1861 return rc; 1862 1863 rc = ahci_reset_controller(host); 1864 if (rc) 1865 return rc; 1866 1867 ahci_pci_init_controller(host); 1868 ahci_pci_print_info(host); 1869 1870 pci_set_master(pdev); 1871 1872 rc = ahci_host_activate(host, &ahci_sht); 1873 if (rc) 1874 return rc; 1875 1876 pm_runtime_put_noidle(&pdev->dev); 1877 return 0; 1878} 1879 1880static void ahci_remove_one(struct pci_dev *pdev) 1881{ 1882 pm_runtime_get_noresume(&pdev->dev); 1883 ata_pci_remove_one(pdev); 1884} 1885 1886module_pci_driver(ahci_pci_driver); 1887 1888MODULE_AUTHOR("Jeff Garzik"); 1889MODULE_DESCRIPTION("AHCI SATA low-level driver"); 1890MODULE_LICENSE("GPL"); 1891MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); 1892MODULE_VERSION(DRV_VERSION);