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1Qualcomm SuperSpeed DWC3 USB SoC controller
2
3Required properties:
4- compatible: Compatible list, contains
5 "qcom,dwc3"
6 "qcom,msm8996-dwc3" for msm8996 SOC.
7 "qcom,msm8998-dwc3" for msm8998 SOC.
8 "qcom,sdm845-dwc3" for sdm845 SOC.
9- reg: Offset and length of register set for QSCRATCH wrapper
10- power-domains: specifies a phandle to PM domain provider node
11- clocks: A list of phandle + clock-specifier pairs for the
12 clocks listed in clock-names
13- clock-names: Should contain the following:
14 "core" Master/Core clock, have to be >= 125 MHz for SS
15 operation and >= 60MHz for HS operation
16 "mock_utmi" Mock utmi clock needed for ITP/SOF generation in
17 host mode. Its frequency should be 19.2MHz.
18 "sleep" Sleep clock, used for wakeup when USB3 core goes
19 into low power mode (U3).
20
21Optional clocks:
22 "iface" System bus AXI clock.
23 Not present on "qcom,msm8996-dwc3" compatible.
24 "cfg_noc" System Config NOC clock.
25 Not present on "qcom,msm8996-dwc3" compatible.
26- assigned-clocks: Should be:
27 MOCK_UTMI_CLK
28 MASTER_CLK
29- assigned-clock-rates: Should be:
30 19.2Mhz (192000000) for MOCK_UTMI_CLK
31 >=125Mhz (125000000) for MASTER_CLK in SS mode
32 >=60Mhz (60000000) for MASTER_CLK in HS mode
33
34Optional properties:
35- resets: Phandle to reset control that resets core and wrapper.
36- interrupts: specifies interrupts from controller wrapper used
37 to wakeup from low power/susepnd state. Must contain
38 one or more entry for interrupt-names property
39- interrupt-names: Must include the following entries:
40 - "hs_phy_irq": The interrupt that is asserted when a
41 wakeup event is received on USB2 bus
42 - "ss_phy_irq": The interrupt that is asserted when a
43 wakeup event is received on USB3 bus
44 - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate
45 interrupts for any wakeup event on DM and DP lines
46- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement.
47 Used when dwc3 operates without SSPHY and only
48 HS/FS/LS modes are supported.
49
50Required child node:
51A child node must exist to represent the core DWC3 IP block. The name of
52the node is not important. The content of the node is defined in dwc3.txt.
53
54Phy documentation is provided in the following places:
55Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY
56Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY
57
58Example device nodes:
59
60 hs_phy: phy@100f8800 {
61 compatible = "qcom,qusb2-v2-phy";
62 ...
63 };
64
65 ss_phy: phy@100f8830 {
66 compatible = "qcom,qmp-v3-usb3-phy";
67 ...
68 };
69
70 usb3_0: usb30@a6f8800 {
71 compatible = "qcom,dwc3";
72 reg = <0xa6f8800 0x400>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>;
78 interrupt-names = "hs_phy_irq", "ss_phy_irq",
79 "dm_hs_phy_irq", "dp_hs_phy_irq";
80
81 clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
82 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
83 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
84 clock-names = "core", "mock_utmi", "sleep";
85
86 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
87 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
88 assigned-clock-rates = <19200000>, <133000000>;
89
90 resets = <&gcc GCC_USB30_PRIM_BCR>;
91 reset-names = "core_reset";
92 power-domains = <&gcc USB30_PRIM_GDSC>;
93 qcom,select-utmi-as-pipe-clk;
94
95 dwc3@10000000 {
96 compatible = "snps,dwc3";
97 reg = <0x10000000 0xcd00>;
98 interrupts = <0 205 0x4>;
99 phys = <&hs_phy>, <&ss_phy>;
100 phy-names = "usb2-phy", "usb3-phy";
101 dr_mode = "host";
102 };
103 };
104