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1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2014-2019 MediaTek Inc. 4 * 5 * Author: Tianping.Fang <tianping.fang@mediatek.com> 6 * Sean Wang <sean.wang@mediatek.com> 7 */ 8 9#ifndef _LINUX_MFD_MT6397_RTC_H_ 10#define _LINUX_MFD_MT6397_RTC_H_ 11 12#include <linux/jiffies.h> 13#include <linux/mutex.h> 14#include <linux/regmap.h> 15#include <linux/rtc.h> 16 17#define RTC_BBPU 0x0000 18#define RTC_BBPU_CBUSY BIT(6) 19#define RTC_BBPU_KEY (0x43 << 8) 20 21#define RTC_WRTGR 0x003c 22 23#define RTC_IRQ_STA 0x0002 24#define RTC_IRQ_STA_AL BIT(0) 25#define RTC_IRQ_STA_LP BIT(3) 26 27#define RTC_IRQ_EN 0x0004 28#define RTC_IRQ_EN_AL BIT(0) 29#define RTC_IRQ_EN_ONESHOT BIT(2) 30#define RTC_IRQ_EN_LP BIT(3) 31#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) 32 33#define RTC_AL_MASK 0x0008 34#define RTC_AL_MASK_DOW BIT(4) 35 36#define RTC_TC_SEC 0x000a 37/* Min, Hour, Dom... register offset to RTC_TC_SEC */ 38#define RTC_OFFSET_SEC 0 39#define RTC_OFFSET_MIN 1 40#define RTC_OFFSET_HOUR 2 41#define RTC_OFFSET_DOM 3 42#define RTC_OFFSET_DOW 4 43#define RTC_OFFSET_MTH 5 44#define RTC_OFFSET_YEAR 6 45#define RTC_OFFSET_COUNT 7 46 47#define RTC_AL_SEC 0x0018 48 49#define RTC_PDN2 0x002e 50#define RTC_PDN2_PWRON_ALARM BIT(4) 51 52#define RTC_MIN_YEAR 1968 53#define RTC_BASE_YEAR 1900 54#define RTC_NUM_YEARS 128 55#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR) 56 57#define MTK_RTC_POLL_DELAY_US 10 58#define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ)) 59 60struct mt6397_rtc { 61 struct device *dev; 62 struct rtc_device *rtc_dev; 63 64 /* Protect register access from multiple tasks */ 65 struct mutex lock; 66 struct regmap *regmap; 67 int irq; 68 u32 addr_base; 69}; 70 71#endif /* _LINUX_MFD_MT6397_RTC_H_ */