tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Texas Instruments DP83867 PHY
4 *
5 * Copyright (C) 2015 Texas Instruments Inc.
6 */
7
8#include <linux/ethtool.h>
9#include <linux/kernel.h>
10#include <linux/mii.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/phy.h>
14#include <linux/delay.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17
18#include <dt-bindings/net/ti-dp83867.h>
19
20#define DP83867_PHY_ID 0x2000a231
21#define DP83867_DEVADDR 0x1f
22
23#define MII_DP83867_PHYCTRL 0x10
24#define MII_DP83867_MICR 0x12
25#define MII_DP83867_ISR 0x13
26#define DP83867_CFG2 0x14
27#define DP83867_CFG3 0x1e
28#define DP83867_CTRL 0x1f
29
30/* Extended Registers */
31#define DP83867_CFG4 0x0031
32#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
33#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
34#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
35#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
36#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
37
38#define DP83867_RGMIICTL 0x0032
39#define DP83867_STRAP_STS1 0x006E
40#define DP83867_STRAP_STS2 0x006f
41#define DP83867_RGMIIDCTL 0x0086
42#define DP83867_RXFCFG 0x0134
43#define DP83867_RXFPMD1 0x0136
44#define DP83867_RXFPMD2 0x0137
45#define DP83867_RXFPMD3 0x0138
46#define DP83867_RXFSOP1 0x0139
47#define DP83867_RXFSOP2 0x013A
48#define DP83867_RXFSOP3 0x013B
49#define DP83867_IO_MUX_CFG 0x0170
50#define DP83867_SGMIICTL 0x00D3
51#define DP83867_10M_SGMII_CFG 0x016F
52#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
53
54#define DP83867_SW_RESET BIT(15)
55#define DP83867_SW_RESTART BIT(14)
56
57/* MICR Interrupt bits */
58#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
59#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
60#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
61#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
62#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
63#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
64#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
65#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
66#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
67#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
68#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
69#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
70
71/* RGMIICTL bits */
72#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
73#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
74
75/* SGMIICTL bits */
76#define DP83867_SGMII_TYPE BIT(14)
77
78/* RXFCFG bits*/
79#define DP83867_WOL_MAGIC_EN BIT(0)
80#define DP83867_WOL_BCAST_EN BIT(2)
81#define DP83867_WOL_UCAST_EN BIT(4)
82#define DP83867_WOL_SEC_EN BIT(5)
83#define DP83867_WOL_ENH_MAC BIT(7)
84
85/* STRAP_STS1 bits */
86#define DP83867_STRAP_STS1_RESERVED BIT(11)
87
88/* STRAP_STS2 bits */
89#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
90#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
91#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
92#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
93#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
94
95/* PHY CTRL bits */
96#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
97#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
98#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
99#define DP83867_PHYCR_RESERVED_MASK BIT(11)
100
101/* RGMIIDCTL bits */
102#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
103#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
104#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
105#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
106#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
107#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
108
109
110/* IO_MUX_CFG bits */
111#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
112#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
113#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
114#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
115#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
116#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
117
118/* CFG3 bits */
119#define DP83867_CFG3_INT_OE BIT(7)
120#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
121
122/* CFG4 bits */
123#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
124
125enum {
126 DP83867_PORT_MIRROING_KEEP,
127 DP83867_PORT_MIRROING_EN,
128 DP83867_PORT_MIRROING_DIS,
129};
130
131struct dp83867_private {
132 u32 rx_id_delay;
133 u32 tx_id_delay;
134 u32 fifo_depth;
135 int io_impedance;
136 int port_mirroring;
137 bool rxctrl_strap_quirk;
138 bool set_clk_output;
139 u32 clk_output_sel;
140 bool sgmii_ref_clk_en;
141};
142
143static int dp83867_ack_interrupt(struct phy_device *phydev)
144{
145 int err = phy_read(phydev, MII_DP83867_ISR);
146
147 if (err < 0)
148 return err;
149
150 return 0;
151}
152
153static int dp83867_set_wol(struct phy_device *phydev,
154 struct ethtool_wolinfo *wol)
155{
156 struct net_device *ndev = phydev->attached_dev;
157 u16 val_rxcfg, val_micr;
158 u8 *mac;
159
160 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
161 val_micr = phy_read(phydev, MII_DP83867_MICR);
162
163 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
164 WAKE_BCAST)) {
165 val_rxcfg |= DP83867_WOL_ENH_MAC;
166 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
167
168 if (wol->wolopts & WAKE_MAGIC) {
169 mac = (u8 *)ndev->dev_addr;
170
171 if (!is_valid_ether_addr(mac))
172 return -EINVAL;
173
174 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
175 (mac[1] << 8 | mac[0]));
176 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
177 (mac[3] << 8 | mac[2]));
178 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
179 (mac[5] << 8 | mac[4]));
180
181 val_rxcfg |= DP83867_WOL_MAGIC_EN;
182 } else {
183 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
184 }
185
186 if (wol->wolopts & WAKE_MAGICSECURE) {
187 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
188 (wol->sopass[1] << 8) | wol->sopass[0]);
189 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
190 (wol->sopass[3] << 8) | wol->sopass[2]);
191 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
192 (wol->sopass[5] << 8) | wol->sopass[4]);
193
194 val_rxcfg |= DP83867_WOL_SEC_EN;
195 } else {
196 val_rxcfg &= ~DP83867_WOL_SEC_EN;
197 }
198
199 if (wol->wolopts & WAKE_UCAST)
200 val_rxcfg |= DP83867_WOL_UCAST_EN;
201 else
202 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
203
204 if (wol->wolopts & WAKE_BCAST)
205 val_rxcfg |= DP83867_WOL_BCAST_EN;
206 else
207 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
208 } else {
209 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
210 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
211 }
212
213 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
214 phy_write(phydev, MII_DP83867_MICR, val_micr);
215
216 return 0;
217}
218
219static void dp83867_get_wol(struct phy_device *phydev,
220 struct ethtool_wolinfo *wol)
221{
222 u16 value, sopass_val;
223
224 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
225 WAKE_MAGICSECURE);
226 wol->wolopts = 0;
227
228 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
229
230 if (value & DP83867_WOL_UCAST_EN)
231 wol->wolopts |= WAKE_UCAST;
232
233 if (value & DP83867_WOL_BCAST_EN)
234 wol->wolopts |= WAKE_BCAST;
235
236 if (value & DP83867_WOL_MAGIC_EN)
237 wol->wolopts |= WAKE_MAGIC;
238
239 if (value & DP83867_WOL_SEC_EN) {
240 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
241 DP83867_RXFSOP1);
242 wol->sopass[0] = (sopass_val & 0xff);
243 wol->sopass[1] = (sopass_val >> 8);
244
245 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
246 DP83867_RXFSOP2);
247 wol->sopass[2] = (sopass_val & 0xff);
248 wol->sopass[3] = (sopass_val >> 8);
249
250 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
251 DP83867_RXFSOP3);
252 wol->sopass[4] = (sopass_val & 0xff);
253 wol->sopass[5] = (sopass_val >> 8);
254
255 wol->wolopts |= WAKE_MAGICSECURE;
256 }
257
258 if (!(value & DP83867_WOL_ENH_MAC))
259 wol->wolopts = 0;
260}
261
262static int dp83867_config_intr(struct phy_device *phydev)
263{
264 int micr_status;
265
266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
267 micr_status = phy_read(phydev, MII_DP83867_MICR);
268 if (micr_status < 0)
269 return micr_status;
270
271 micr_status |=
272 (MII_DP83867_MICR_AN_ERR_INT_EN |
273 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
274 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
275 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
276 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
277 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
278
279 return phy_write(phydev, MII_DP83867_MICR, micr_status);
280 }
281
282 micr_status = 0x0;
283 return phy_write(phydev, MII_DP83867_MICR, micr_status);
284}
285
286static int dp83867_config_port_mirroring(struct phy_device *phydev)
287{
288 struct dp83867_private *dp83867 =
289 (struct dp83867_private *)phydev->priv;
290
291 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
292 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
293 DP83867_CFG4_PORT_MIRROR_EN);
294 else
295 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
296 DP83867_CFG4_PORT_MIRROR_EN);
297 return 0;
298}
299
300static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
301{
302 struct dp83867_private *dp83867 = phydev->priv;
303
304 /* Existing behavior was to use default pin strapping delay in rgmii
305 * mode, but rgmii should have meant no delay. Warn existing users.
306 */
307 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
308 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
309 DP83867_STRAP_STS2);
310 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
311 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
312 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
313 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
314
315 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
316 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
317 phydev_warn(phydev,
318 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
319 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
320 txskew, rxskew);
321 }
322
323 /* RX delay *must* be specified if internal delay of RX is used. */
324 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
325 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
326 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
327 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
328 return -EINVAL;
329 }
330
331 /* TX delay *must* be specified if internal delay of TX is used. */
332 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
333 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
334 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
335 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
336 return -EINVAL;
337 }
338
339 return 0;
340}
341
342#ifdef CONFIG_OF_MDIO
343static int dp83867_of_init(struct phy_device *phydev)
344{
345 struct dp83867_private *dp83867 = phydev->priv;
346 struct device *dev = &phydev->mdio.dev;
347 struct device_node *of_node = dev->of_node;
348 int ret;
349
350 if (!of_node)
351 return -ENODEV;
352
353 /* Optional configuration */
354 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
355 &dp83867->clk_output_sel);
356 /* If not set, keep default */
357 if (!ret) {
358 dp83867->set_clk_output = true;
359 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
360 * DP83867_CLK_O_SEL_OFF.
361 */
362 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
363 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
364 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
365 dp83867->clk_output_sel);
366 return -EINVAL;
367 }
368 }
369
370 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
371 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
372 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
373 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
374 else
375 dp83867->io_impedance = -1; /* leave at default */
376
377 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
378 "ti,dp83867-rxctrl-strap-quirk");
379
380 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
381 "ti,sgmii-ref-clock-output-enable");
382
383
384 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
385 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
386 &dp83867->rx_id_delay);
387 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
388 phydev_err(phydev,
389 "ti,rx-internal-delay value of %u out of range\n",
390 dp83867->rx_id_delay);
391 return -EINVAL;
392 }
393
394 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
395 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
396 &dp83867->tx_id_delay);
397 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
398 phydev_err(phydev,
399 "ti,tx-internal-delay value of %u out of range\n",
400 dp83867->tx_id_delay);
401 return -EINVAL;
402 }
403
404 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
405 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
406
407 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
408 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
409
410 ret = of_property_read_u32(of_node, "ti,fifo-depth",
411 &dp83867->fifo_depth);
412 if (ret) {
413 phydev_err(phydev,
414 "ti,fifo-depth property is required\n");
415 return ret;
416 }
417 if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
418 phydev_err(phydev,
419 "ti,fifo-depth value %u out of range\n",
420 dp83867->fifo_depth);
421 return -EINVAL;
422 }
423 return 0;
424}
425#else
426static int dp83867_of_init(struct phy_device *phydev)
427{
428 return 0;
429}
430#endif /* CONFIG_OF_MDIO */
431
432static int dp83867_probe(struct phy_device *phydev)
433{
434 struct dp83867_private *dp83867;
435
436 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
437 GFP_KERNEL);
438 if (!dp83867)
439 return -ENOMEM;
440
441 phydev->priv = dp83867;
442
443 return dp83867_of_init(phydev);
444}
445
446static int dp83867_config_init(struct phy_device *phydev)
447{
448 struct dp83867_private *dp83867 = phydev->priv;
449 int ret, val, bs;
450 u16 delay;
451
452 ret = dp83867_verify_rgmii_cfg(phydev);
453 if (ret)
454 return ret;
455
456 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
457 if (dp83867->rxctrl_strap_quirk)
458 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
459 BIT(7));
460
461 if (phy_interface_is_rgmii(phydev)) {
462 val = phy_read(phydev, MII_DP83867_PHYCTRL);
463 if (val < 0)
464 return val;
465 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
466 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
467
468 /* The code below checks if "port mirroring" N/A MODE4 has been
469 * enabled during power on bootstrap.
470 *
471 * Such N/A mode enabled by mistake can put PHY IC in some
472 * internal testing mode and disable RGMII transmission.
473 *
474 * In this particular case one needs to check STRAP_STS1
475 * register's bit 11 (marked as RESERVED).
476 */
477
478 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
479 if (bs & DP83867_STRAP_STS1_RESERVED)
480 val &= ~DP83867_PHYCR_RESERVED_MASK;
481
482 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
483 if (ret)
484 return ret;
485
486 /* If rgmii mode with no internal delay is selected, we do NOT use
487 * aligned mode as one might expect. Instead we use the PHY's default
488 * based on pin strapping. And the "mode 0" default is to *use*
489 * internal delay with a value of 7 (2.00 ns).
490 *
491 * Set up RGMII delays
492 */
493 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
494
495 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
496 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
497 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
498
499 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
500 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
501
502 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
503 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
504
505 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
506
507 delay = 0;
508 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
509 delay |= dp83867->rx_id_delay;
510 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
511 delay |= dp83867->tx_id_delay <<
512 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
513
514 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
515 delay);
516 }
517
518 /* If specified, set io impedance */
519 if (dp83867->io_impedance >= 0)
520 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
521 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
522 dp83867->io_impedance);
523
524 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
525 /* For support SPEED_10 in SGMII mode
526 * DP83867_10M_SGMII_RATE_ADAPT bit
527 * has to be cleared by software. That
528 * does not affect SPEED_100 and
529 * SPEED_1000.
530 */
531 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
532 DP83867_10M_SGMII_CFG,
533 DP83867_10M_SGMII_RATE_ADAPT_MASK,
534 0);
535 if (ret)
536 return ret;
537
538 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
539 * are 01). That is not enough to finalize autoneg on some
540 * devices. Increase this timer duration to maximum 16ms.
541 */
542 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
543 DP83867_CFG4,
544 DP83867_CFG4_SGMII_ANEG_MASK,
545 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
546
547 if (ret)
548 return ret;
549
550 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
551 /* SGMII type is set to 4-wire mode by default.
552 * If we place appropriate property in dts (see above)
553 * switch on 6-wire mode.
554 */
555 if (dp83867->sgmii_ref_clk_en)
556 val |= DP83867_SGMII_TYPE;
557 else
558 val &= ~DP83867_SGMII_TYPE;
559 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
560 }
561
562 val = phy_read(phydev, DP83867_CFG3);
563 /* Enable Interrupt output INT_OE in CFG3 register */
564 if (phy_interrupt_is_valid(phydev))
565 val |= DP83867_CFG3_INT_OE;
566
567 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
568 phy_write(phydev, DP83867_CFG3, val);
569
570 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
571 dp83867_config_port_mirroring(phydev);
572
573 /* Clock output selection if muxing property is set */
574 if (dp83867->set_clk_output) {
575 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
576
577 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
578 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
579 } else {
580 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
581 val = dp83867->clk_output_sel <<
582 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
583 }
584
585 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
586 mask, val);
587 }
588
589 return 0;
590}
591
592static int dp83867_phy_reset(struct phy_device *phydev)
593{
594 int err;
595
596 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
597 if (err < 0)
598 return err;
599
600 usleep_range(10, 20);
601
602 return 0;
603}
604
605static struct phy_driver dp83867_driver[] = {
606 {
607 .phy_id = DP83867_PHY_ID,
608 .phy_id_mask = 0xfffffff0,
609 .name = "TI DP83867",
610 /* PHY_GBIT_FEATURES */
611
612 .probe = dp83867_probe,
613 .config_init = dp83867_config_init,
614 .soft_reset = dp83867_phy_reset,
615
616 .get_wol = dp83867_get_wol,
617 .set_wol = dp83867_set_wol,
618
619 /* IRQ related */
620 .ack_interrupt = dp83867_ack_interrupt,
621 .config_intr = dp83867_config_intr,
622
623 .suspend = genphy_suspend,
624 .resume = genphy_resume,
625 },
626};
627module_phy_driver(dp83867_driver);
628
629static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
630 { DP83867_PHY_ID, 0xfffffff0 },
631 { }
632};
633
634MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
635
636MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
637MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
638MODULE_LICENSE("GPL v2");