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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM L2 Cache Controller
8
9maintainers:
10 - Rob Herring <robh@kernel.org>
11
12description: |+
13 ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
14 PL220/PL310 and variants) based level 2 cache controller. All these various
15 implementations of the L2 cache controller have compatible programming
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
17 taken from section 3.7.3 of the Devicetree Specification which can be found
18 at:
19 https://www.devicetree.org/specifications/
20
21 Note 1: The description in this document doesn't apply to integrated L2
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23 integrated L2 controllers are assumed to be all preconfigured by
24 early secure boot code. Thus no need to deal with their configuration
25 in the kernel at all.
26
27allOf:
28 - $ref: /schemas/cache-controller.yaml#
29
30properties:
31 compatible:
32 enum:
33 - arm,pl310-cache
34 - arm,l220-cache
35 - arm,l210-cache
36 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
37 - bcm,bcm11351-a2-pl310-cache
38 # For Broadcom bcm11351 chipset where an
39 # offset needs to be added to the address before passing down to the L2
40 # cache controller
41 - brcm,bcm11351-a2-pl310-cache
42 # Marvell Controller designed to be
43 # compatible with the ARM one, with system cache mode (meaning
44 # maintenance operations on L1 are broadcasted to the L2 and L2
45 # performs the same operation).
46 - marvell,aurora-system-cache
47 # Marvell Controller designed to be
48 # compatible with the ARM one with outer cache mode.
49 - marvell,aurora-outer-cache
50 # Marvell Tauros3 cache controller, compatible
51 # with arm,pl310-cache controller.
52 - marvell,tauros3-cache
53
54 cache-level:
55 const: 2
56
57 cache-unified: true
58 cache-size: true
59 cache-sets: true
60 cache-block-size: true
61 cache-line-size: true
62
63 reg:
64 maxItems: 1
65
66 arm,data-latency:
67 description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
68 read, write and setup latencies. Minimum valid values are 1. Controllers
69 without setup latency control should use a value of 0.
70 allOf:
71 - $ref: /schemas/types.yaml#/definitions/uint32-array
72 - minItems: 2
73 maxItems: 3
74 items:
75 minimum: 0
76 maximum: 8
77
78 arm,tag-latency:
79 description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
80 read, write and setup latencies. Controllers without setup latency control
81 should use 0. Controllers without separate read and write Tag RAM latency
82 values should only use the first cell.
83 allOf:
84 - $ref: /schemas/types.yaml#/definitions/uint32-array
85 - minItems: 1
86 maxItems: 3
87 items:
88 minimum: 0
89 maximum: 8
90
91 arm,dirty-latency:
92 description: Cycles of latency for Dirty RAMs. This is a single cell.
93 allOf:
94 - $ref: /schemas/types.yaml#/definitions/uint32
95 - minimum: 1
96 maximum: 8
97
98 arm,filter-ranges:
99 description: <start length> Starting address and length of window to
100 filter. Addresses in the filter window are directed to the M1 port. Other
101 addresses will go to the M0 port.
102 allOf:
103 - $ref: /schemas/types.yaml#/definitions/uint32-array
104 - items:
105 minItems: 2
106 maxItems: 2
107
108 arm,io-coherent:
109 description: indicates that the system is operating in an hardware
110 I/O coherent mode. Valid only when the arm,pl310-cache compatible
111 string is used.
112 type: boolean
113
114 interrupts:
115 # Either a single combined interrupt or up to 9 individual interrupts
116 minItems: 1
117 maxItems: 9
118
119 cache-id-part:
120 description: cache id part number to be used if it is not present
121 on hardware
122 $ref: /schemas/types.yaml#/definitions/uint32
123
124 wt-override:
125 description: If present then L2 is forced to Write through mode
126 type: boolean
127
128 arm,double-linefill:
129 description: Override double linefill enable setting. Enable if
130 non-zero, disable if zero.
131 allOf:
132 - $ref: /schemas/types.yaml#/definitions/uint32
133 - enum: [ 0, 1 ]
134
135 arm,double-linefill-incr:
136 description: Override double linefill on INCR read. Enable
137 if non-zero, disable if zero.
138 allOf:
139 - $ref: /schemas/types.yaml#/definitions/uint32
140 - enum: [ 0, 1 ]
141
142 arm,double-linefill-wrap:
143 description: Override double linefill on WRAP read. Enable
144 if non-zero, disable if zero.
145 allOf:
146 - $ref: /schemas/types.yaml#/definitions/uint32
147 - enum: [ 0, 1 ]
148
149 arm,prefetch-drop:
150 description: Override prefetch drop enable setting. Enable if non-zero,
151 disable if zero.
152 allOf:
153 - $ref: /schemas/types.yaml#/definitions/uint32
154 - enum: [ 0, 1 ]
155
156 arm,prefetch-offset:
157 description: Override prefetch offset value.
158 allOf:
159 - $ref: /schemas/types.yaml#/definitions/uint32
160 - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
161
162 arm,shared-override:
163 description: The default behavior of the L220 or PL310 cache
164 controllers with respect to the shareable attribute is to transform "normal
165 memory non-cacheable transactions" into "cacheable no allocate" (for reads)
166 or "write through no write allocate" (for writes).
167 On systems where this may cause DMA buffer corruption, this property must
168 be specified to indicate that such transforms are precluded.
169 type: boolean
170
171 arm,parity-enable:
172 description: enable parity checking on the L2 cache (L220 or PL310).
173 type: boolean
174
175 arm,parity-disable:
176 description: disable parity checking on the L2 cache (L220 or PL310).
177 type: boolean
178
179 marvell,ecc-enable:
180 description: enable ECC protection on the L2 cache
181 type: boolean
182
183 arm,outer-sync-disable:
184 description: disable the outer sync operation on the L2 cache.
185 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
186 will randomly hang unless outer sync operations are disabled.
187 type: boolean
188
189 prefetch-data:
190 description: |
191 Data prefetch. Value: <0> (forcibly disable), <1>
192 (forcibly enable), property absent (retain settings set by firmware)
193 allOf:
194 - $ref: /schemas/types.yaml#/definitions/uint32
195 - enum: [ 0, 1 ]
196
197 prefetch-instr:
198 description: |
199 Instruction prefetch. Value: <0> (forcibly disable),
200 <1> (forcibly enable), property absent (retain settings set by
201 firmware)
202 allOf:
203 - $ref: /schemas/types.yaml#/definitions/uint32
204 - enum: [ 0, 1 ]
205
206 arm,dynamic-clock-gating:
207 description: |
208 L2 dynamic clock gating. Value: <0> (forcibly
209 disable), <1> (forcibly enable), property absent (OS specific behavior,
210 preferably retain firmware settings)
211 allOf:
212 - $ref: /schemas/types.yaml#/definitions/uint32
213 - enum: [ 0, 1 ]
214
215 arm,standby-mode:
216 description: L2 standby mode enable. Value <0> (forcibly disable),
217 <1> (forcibly enable), property absent (OS specific behavior,
218 preferably retain firmware settings)
219 allOf:
220 - $ref: /schemas/types.yaml#/definitions/uint32
221 - enum: [ 0, 1 ]
222
223 arm,early-bresp-disable:
224 description: Disable the CA9 optimization Early BRESP (PL310)
225 type: boolean
226
227 arm,full-line-zero-disable:
228 description: Disable the CA9 optimization Full line of zero
229 write (PL310)
230 type: boolean
231
232required:
233 - compatible
234 - cache-unified
235 - reg
236
237additionalProperties: false
238
239examples:
240 - |
241 cache-controller@fff12000 {
242 compatible = "arm,pl310-cache";
243 reg = <0xfff12000 0x1000>;
244 arm,data-latency = <1 1 1>;
245 arm,tag-latency = <2 2 2>;
246 arm,filter-ranges = <0x80000000 0x8000000>;
247 cache-unified;
248 cache-level = <2>;
249 interrupts = <45>;
250 };
251
252...