tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Low-level API.
4 *
5 * Copyright (c) 2017-2018, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
7 */
8#ifndef WFX_HWIO_H
9#define WFX_HWIO_H
10
11#include <linux/types.h>
12
13struct wfx_dev;
14
15int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
16int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
17
18int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
19int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
20
21int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
22int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
23
24int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
25int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
26
27int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
28int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
29
30#define CFG_ERR_SPI_FRAME 0x00000001 // only with SPI
31#define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 // only with SDIO
32#define CFG_ERR_BUF_UNDERRUN 0x00000002
33#define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
34#define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
35#define CFG_ERR_BUF_OVERRUN 0x00000010
36#define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
37#define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
38#define CFG_ERR_HOST_CRC_MISS 0x00000080 // only with SDIO
39#define CFG_SPI_IGNORE_CS 0x00000080 // only with SPI
40/* Bytes ordering (only writable in SPI): */
41#define CFG_WORD_MODE_MASK 0x00000300
42/*
43 * B1,B0,B3,B2 (In SPI, register address and
44 * CONFIG data always use this mode)
45 */
46#define CFG_WORD_MODE0 0x00000000
47#define CFG_WORD_MODE1 0x00000100 // B3,B2,B1,B0
48#define CFG_WORD_MODE2 0x00000200 // B0,B1,B2,B3 (SDIO)
49#define CFG_DIRECT_ACCESS_MODE 0x00000400 // Direct or queue access mode
50#define CFG_PREFETCH_AHB 0x00000800
51#define CFG_DISABLE_CPU_CLK 0x00001000
52#define CFG_PREFETCH_SRAM 0x00002000
53#define CFG_CPU_RESET 0x00004000
54#define CFG_SDIO_DISABLE_IRQ 0x00008000 // only with SDIO
55#define CFG_IRQ_ENABLE_DATA 0x00010000
56#define CFG_IRQ_ENABLE_WRDY 0x00020000
57#define CFG_CLK_RISE_EDGE 0x00040000
58#define CFG_SDIO_DISABLE_CRC_CHK 0x00080000 // only with SDIO
59#define CFG_RESERVED 0x00F00000
60#define CFG_DEVICE_ID_MAJOR 0x07000000
61#define CFG_DEVICE_ID_RESERVED 0x78000000
62#define CFG_DEVICE_ID_TYPE 0x80000000
63int config_reg_read(struct wfx_dev *wdev, u32 *val);
64int config_reg_write(struct wfx_dev *wdev, u32 val);
65int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
66
67#define CTRL_NEXT_LEN_MASK 0x00000FFF
68#define CTRL_WLAN_WAKEUP 0x00001000
69#define CTRL_WLAN_READY 0x00002000
70int control_reg_read(struct wfx_dev *wdev, u32 *val);
71int control_reg_write(struct wfx_dev *wdev, u32 val);
72int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
73
74#define IGPR_RW 0x80000000
75#define IGPR_INDEX 0x7F000000
76#define IGPR_VALUE 0x00FFFFFF
77int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
78int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
79
80#endif /* WFX_HWIO_H */