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1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type {
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
184};
185
186enum atom_dp_vs_preemph_def{
187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
197};
198
199
200/*
201enum atom_string_def{
202asic_bus_type_pcie_string = "PCI_EXPRESS",
203atom_fire_gl_string = "FGL",
204atom_bios_string = "ATOM"
205};
206*/
207
208#pragma pack(1) /* BIOS data must use byte aligment*/
209
210enum atombios_image_offset{
211OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
212OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
213OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
214MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
215OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
216OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
217};
218
219/****************************************************************************
220* Common header for all tables (Data table, Command function).
221* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
222* And the pointer actually points to this header.
223****************************************************************************/
224
225struct atom_common_table_header
226{
227 uint16_t structuresize;
228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
230};
231
232/****************************************************************************
233* Structure stores the ROM header.
234****************************************************************************/
235struct atom_rom_header_v2_2
236{
237 struct atom_common_table_header table_header;
238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
239 uint16_t bios_segment_address;
240 uint16_t protectedmodeoffset;
241 uint16_t configfilenameoffset;
242 uint16_t crc_block_offset;
243 uint16_t vbios_bootupmessageoffset;
244 uint16_t int10_offset;
245 uint16_t pcibusdevinitcode;
246 uint16_t iobaseaddress;
247 uint16_t subsystem_vendor_id;
248 uint16_t subsystem_id;
249 uint16_t pci_info_offset;
250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
252 uint16_t reserved;
253 uint32_t pspdirtableoffset;
254};
255
256/*==============================hw function portion======================================================================*/
257
258
259/****************************************************************************
260* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
261* The real functionality of each function is associated with the parameter structure version when defined
262* For all internal cmd function definitions, please reference to atomstruct.h
263****************************************************************************/
264struct atom_master_list_of_command_functions_v2_1{
265 uint16_t asic_init; //Function
266 uint16_t cmd_function1; //used as an internal one
267 uint16_t cmd_function2; //used as an internal one
268 uint16_t cmd_function3; //used as an internal one
269 uint16_t digxencodercontrol; //Function
270 uint16_t cmd_function5; //used as an internal one
271 uint16_t cmd_function6; //used as an internal one
272 uint16_t cmd_function7; //used as an internal one
273 uint16_t cmd_function8; //used as an internal one
274 uint16_t cmd_function9; //used as an internal one
275 uint16_t setengineclock; //Function
276 uint16_t setmemoryclock; //Function
277 uint16_t setpixelclock; //Function
278 uint16_t enabledisppowergating; //Function
279 uint16_t cmd_function14; //used as an internal one
280 uint16_t cmd_function15; //used as an internal one
281 uint16_t cmd_function16; //used as an internal one
282 uint16_t cmd_function17; //used as an internal one
283 uint16_t cmd_function18; //used as an internal one
284 uint16_t cmd_function19; //used as an internal one
285 uint16_t cmd_function20; //used as an internal one
286 uint16_t cmd_function21; //used as an internal one
287 uint16_t cmd_function22; //used as an internal one
288 uint16_t cmd_function23; //used as an internal one
289 uint16_t cmd_function24; //used as an internal one
290 uint16_t cmd_function25; //used as an internal one
291 uint16_t cmd_function26; //used as an internal one
292 uint16_t cmd_function27; //used as an internal one
293 uint16_t cmd_function28; //used as an internal one
294 uint16_t cmd_function29; //used as an internal one
295 uint16_t cmd_function30; //used as an internal one
296 uint16_t cmd_function31; //used as an internal one
297 uint16_t cmd_function32; //used as an internal one
298 uint16_t cmd_function33; //used as an internal one
299 uint16_t blankcrtc; //Function
300 uint16_t enablecrtc; //Function
301 uint16_t cmd_function36; //used as an internal one
302 uint16_t cmd_function37; //used as an internal one
303 uint16_t cmd_function38; //used as an internal one
304 uint16_t cmd_function39; //used as an internal one
305 uint16_t cmd_function40; //used as an internal one
306 uint16_t getsmuclockinfo; //Function
307 uint16_t selectcrtc_source; //Function
308 uint16_t cmd_function43; //used as an internal one
309 uint16_t cmd_function44; //used as an internal one
310 uint16_t cmd_function45; //used as an internal one
311 uint16_t setdceclock; //Function
312 uint16_t getmemoryclock; //Function
313 uint16_t getengineclock; //Function
314 uint16_t setcrtc_usingdtdtiming; //Function
315 uint16_t externalencodercontrol; //Function
316 uint16_t cmd_function51; //used as an internal one
317 uint16_t cmd_function52; //used as an internal one
318 uint16_t cmd_function53; //used as an internal one
319 uint16_t processi2cchanneltransaction;//Function
320 uint16_t cmd_function55; //used as an internal one
321 uint16_t cmd_function56; //used as an internal one
322 uint16_t cmd_function57; //used as an internal one
323 uint16_t cmd_function58; //used as an internal one
324 uint16_t cmd_function59; //used as an internal one
325 uint16_t computegpuclockparam; //Function
326 uint16_t cmd_function61; //used as an internal one
327 uint16_t cmd_function62; //used as an internal one
328 uint16_t dynamicmemorysettings; //Function function
329 uint16_t memorytraining; //Function function
330 uint16_t cmd_function65; //used as an internal one
331 uint16_t cmd_function66; //used as an internal one
332 uint16_t setvoltage; //Function
333 uint16_t cmd_function68; //used as an internal one
334 uint16_t readefusevalue; //Function
335 uint16_t cmd_function70; //used as an internal one
336 uint16_t cmd_function71; //used as an internal one
337 uint16_t cmd_function72; //used as an internal one
338 uint16_t cmd_function73; //used as an internal one
339 uint16_t cmd_function74; //used as an internal one
340 uint16_t cmd_function75; //used as an internal one
341 uint16_t dig1transmittercontrol; //Function
342 uint16_t cmd_function77; //used as an internal one
343 uint16_t processauxchanneltransaction;//Function
344 uint16_t cmd_function79; //used as an internal one
345 uint16_t getvoltageinfo; //Function
346};
347
348struct atom_master_command_function_v2_1
349{
350 struct atom_common_table_header table_header;
351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
352};
353
354/****************************************************************************
355* Structures used in every command function
356****************************************************************************/
357struct atom_function_attribute
358{
359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
362};
363
364
365/****************************************************************************
366* Common header for all hw functions.
367* Every function pointed by _master_list_of_hw_function has this common header.
368* And the pointer actually points to this header.
369****************************************************************************/
370struct atom_rom_hw_function_header
371{
372 struct atom_common_table_header func_header;
373 struct atom_function_attribute func_attrib;
374};
375
376
377/*==============================sw data table portion======================================================================*/
378/****************************************************************************
379* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
380* The real name of each table is given when its data structure version is defined
381****************************************************************************/
382struct atom_master_list_of_data_tables_v2_1{
383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
384 uint16_t multimedia_info;
385 uint16_t smc_dpm_info;
386 uint16_t sw_datatable3;
387 uint16_t firmwareinfo; /* Shared by various SW components */
388 uint16_t sw_datatable5;
389 uint16_t lcd_info; /* Shared by various SW components */
390 uint16_t sw_datatable7;
391 uint16_t smu_info;
392 uint16_t sw_datatable9;
393 uint16_t sw_datatable10;
394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
395 uint16_t gpio_pin_lut; /* Shared by various SW components */
396 uint16_t sw_datatable13;
397 uint16_t gfx_info;
398 uint16_t powerplayinfo; /* Shared by various SW components */
399 uint16_t sw_datatable16;
400 uint16_t sw_datatable17;
401 uint16_t sw_datatable18;
402 uint16_t sw_datatable19;
403 uint16_t sw_datatable20;
404 uint16_t sw_datatable21;
405 uint16_t displayobjectinfo; /* Shared by various SW components */
406 uint16_t indirectioaccess; /* used as an internal one */
407 uint16_t umc_info; /* Shared by various SW components */
408 uint16_t sw_datatable25;
409 uint16_t sw_datatable26;
410 uint16_t dce_info; /* Shared by various SW components */
411 uint16_t vram_info; /* Shared by various SW components */
412 uint16_t sw_datatable29;
413 uint16_t integratedsysteminfo; /* Shared by various SW components */
414 uint16_t asic_profiling_info; /* Shared by various SW components */
415 uint16_t voltageobject_info; /* shared by various SW components */
416 uint16_t sw_datatable33;
417 uint16_t sw_datatable34;
418};
419
420
421struct atom_master_data_table_v2_1
422{
423 struct atom_common_table_header table_header;
424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
425};
426
427
428struct atom_dtd_format
429{
430 uint16_t pixclk;
431 uint16_t h_active;
432 uint16_t h_blanking_time;
433 uint16_t v_active;
434 uint16_t v_blanking_time;
435 uint16_t h_sync_offset;
436 uint16_t h_sync_width;
437 uint16_t v_sync_offset;
438 uint16_t v_syncwidth;
439 uint16_t reserved;
440 uint16_t reserved0;
441 uint8_t h_border;
442 uint8_t v_border;
443 uint16_t miscinfo;
444 uint8_t atom_mode_id;
445 uint8_t refreshrate;
446};
447
448/* atom_dtd_format.modemiscinfo defintion */
449enum atom_dtd_format_modemiscinfo{
450 ATOM_HSYNC_POLARITY = 0x0002,
451 ATOM_VSYNC_POLARITY = 0x0004,
452 ATOM_H_REPLICATIONBY2 = 0x0010,
453 ATOM_V_REPLICATIONBY2 = 0x0020,
454 ATOM_INTERLACE = 0x0080,
455 ATOM_COMPOSITESYNC = 0x0040,
456};
457
458
459/* utilitypipeline
460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
461 * the location of it can't change
462*/
463
464
465/*
466 ***************************************************************************
467 Data Table firmwareinfo structure
468 ***************************************************************************
469*/
470
471struct atom_firmware_info_v3_1
472{
473 struct atom_common_table_header table_header;
474 uint32_t firmware_revision;
475 uint32_t bootup_sclk_in10khz;
476 uint32_t bootup_mclk_in10khz;
477 uint32_t firmware_capability; // enum atombios_firmware_capability
478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
480 uint16_t bootup_vddc_mv;
481 uint16_t bootup_vddci_mv;
482 uint16_t bootup_mvddc_mv;
483 uint16_t bootup_vddgfx_mv;
484 uint8_t mem_module_id;
485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
486 uint8_t reserved1[2];
487 uint32_t mc_baseaddr_high;
488 uint32_t mc_baseaddr_low;
489 uint32_t reserved2[6];
490};
491
492/* Total 32bit cap indication */
493enum atombios_firmware_capability
494{
495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
501 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
502};
503
504enum atom_cooling_solution_id{
505 AIR_COOLING = 0x00,
506 LIQUID_COOLING = 0x01
507};
508
509struct atom_firmware_info_v3_2 {
510 struct atom_common_table_header table_header;
511 uint32_t firmware_revision;
512 uint32_t bootup_sclk_in10khz;
513 uint32_t bootup_mclk_in10khz;
514 uint32_t firmware_capability; // enum atombios_firmware_capability
515 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
516 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
517 uint16_t bootup_vddc_mv;
518 uint16_t bootup_vddci_mv;
519 uint16_t bootup_mvddc_mv;
520 uint16_t bootup_vddgfx_mv;
521 uint8_t mem_module_id;
522 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
523 uint8_t reserved1[2];
524 uint32_t mc_baseaddr_high;
525 uint32_t mc_baseaddr_low;
526 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
527 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
528 uint8_t board_i2c_feature_slave_addr;
529 uint8_t reserved3;
530 uint16_t bootup_mvddq_mv;
531 uint16_t bootup_mvpp_mv;
532 uint32_t zfbstartaddrin16mb;
533 uint32_t reserved2[3];
534};
535
536struct atom_firmware_info_v3_3
537{
538 struct atom_common_table_header table_header;
539 uint32_t firmware_revision;
540 uint32_t bootup_sclk_in10khz;
541 uint32_t bootup_mclk_in10khz;
542 uint32_t firmware_capability; // enum atombios_firmware_capability
543 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
544 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
545 uint16_t bootup_vddc_mv;
546 uint16_t bootup_vddci_mv;
547 uint16_t bootup_mvddc_mv;
548 uint16_t bootup_vddgfx_mv;
549 uint8_t mem_module_id;
550 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
551 uint8_t reserved1[2];
552 uint32_t mc_baseaddr_high;
553 uint32_t mc_baseaddr_low;
554 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
555 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
556 uint8_t board_i2c_feature_slave_addr;
557 uint8_t reserved3;
558 uint16_t bootup_mvddq_mv;
559 uint16_t bootup_mvpp_mv;
560 uint32_t zfbstartaddrin16mb;
561 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
562 uint32_t reserved2[2];
563};
564
565/*
566 ***************************************************************************
567 Data Table lcd_info structure
568 ***************************************************************************
569*/
570
571struct lcd_info_v2_1
572{
573 struct atom_common_table_header table_header;
574 struct atom_dtd_format lcd_timing;
575 uint16_t backlight_pwm;
576 uint16_t special_handle_cap;
577 uint16_t panel_misc;
578 uint16_t lvds_max_slink_pclk;
579 uint16_t lvds_ss_percentage;
580 uint16_t lvds_ss_rate_10hz;
581 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
582 uint8_t pwr_on_de_to_vary_bl;
583 uint8_t pwr_down_vary_bloff_to_de;
584 uint8_t pwr_down_de_to_digoff;
585 uint8_t pwr_off_delay;
586 uint8_t pwr_on_vary_bl_to_blon;
587 uint8_t pwr_down_bloff_to_vary_bloff;
588 uint8_t panel_bpc;
589 uint8_t dpcd_edp_config_cap;
590 uint8_t dpcd_max_link_rate;
591 uint8_t dpcd_max_lane_count;
592 uint8_t dpcd_max_downspread;
593 uint8_t min_allowed_bl_level;
594 uint8_t max_allowed_bl_level;
595 uint8_t bootup_bl_level;
596 uint8_t dplvdsrxid;
597 uint32_t reserved1[8];
598};
599
600/* lcd_info_v2_1.panel_misc defintion */
601enum atom_lcd_info_panel_misc{
602 ATOM_PANEL_MISC_FPDI =0x0002,
603};
604
605//uceDPToLVDSRxId
606enum atom_lcd_info_dptolvds_rx_id
607{
608 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
609 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
610 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
611};
612
613
614/*
615 ***************************************************************************
616 Data Table gpio_pin_lut structure
617 ***************************************************************************
618*/
619
620struct atom_gpio_pin_assignment
621{
622 uint32_t data_a_reg_index;
623 uint8_t gpio_bitshift;
624 uint8_t gpio_mask_bitshift;
625 uint8_t gpio_id;
626 uint8_t reserved;
627};
628
629/* atom_gpio_pin_assignment.gpio_id definition */
630enum atom_gpio_pin_assignment_gpio_id {
631 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
632 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
633 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
634
635 /* gpio_id pre-define id for multiple usage */
636 /* GPIO use to control PCIE_VDDC in certain SLT board */
637 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
638 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
639 PP_AC_DC_SWITCH_GPIO_PINID = 60,
640 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
641 VDDC_VRHOT_GPIO_PINID = 61,
642 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
643 VDDC_PCC_GPIO_PINID = 62,
644 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
645 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
646 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
647 DRAM_SELF_REFRESH_GPIO_PINID = 64,
648 /* Thermal interrupt output->system thermal chip GPIO pin */
649 THERMAL_INT_OUTPUT_GPIO_PINID =65,
650};
651
652
653struct atom_gpio_pin_lut_v2_1
654{
655 struct atom_common_table_header table_header;
656 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
657 struct atom_gpio_pin_assignment gpio_pin[8];
658};
659
660
661/*
662 ***************************************************************************
663 Data Table vram_usagebyfirmware structure
664 ***************************************************************************
665*/
666
667struct vram_usagebyfirmware_v2_1
668{
669 struct atom_common_table_header table_header;
670 uint32_t start_address_in_kb;
671 uint16_t used_by_firmware_in_kb;
672 uint16_t used_by_driver_in_kb;
673};
674
675/* This is part of vram_usagebyfirmware_v2_1 */
676struct vram_reserve_block
677{
678 uint32_t start_address_in_kb;
679 uint16_t used_by_firmware_in_kb;
680 uint16_t used_by_driver_in_kb;
681};
682
683/* Definitions for constance */
684enum atomfirmware_internal_constants
685{
686 ONE_KiB = 0x400,
687 ONE_MiB = 0x100000,
688};
689
690/*
691 ***************************************************************************
692 Data Table displayobjectinfo structure
693 ***************************************************************************
694*/
695
696enum atom_object_record_type_id
697{
698 ATOM_I2C_RECORD_TYPE =1,
699 ATOM_HPD_INT_RECORD_TYPE =2,
700 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
701 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
702 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
703 ATOM_ENCODER_CAP_RECORD_TYPE=20,
704 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
705 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
706 ATOM_RECORD_END_TYPE =0xFF,
707};
708
709struct atom_common_record_header
710{
711 uint8_t record_type; //An emun to indicate the record type
712 uint8_t record_size; //The size of the whole record in byte
713};
714
715struct atom_i2c_record
716{
717 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
718 uint8_t i2c_id;
719 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
720};
721
722struct atom_hpd_int_record
723{
724 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
725 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
726 uint8_t plugin_pin_state;
727};
728
729// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
730enum atom_encoder_caps_def
731{
732 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
733 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
734 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
735 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
736 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
737 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
738};
739
740struct atom_encoder_caps_record
741{
742 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
743 uint32_t encodercaps;
744};
745
746enum atom_connector_caps_def
747{
748 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
749 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
750};
751
752struct atom_disp_connector_caps_record
753{
754 struct atom_common_record_header record_header;
755 uint32_t connectcaps;
756};
757
758//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
759struct atom_gpio_pin_control_pair
760{
761 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
762 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
763};
764
765struct atom_object_gpio_cntl_record
766{
767 struct atom_common_record_header record_header;
768 uint8_t flag; // Future expnadibility
769 uint8_t number_of_pins; // Number of GPIO pins used to control the object
770 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
771};
772
773//Definitions for GPIO pin state
774enum atom_gpio_pin_control_pinstate_def
775{
776 GPIO_PIN_TYPE_INPUT = 0x00,
777 GPIO_PIN_TYPE_OUTPUT = 0x10,
778 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
779
780//For GPIO_PIN_TYPE_OUTPUT the following is defined
781 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
782 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
783 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
784 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
785};
786
787// Indexes to GPIO array in GLSync record
788// GLSync record is for Frame Lock/Gen Lock feature.
789enum atom_glsync_record_gpio_index_def
790{
791 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
792 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
793 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
794 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
795 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
796 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
797 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
798 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
799 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
800 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
801};
802
803
804struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
805{
806 struct atom_common_record_header record_header;
807 uint8_t hpd_pin_map[8];
808};
809
810struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
811{
812 struct atom_common_record_header record_header;
813 uint8_t aux_ddc_map[8];
814};
815
816struct atom_connector_forced_tmds_cap_record
817{
818 struct atom_common_record_header record_header;
819 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
820 uint8_t maxtmdsclkrate_in2_5mhz;
821 uint8_t reserved;
822};
823
824struct atom_connector_layout_info
825{
826 uint16_t connectorobjid;
827 uint8_t connector_type;
828 uint8_t position;
829};
830
831// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
832enum atom_connector_layout_info_connector_type_def
833{
834 CONNECTOR_TYPE_DVI_D = 1,
835
836 CONNECTOR_TYPE_HDMI = 4,
837 CONNECTOR_TYPE_DISPLAY_PORT = 5,
838 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
839};
840
841struct atom_bracket_layout_record
842{
843 struct atom_common_record_header record_header;
844 uint8_t bracketlen;
845 uint8_t bracketwidth;
846 uint8_t conn_num;
847 uint8_t reserved;
848 struct atom_connector_layout_info conn_info[1];
849};
850
851enum atom_display_device_tag_def{
852 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
853 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
854 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
855 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
856 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
857 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
858 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
859 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
860};
861
862struct atom_display_object_path_v2
863{
864 uint16_t display_objid; //Connector Object ID or Misc Object ID
865 uint16_t disp_recordoffset;
866 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
867 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
868 uint16_t encoder_recordoffset;
869 uint16_t extencoder_recordoffset;
870 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
871 uint8_t priority_id;
872 uint8_t reserved;
873};
874
875struct display_object_info_table_v1_4
876{
877 struct atom_common_table_header table_header;
878 uint16_t supporteddevices;
879 uint8_t number_of_path;
880 uint8_t reserved;
881 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
882};
883
884
885/*
886 ***************************************************************************
887 Data Table dce_info structure
888 ***************************************************************************
889*/
890struct atom_display_controller_info_v4_1
891{
892 struct atom_common_table_header table_header;
893 uint32_t display_caps;
894 uint32_t bootup_dispclk_10khz;
895 uint16_t dce_refclk_10khz;
896 uint16_t i2c_engine_refclk_10khz;
897 uint16_t dvi_ss_percentage; // in unit of 0.001%
898 uint16_t dvi_ss_rate_10hz;
899 uint16_t hdmi_ss_percentage; // in unit of 0.001%
900 uint16_t hdmi_ss_rate_10hz;
901 uint16_t dp_ss_percentage; // in unit of 0.001%
902 uint16_t dp_ss_rate_10hz;
903 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
904 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
905 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
906 uint8_t ss_reserved;
907 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
908 uint8_t reserved1[3];
909 uint16_t dpphy_refclk_10khz;
910 uint16_t reserved2;
911 uint8_t dceip_min_ver;
912 uint8_t dceip_max_ver;
913 uint8_t max_disp_pipe_num;
914 uint8_t max_vbios_active_disp_pipe_num;
915 uint8_t max_ppll_num;
916 uint8_t max_disp_phy_num;
917 uint8_t max_aux_pairs;
918 uint8_t remotedisplayconfig;
919 uint8_t reserved3[8];
920};
921
922
923struct atom_display_controller_info_v4_2
924{
925 struct atom_common_table_header table_header;
926 uint32_t display_caps;
927 uint32_t bootup_dispclk_10khz;
928 uint16_t dce_refclk_10khz;
929 uint16_t i2c_engine_refclk_10khz;
930 uint16_t dvi_ss_percentage; // in unit of 0.001%
931 uint16_t dvi_ss_rate_10hz;
932 uint16_t hdmi_ss_percentage; // in unit of 0.001%
933 uint16_t hdmi_ss_rate_10hz;
934 uint16_t dp_ss_percentage; // in unit of 0.001%
935 uint16_t dp_ss_rate_10hz;
936 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
937 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
938 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
939 uint8_t ss_reserved;
940 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
941 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
942 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
943 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
944 uint16_t dpphy_refclk_10khz;
945 uint16_t reserved2;
946 uint8_t dcnip_min_ver;
947 uint8_t dcnip_max_ver;
948 uint8_t max_disp_pipe_num;
949 uint8_t max_vbios_active_disp_pipe_num;
950 uint8_t max_ppll_num;
951 uint8_t max_disp_phy_num;
952 uint8_t max_aux_pairs;
953 uint8_t remotedisplayconfig;
954 uint8_t reserved3[8];
955};
956
957
958enum dce_info_caps_def
959{
960 // only for VBIOS
961 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
962 // only for VBIOS
963 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
964 // only for VBIOS
965 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
966
967};
968
969/*
970 ***************************************************************************
971 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
972 ***************************************************************************
973*/
974struct atom_ext_display_path
975{
976 uint16_t device_tag; //A bit vector to show what devices are supported
977 uint16_t device_acpi_enum; //16bit device ACPI id.
978 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
979 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
980 uint8_t hpdlut_index; //An index into external HPD pin LUT
981 uint16_t ext_encoder_objid; //external encoder object id
982 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
983 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
984 uint16_t caps;
985 uint16_t reserved;
986};
987
988//usCaps
989enum ext_display_path_cap_def
990{
991 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
992 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
993 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
994};
995
996struct atom_external_display_connection_info
997{
998 struct atom_common_table_header table_header;
999 uint8_t guid[16]; // a GUID is a 16 byte long string
1000 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
1001 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1002 uint8_t stereopinid; // use for eDP panel
1003 uint8_t remotedisplayconfig;
1004 uint8_t edptolvdsrxid;
1005 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1006 uint8_t reserved[3]; // for potential expansion
1007};
1008
1009/*
1010 ***************************************************************************
1011 Data Table integratedsysteminfo structure
1012 ***************************************************************************
1013*/
1014
1015struct atom_camera_dphy_timing_param
1016{
1017 uint8_t profile_id; // SENSOR_PROFILES
1018 uint32_t param;
1019};
1020
1021struct atom_camera_dphy_elec_param
1022{
1023 uint16_t param[3];
1024};
1025
1026struct atom_camera_module_info
1027{
1028 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1029 uint8_t module_name[8];
1030 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1031};
1032
1033struct atom_camera_flashlight_info
1034{
1035 uint8_t flashlight_id; // 0: Rear, 1: Front
1036 uint8_t name[8];
1037};
1038
1039struct atom_camera_data
1040{
1041 uint32_t versionCode;
1042 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1043 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1044 struct atom_camera_dphy_elec_param dphy_param;
1045 uint32_t crc_val; // CRC
1046};
1047
1048
1049struct atom_14nm_dpphy_dvihdmi_tuningset
1050{
1051 uint32_t max_symclk_in10khz;
1052 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1053 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1054 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1055 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1056 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1057 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1058 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1059};
1060
1061struct atom_14nm_dpphy_dp_setting{
1062 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1063 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1064 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1065 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1066};
1067
1068struct atom_14nm_dpphy_dp_tuningset{
1069 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1070 uint8_t version;
1071 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1072 uint16_t reserved;
1073 struct atom_14nm_dpphy_dp_setting dptuning[10];
1074};
1075
1076struct atom_14nm_dig_transmitter_info_header_v4_0{
1077 struct atom_common_table_header table_header;
1078 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1079 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1080 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1081};
1082
1083struct atom_14nm_combphy_tmds_vs_set
1084{
1085 uint8_t sym_clk;
1086 uint8_t dig_mode;
1087 uint8_t phy_sel;
1088 uint16_t common_mar_deemph_nom__margin_deemph_val;
1089 uint8_t common_seldeemph60__deemph_6db_4_val;
1090 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1091 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1092 uint8_t margin_deemph_lane0__deemph_sel_val;
1093};
1094
1095struct atom_i2c_reg_info {
1096 uint8_t ucI2cRegIndex;
1097 uint8_t ucI2cRegVal;
1098};
1099
1100struct atom_hdmi_retimer_redriver_set {
1101 uint8_t HdmiSlvAddr;
1102 uint8_t HdmiRegNum;
1103 uint8_t Hdmi6GRegNum;
1104 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1105 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1106};
1107
1108struct atom_integrated_system_info_v1_11
1109{
1110 struct atom_common_table_header table_header;
1111 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1112 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1113 uint32_t system_config;
1114 uint32_t cpucapinfo;
1115 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1116 uint16_t gpuclk_ss_type;
1117 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1118 uint16_t lvds_ss_rate_10hz;
1119 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1120 uint16_t hdmi_ss_rate_10hz;
1121 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1122 uint16_t dvi_ss_rate_10hz;
1123 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1124 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1125 uint16_t backlight_pwm_hz; // pwm frequency in hz
1126 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1127 uint8_t umachannelnumber; // number of memory channels
1128 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1129 uint8_t pwr_on_de_to_vary_bl;
1130 uint8_t pwr_down_vary_bloff_to_de;
1131 uint8_t pwr_down_de_to_digoff;
1132 uint8_t pwr_off_delay;
1133 uint8_t pwr_on_vary_bl_to_blon;
1134 uint8_t pwr_down_bloff_to_vary_bloff;
1135 uint8_t min_allowed_bl_level;
1136 uint8_t htc_hyst_limit;
1137 uint8_t htc_tmp_limit;
1138 uint8_t reserved1;
1139 uint8_t reserved2;
1140 struct atom_external_display_connection_info extdispconninfo;
1141 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1142 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1143 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1144 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1145 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1146 struct atom_camera_data camera_info;
1147 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1148 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1149 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1150 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1151 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1152 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1153 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1154 uint32_t reserved[66];
1155};
1156
1157
1158// system_config
1159enum atom_system_vbiosmisc_def{
1160 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1161};
1162
1163
1164// gpucapinfo
1165enum atom_system_gpucapinf_def{
1166 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1167};
1168
1169//dpphy_override
1170enum atom_sysinfo_dpphy_override_def{
1171 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1172 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1173 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1174 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1175 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1176};
1177
1178//lvds_misc
1179enum atom_sys_info_lvds_misc_def
1180{
1181 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1182 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1183 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1184};
1185
1186
1187//memorytype DMI Type 17 offset 12h - Memory Type
1188enum atom_dmi_t17_mem_type_def{
1189 OtherMemType = 0x01, ///< Assign 01 to Other
1190 UnknownMemType, ///< Assign 02 to Unknown
1191 DramMemType, ///< Assign 03 to DRAM
1192 EdramMemType, ///< Assign 04 to EDRAM
1193 VramMemType, ///< Assign 05 to VRAM
1194 SramMemType, ///< Assign 06 to SRAM
1195 RamMemType, ///< Assign 07 to RAM
1196 RomMemType, ///< Assign 08 to ROM
1197 FlashMemType, ///< Assign 09 to Flash
1198 EepromMemType, ///< Assign 10 to EEPROM
1199 FepromMemType, ///< Assign 11 to FEPROM
1200 EpromMemType, ///< Assign 12 to EPROM
1201 CdramMemType, ///< Assign 13 to CDRAM
1202 ThreeDramMemType, ///< Assign 14 to 3DRAM
1203 SdramMemType, ///< Assign 15 to SDRAM
1204 SgramMemType, ///< Assign 16 to SGRAM
1205 RdramMemType, ///< Assign 17 to RDRAM
1206 DdrMemType, ///< Assign 18 to DDR
1207 Ddr2MemType, ///< Assign 19 to DDR2
1208 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1209 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1210 Fbd2MemType, ///< Assign 25 to FBD2
1211 Ddr4MemType, ///< Assign 26 to DDR4
1212 LpDdrMemType, ///< Assign 27 to LPDDR
1213 LpDdr2MemType, ///< Assign 28 to LPDDR2
1214 LpDdr3MemType, ///< Assign 29 to LPDDR3
1215 LpDdr4MemType, ///< Assign 30 to LPDDR4
1216};
1217
1218
1219// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1220struct atom_fusion_system_info_v4
1221{
1222 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1223 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1224};
1225
1226
1227/*
1228 ***************************************************************************
1229 Data Table gfx_info structure
1230 ***************************************************************************
1231*/
1232
1233struct atom_gfx_info_v2_2
1234{
1235 struct atom_common_table_header table_header;
1236 uint8_t gfxip_min_ver;
1237 uint8_t gfxip_max_ver;
1238 uint8_t max_shader_engines;
1239 uint8_t max_tile_pipes;
1240 uint8_t max_cu_per_sh;
1241 uint8_t max_sh_per_se;
1242 uint8_t max_backends_per_se;
1243 uint8_t max_texture_channel_caches;
1244 uint32_t regaddr_cp_dma_src_addr;
1245 uint32_t regaddr_cp_dma_src_addr_hi;
1246 uint32_t regaddr_cp_dma_dst_addr;
1247 uint32_t regaddr_cp_dma_dst_addr_hi;
1248 uint32_t regaddr_cp_dma_command;
1249 uint32_t regaddr_cp_status;
1250 uint32_t regaddr_rlc_gpu_clock_32;
1251 uint32_t rlc_gpu_timer_refclk;
1252};
1253
1254struct atom_gfx_info_v2_3 {
1255 struct atom_common_table_header table_header;
1256 uint8_t gfxip_min_ver;
1257 uint8_t gfxip_max_ver;
1258 uint8_t max_shader_engines;
1259 uint8_t max_tile_pipes;
1260 uint8_t max_cu_per_sh;
1261 uint8_t max_sh_per_se;
1262 uint8_t max_backends_per_se;
1263 uint8_t max_texture_channel_caches;
1264 uint32_t regaddr_cp_dma_src_addr;
1265 uint32_t regaddr_cp_dma_src_addr_hi;
1266 uint32_t regaddr_cp_dma_dst_addr;
1267 uint32_t regaddr_cp_dma_dst_addr_hi;
1268 uint32_t regaddr_cp_dma_command;
1269 uint32_t regaddr_cp_status;
1270 uint32_t regaddr_rlc_gpu_clock_32;
1271 uint32_t rlc_gpu_timer_refclk;
1272 uint8_t active_cu_per_sh;
1273 uint8_t active_rb_per_se;
1274 uint16_t gcgoldenoffset;
1275 uint32_t rm21_sram_vmin_value;
1276};
1277
1278struct atom_gfx_info_v2_4
1279{
1280 struct atom_common_table_header table_header;
1281 uint8_t gfxip_min_ver;
1282 uint8_t gfxip_max_ver;
1283 uint8_t max_shader_engines;
1284 uint8_t reserved;
1285 uint8_t max_cu_per_sh;
1286 uint8_t max_sh_per_se;
1287 uint8_t max_backends_per_se;
1288 uint8_t max_texture_channel_caches;
1289 uint32_t regaddr_cp_dma_src_addr;
1290 uint32_t regaddr_cp_dma_src_addr_hi;
1291 uint32_t regaddr_cp_dma_dst_addr;
1292 uint32_t regaddr_cp_dma_dst_addr_hi;
1293 uint32_t regaddr_cp_dma_command;
1294 uint32_t regaddr_cp_status;
1295 uint32_t regaddr_rlc_gpu_clock_32;
1296 uint32_t rlc_gpu_timer_refclk;
1297 uint8_t active_cu_per_sh;
1298 uint8_t active_rb_per_se;
1299 uint16_t gcgoldenoffset;
1300 uint16_t gc_num_gprs;
1301 uint16_t gc_gsprim_buff_depth;
1302 uint16_t gc_parameter_cache_depth;
1303 uint16_t gc_wave_size;
1304 uint16_t gc_max_waves_per_simd;
1305 uint16_t gc_lds_size;
1306 uint8_t gc_num_max_gs_thds;
1307 uint8_t gc_gs_table_depth;
1308 uint8_t gc_double_offchip_lds_buffer;
1309 uint8_t gc_max_scratch_slots_per_cu;
1310 uint32_t sram_rm_fuses_val;
1311 uint32_t sram_custom_rm_fuses_val;
1312};
1313
1314/*
1315 ***************************************************************************
1316 Data Table smu_info structure
1317 ***************************************************************************
1318*/
1319struct atom_smu_info_v3_1
1320{
1321 struct atom_common_table_header table_header;
1322 uint8_t smuip_min_ver;
1323 uint8_t smuip_max_ver;
1324 uint8_t smu_rsd1;
1325 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1326 uint16_t sclk_ss_percentage;
1327 uint16_t sclk_ss_rate_10hz;
1328 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1329 uint16_t gpuclk_ss_rate_10hz;
1330 uint32_t core_refclk_10khz;
1331 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1332 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1333 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1334 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1335 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1336 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1337 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1338 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1339};
1340
1341struct atom_smu_info_v3_2 {
1342 struct atom_common_table_header table_header;
1343 uint8_t smuip_min_ver;
1344 uint8_t smuip_max_ver;
1345 uint8_t smu_rsd1;
1346 uint8_t gpuclk_ss_mode;
1347 uint16_t sclk_ss_percentage;
1348 uint16_t sclk_ss_rate_10hz;
1349 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1350 uint16_t gpuclk_ss_rate_10hz;
1351 uint32_t core_refclk_10khz;
1352 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1353 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1354 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1355 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1356 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1357 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1358 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1359 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1360 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1361 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1362 uint16_t smugoldenoffset;
1363 uint32_t gpupll_vco_freq_10khz;
1364 uint32_t bootup_smnclk_10khz;
1365 uint32_t bootup_socclk_10khz;
1366 uint32_t bootup_mp0clk_10khz;
1367 uint32_t bootup_mp1clk_10khz;
1368 uint32_t bootup_lclk_10khz;
1369 uint32_t bootup_dcefclk_10khz;
1370 uint32_t ctf_threshold_override_value;
1371 uint32_t reserved[5];
1372};
1373
1374struct atom_smu_info_v3_3 {
1375 struct atom_common_table_header table_header;
1376 uint8_t smuip_min_ver;
1377 uint8_t smuip_max_ver;
1378 uint8_t waflclk_ss_mode;
1379 uint8_t gpuclk_ss_mode;
1380 uint16_t sclk_ss_percentage;
1381 uint16_t sclk_ss_rate_10hz;
1382 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1383 uint16_t gpuclk_ss_rate_10hz;
1384 uint32_t core_refclk_10khz;
1385 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1386 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1387 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1388 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1389 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1390 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1391 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1392 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1393 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1394 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1395 uint16_t smugoldenoffset;
1396 uint32_t gpupll_vco_freq_10khz;
1397 uint32_t bootup_smnclk_10khz;
1398 uint32_t bootup_socclk_10khz;
1399 uint32_t bootup_mp0clk_10khz;
1400 uint32_t bootup_mp1clk_10khz;
1401 uint32_t bootup_lclk_10khz;
1402 uint32_t bootup_dcefclk_10khz;
1403 uint32_t ctf_threshold_override_value;
1404 uint32_t syspll3_0_vco_freq_10khz;
1405 uint32_t syspll3_1_vco_freq_10khz;
1406 uint32_t bootup_fclk_10khz;
1407 uint32_t bootup_waflclk_10khz;
1408 uint32_t smu_info_caps;
1409 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1410 uint16_t smuinitoffset;
1411 uint32_t reserved;
1412};
1413
1414/*
1415 ***************************************************************************
1416 Data Table smc_dpm_info structure
1417 ***************************************************************************
1418 */
1419struct atom_smc_dpm_info_v4_1
1420{
1421 struct atom_common_table_header table_header;
1422 uint8_t liquid1_i2c_address;
1423 uint8_t liquid2_i2c_address;
1424 uint8_t vr_i2c_address;
1425 uint8_t plx_i2c_address;
1426
1427 uint8_t liquid_i2c_linescl;
1428 uint8_t liquid_i2c_linesda;
1429 uint8_t vr_i2c_linescl;
1430 uint8_t vr_i2c_linesda;
1431
1432 uint8_t plx_i2c_linescl;
1433 uint8_t plx_i2c_linesda;
1434 uint8_t vrsensorpresent;
1435 uint8_t liquidsensorpresent;
1436
1437 uint16_t maxvoltagestepgfx;
1438 uint16_t maxvoltagestepsoc;
1439
1440 uint8_t vddgfxvrmapping;
1441 uint8_t vddsocvrmapping;
1442 uint8_t vddmem0vrmapping;
1443 uint8_t vddmem1vrmapping;
1444
1445 uint8_t gfxulvphasesheddingmask;
1446 uint8_t soculvphasesheddingmask;
1447 uint8_t padding8_v[2];
1448
1449 uint16_t gfxmaxcurrent;
1450 uint8_t gfxoffset;
1451 uint8_t padding_telemetrygfx;
1452
1453 uint16_t socmaxcurrent;
1454 uint8_t socoffset;
1455 uint8_t padding_telemetrysoc;
1456
1457 uint16_t mem0maxcurrent;
1458 uint8_t mem0offset;
1459 uint8_t padding_telemetrymem0;
1460
1461 uint16_t mem1maxcurrent;
1462 uint8_t mem1offset;
1463 uint8_t padding_telemetrymem1;
1464
1465 uint8_t acdcgpio;
1466 uint8_t acdcpolarity;
1467 uint8_t vr0hotgpio;
1468 uint8_t vr0hotpolarity;
1469
1470 uint8_t vr1hotgpio;
1471 uint8_t vr1hotpolarity;
1472 uint8_t padding1;
1473 uint8_t padding2;
1474
1475 uint8_t ledpin0;
1476 uint8_t ledpin1;
1477 uint8_t ledpin2;
1478 uint8_t padding8_4;
1479
1480 uint8_t pllgfxclkspreadenabled;
1481 uint8_t pllgfxclkspreadpercent;
1482 uint16_t pllgfxclkspreadfreq;
1483
1484 uint8_t uclkspreadenabled;
1485 uint8_t uclkspreadpercent;
1486 uint16_t uclkspreadfreq;
1487
1488 uint8_t socclkspreadenabled;
1489 uint8_t socclkspreadpercent;
1490 uint16_t socclkspreadfreq;
1491
1492 uint8_t acggfxclkspreadenabled;
1493 uint8_t acggfxclkspreadpercent;
1494 uint16_t acggfxclkspreadfreq;
1495
1496 uint8_t Vr2_I2C_address;
1497 uint8_t padding_vr2[3];
1498
1499 uint32_t boardreserved[9];
1500};
1501
1502/*
1503 ***************************************************************************
1504 Data Table smc_dpm_info structure
1505 ***************************************************************************
1506 */
1507struct atom_smc_dpm_info_v4_3
1508{
1509 struct atom_common_table_header table_header;
1510 uint8_t liquid1_i2c_address;
1511 uint8_t liquid2_i2c_address;
1512 uint8_t vr_i2c_address;
1513 uint8_t plx_i2c_address;
1514
1515 uint8_t liquid_i2c_linescl;
1516 uint8_t liquid_i2c_linesda;
1517 uint8_t vr_i2c_linescl;
1518 uint8_t vr_i2c_linesda;
1519
1520 uint8_t plx_i2c_linescl;
1521 uint8_t plx_i2c_linesda;
1522 uint8_t vrsensorpresent;
1523 uint8_t liquidsensorpresent;
1524
1525 uint16_t maxvoltagestepgfx;
1526 uint16_t maxvoltagestepsoc;
1527
1528 uint8_t vddgfxvrmapping;
1529 uint8_t vddsocvrmapping;
1530 uint8_t vddmem0vrmapping;
1531 uint8_t vddmem1vrmapping;
1532
1533 uint8_t gfxulvphasesheddingmask;
1534 uint8_t soculvphasesheddingmask;
1535 uint8_t externalsensorpresent;
1536 uint8_t padding8_v;
1537
1538 uint16_t gfxmaxcurrent;
1539 uint8_t gfxoffset;
1540 uint8_t padding_telemetrygfx;
1541
1542 uint16_t socmaxcurrent;
1543 uint8_t socoffset;
1544 uint8_t padding_telemetrysoc;
1545
1546 uint16_t mem0maxcurrent;
1547 uint8_t mem0offset;
1548 uint8_t padding_telemetrymem0;
1549
1550 uint16_t mem1maxcurrent;
1551 uint8_t mem1offset;
1552 uint8_t padding_telemetrymem1;
1553
1554 uint8_t acdcgpio;
1555 uint8_t acdcpolarity;
1556 uint8_t vr0hotgpio;
1557 uint8_t vr0hotpolarity;
1558
1559 uint8_t vr1hotgpio;
1560 uint8_t vr1hotpolarity;
1561 uint8_t padding1;
1562 uint8_t padding2;
1563
1564 uint8_t ledpin0;
1565 uint8_t ledpin1;
1566 uint8_t ledpin2;
1567 uint8_t padding8_4;
1568
1569 uint8_t pllgfxclkspreadenabled;
1570 uint8_t pllgfxclkspreadpercent;
1571 uint16_t pllgfxclkspreadfreq;
1572
1573 uint8_t uclkspreadenabled;
1574 uint8_t uclkspreadpercent;
1575 uint16_t uclkspreadfreq;
1576
1577 uint8_t fclkspreadenabled;
1578 uint8_t fclkspreadpercent;
1579 uint16_t fclkspreadfreq;
1580
1581 uint8_t fllgfxclkspreadenabled;
1582 uint8_t fllgfxclkspreadpercent;
1583 uint16_t fllgfxclkspreadfreq;
1584
1585 uint32_t boardreserved[10];
1586};
1587
1588struct smudpm_i2ccontrollerconfig_t {
1589 uint32_t enabled;
1590 uint32_t slaveaddress;
1591 uint32_t controllerport;
1592 uint32_t controllername;
1593 uint32_t thermalthrottler;
1594 uint32_t i2cprotocol;
1595 uint32_t i2cspeed;
1596};
1597
1598struct atom_smc_dpm_info_v4_4
1599{
1600 struct atom_common_table_header table_header;
1601 uint32_t i2c_padding[3];
1602
1603 uint16_t maxvoltagestepgfx;
1604 uint16_t maxvoltagestepsoc;
1605
1606 uint8_t vddgfxvrmapping;
1607 uint8_t vddsocvrmapping;
1608 uint8_t vddmem0vrmapping;
1609 uint8_t vddmem1vrmapping;
1610
1611 uint8_t gfxulvphasesheddingmask;
1612 uint8_t soculvphasesheddingmask;
1613 uint8_t externalsensorpresent;
1614 uint8_t padding8_v;
1615
1616 uint16_t gfxmaxcurrent;
1617 uint8_t gfxoffset;
1618 uint8_t padding_telemetrygfx;
1619
1620 uint16_t socmaxcurrent;
1621 uint8_t socoffset;
1622 uint8_t padding_telemetrysoc;
1623
1624 uint16_t mem0maxcurrent;
1625 uint8_t mem0offset;
1626 uint8_t padding_telemetrymem0;
1627
1628 uint16_t mem1maxcurrent;
1629 uint8_t mem1offset;
1630 uint8_t padding_telemetrymem1;
1631
1632
1633 uint8_t acdcgpio;
1634 uint8_t acdcpolarity;
1635 uint8_t vr0hotgpio;
1636 uint8_t vr0hotpolarity;
1637
1638 uint8_t vr1hotgpio;
1639 uint8_t vr1hotpolarity;
1640 uint8_t padding1;
1641 uint8_t padding2;
1642
1643
1644 uint8_t ledpin0;
1645 uint8_t ledpin1;
1646 uint8_t ledpin2;
1647 uint8_t padding8_4;
1648
1649
1650 uint8_t pllgfxclkspreadenabled;
1651 uint8_t pllgfxclkspreadpercent;
1652 uint16_t pllgfxclkspreadfreq;
1653
1654
1655 uint8_t uclkspreadenabled;
1656 uint8_t uclkspreadpercent;
1657 uint16_t uclkspreadfreq;
1658
1659
1660 uint8_t fclkspreadenabled;
1661 uint8_t fclkspreadpercent;
1662 uint16_t fclkspreadfreq;
1663
1664
1665 uint8_t fllgfxclkspreadenabled;
1666 uint8_t fllgfxclkspreadpercent;
1667 uint16_t fllgfxclkspreadfreq;
1668
1669
1670 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
1671
1672
1673 uint32_t boardreserved[10];
1674};
1675
1676enum smudpm_v4_5_i2ccontrollername_e{
1677 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
1678 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
1679 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
1680 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
1681 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
1682 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
1683 SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
1684 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
1685 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
1686};
1687
1688enum smudpm_v4_5_i2ccontrollerthrottler_e{
1689 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
1690 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
1691 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
1692 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
1693 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
1694 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
1695 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
1696 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
1697 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
1698};
1699
1700enum smudpm_v4_5_i2ccontrollerprotocol_e{
1701 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
1702 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
1703 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
1704 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
1705 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
1706 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
1707 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
1708};
1709
1710struct smudpm_i2c_controller_config_v2
1711{
1712 uint8_t Enabled;
1713 uint8_t Speed;
1714 uint8_t Padding[2];
1715 uint32_t SlaveAddress;
1716 uint8_t ControllerPort;
1717 uint8_t ControllerName;
1718 uint8_t ThermalThrotter;
1719 uint8_t I2cProtocol;
1720};
1721
1722struct atom_smc_dpm_info_v4_5
1723{
1724 struct atom_common_table_header table_header;
1725 // SECTION: BOARD PARAMETERS
1726 // I2C Control
1727 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
1728
1729 // SVI2 Board Parameters
1730 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1731 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1732
1733 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1734 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1735 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1736 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1737
1738 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1739 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1740 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1741 uint8_t Padding8_V;
1742
1743 // Telemetry Settings
1744 uint16_t GfxMaxCurrent; // in Amps
1745 uint8_t GfxOffset; // in Amps
1746 uint8_t Padding_TelemetryGfx;
1747 uint16_t SocMaxCurrent; // in Amps
1748 uint8_t SocOffset; // in Amps
1749 uint8_t Padding_TelemetrySoc;
1750
1751 uint16_t Mem0MaxCurrent; // in Amps
1752 uint8_t Mem0Offset; // in Amps
1753 uint8_t Padding_TelemetryMem0;
1754
1755 uint16_t Mem1MaxCurrent; // in Amps
1756 uint8_t Mem1Offset; // in Amps
1757 uint8_t Padding_TelemetryMem1;
1758
1759 // GPIO Settings
1760 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1761 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1762 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1763 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1764
1765 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
1766 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
1767 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1768 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1769
1770 // LED Display Settings
1771 uint8_t LedPin0; // GPIO number for LedPin[0]
1772 uint8_t LedPin1; // GPIO number for LedPin[1]
1773 uint8_t LedPin2; // GPIO number for LedPin[2]
1774 uint8_t padding8_4;
1775
1776 // GFXCLK PLL Spread Spectrum
1777 uint8_t PllGfxclkSpreadEnabled; // on or off
1778 uint8_t PllGfxclkSpreadPercent; // Q4.4
1779 uint16_t PllGfxclkSpreadFreq; // kHz
1780
1781 // GFXCLK DFLL Spread Spectrum
1782 uint8_t DfllGfxclkSpreadEnabled; // on or off
1783 uint8_t DfllGfxclkSpreadPercent; // Q4.4
1784 uint16_t DfllGfxclkSpreadFreq; // kHz
1785
1786 // UCLK Spread Spectrum
1787 uint8_t UclkSpreadEnabled; // on or off
1788 uint8_t UclkSpreadPercent; // Q4.4
1789 uint16_t UclkSpreadFreq; // kHz
1790
1791 // SOCCLK Spread Spectrum
1792 uint8_t SoclkSpreadEnabled; // on or off
1793 uint8_t SocclkSpreadPercent; // Q4.4
1794 uint16_t SocclkSpreadFreq; // kHz
1795
1796 // Total board power
1797 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
1798 uint16_t BoardPadding;
1799
1800 // Mvdd Svi2 Div Ratio Setting
1801 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
1802
1803 uint32_t BoardReserved[9];
1804
1805};
1806
1807struct atom_smc_dpm_info_v4_6
1808{
1809 struct atom_common_table_header table_header;
1810 // section: board parameters
1811 uint32_t i2c_padding[3]; // old i2c control are moved to new area
1812
1813 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1814 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1815
1816 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
1817 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
1818 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
1819 uint8_t boardvrmapping; // use vr_mapping* bitfields
1820
1821 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1822 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
1823 uint8_t padding8_v[2];
1824
1825 // telemetry settings
1826 uint16_t gfxmaxcurrent; // in amps
1827 uint8_t gfxoffset; // in amps
1828 uint8_t padding_telemetrygfx;
1829
1830 uint16_t socmaxcurrent; // in amps
1831 uint8_t socoffset; // in amps
1832 uint8_t padding_telemetrysoc;
1833
1834 uint16_t memmaxcurrent; // in amps
1835 uint8_t memoffset; // in amps
1836 uint8_t padding_telemetrymem;
1837
1838 uint16_t boardmaxcurrent; // in amps
1839 uint8_t boardoffset; // in amps
1840 uint8_t padding_telemetryboardinput;
1841
1842 // gpio settings
1843 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
1844 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
1845 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
1846 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
1847
1848 // gfxclk pll spread spectrum
1849 uint8_t pllgfxclkspreadenabled; // on or off
1850 uint8_t pllgfxclkspreadpercent; // q4.4
1851 uint16_t pllgfxclkspreadfreq; // khz
1852
1853 // uclk spread spectrum
1854 uint8_t uclkspreadenabled; // on or off
1855 uint8_t uclkspreadpercent; // q4.4
1856 uint16_t uclkspreadfreq; // khz
1857
1858 // fclk spread spectrum
1859 uint8_t fclkspreadenabled; // on or off
1860 uint8_t fclkspreadpercent; // q4.4
1861 uint16_t fclkspreadfreq; // khz
1862
1863
1864 // gfxclk fll spread spectrum
1865 uint8_t fllgfxclkspreadenabled; // on or off
1866 uint8_t fllgfxclkspreadpercent; // q4.4
1867 uint16_t fllgfxclkspreadfreq; // khz
1868
1869 // i2c controller structure
1870 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
1871
1872 // memory section
1873 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
1874
1875 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
1876 uint8_t paddingmem[3];
1877
1878 // total board power
1879 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power
1880 uint16_t boardpadding;
1881
1882 // section: xgmi training
1883 uint8_t xgmilinkspeed[4];
1884 uint8_t xgmilinkwidth[4];
1885
1886 uint16_t xgmifclkfreq[4];
1887 uint16_t xgmisocvoltage[4];
1888
1889 // reserved
1890 uint32_t boardreserved[10];
1891};
1892
1893/*
1894 ***************************************************************************
1895 Data Table asic_profiling_info structure
1896 ***************************************************************************
1897*/
1898struct atom_asic_profiling_info_v4_1
1899{
1900 struct atom_common_table_header table_header;
1901 uint32_t maxvddc;
1902 uint32_t minvddc;
1903 uint32_t avfs_meannsigma_acontant0;
1904 uint32_t avfs_meannsigma_acontant1;
1905 uint32_t avfs_meannsigma_acontant2;
1906 uint16_t avfs_meannsigma_dc_tol_sigma;
1907 uint16_t avfs_meannsigma_platform_mean;
1908 uint16_t avfs_meannsigma_platform_sigma;
1909 uint32_t gb_vdroop_table_cksoff_a0;
1910 uint32_t gb_vdroop_table_cksoff_a1;
1911 uint32_t gb_vdroop_table_cksoff_a2;
1912 uint32_t gb_vdroop_table_ckson_a0;
1913 uint32_t gb_vdroop_table_ckson_a1;
1914 uint32_t gb_vdroop_table_ckson_a2;
1915 uint32_t avfsgb_fuse_table_cksoff_m1;
1916 uint32_t avfsgb_fuse_table_cksoff_m2;
1917 uint32_t avfsgb_fuse_table_cksoff_b;
1918 uint32_t avfsgb_fuse_table_ckson_m1;
1919 uint32_t avfsgb_fuse_table_ckson_m2;
1920 uint32_t avfsgb_fuse_table_ckson_b;
1921 uint16_t max_voltage_0_25mv;
1922 uint8_t enable_gb_vdroop_table_cksoff;
1923 uint8_t enable_gb_vdroop_table_ckson;
1924 uint8_t enable_gb_fuse_table_cksoff;
1925 uint8_t enable_gb_fuse_table_ckson;
1926 uint16_t psm_age_comfactor;
1927 uint8_t enable_apply_avfs_cksoff_voltage;
1928 uint8_t reserved;
1929 uint32_t dispclk2gfxclk_a;
1930 uint32_t dispclk2gfxclk_b;
1931 uint32_t dispclk2gfxclk_c;
1932 uint32_t pixclk2gfxclk_a;
1933 uint32_t pixclk2gfxclk_b;
1934 uint32_t pixclk2gfxclk_c;
1935 uint32_t dcefclk2gfxclk_a;
1936 uint32_t dcefclk2gfxclk_b;
1937 uint32_t dcefclk2gfxclk_c;
1938 uint32_t phyclk2gfxclk_a;
1939 uint32_t phyclk2gfxclk_b;
1940 uint32_t phyclk2gfxclk_c;
1941};
1942
1943struct atom_asic_profiling_info_v4_2 {
1944 struct atom_common_table_header table_header;
1945 uint32_t maxvddc;
1946 uint32_t minvddc;
1947 uint32_t avfs_meannsigma_acontant0;
1948 uint32_t avfs_meannsigma_acontant1;
1949 uint32_t avfs_meannsigma_acontant2;
1950 uint16_t avfs_meannsigma_dc_tol_sigma;
1951 uint16_t avfs_meannsigma_platform_mean;
1952 uint16_t avfs_meannsigma_platform_sigma;
1953 uint32_t gb_vdroop_table_cksoff_a0;
1954 uint32_t gb_vdroop_table_cksoff_a1;
1955 uint32_t gb_vdroop_table_cksoff_a2;
1956 uint32_t gb_vdroop_table_ckson_a0;
1957 uint32_t gb_vdroop_table_ckson_a1;
1958 uint32_t gb_vdroop_table_ckson_a2;
1959 uint32_t avfsgb_fuse_table_cksoff_m1;
1960 uint32_t avfsgb_fuse_table_cksoff_m2;
1961 uint32_t avfsgb_fuse_table_cksoff_b;
1962 uint32_t avfsgb_fuse_table_ckson_m1;
1963 uint32_t avfsgb_fuse_table_ckson_m2;
1964 uint32_t avfsgb_fuse_table_ckson_b;
1965 uint16_t max_voltage_0_25mv;
1966 uint8_t enable_gb_vdroop_table_cksoff;
1967 uint8_t enable_gb_vdroop_table_ckson;
1968 uint8_t enable_gb_fuse_table_cksoff;
1969 uint8_t enable_gb_fuse_table_ckson;
1970 uint16_t psm_age_comfactor;
1971 uint8_t enable_apply_avfs_cksoff_voltage;
1972 uint8_t reserved;
1973 uint32_t dispclk2gfxclk_a;
1974 uint32_t dispclk2gfxclk_b;
1975 uint32_t dispclk2gfxclk_c;
1976 uint32_t pixclk2gfxclk_a;
1977 uint32_t pixclk2gfxclk_b;
1978 uint32_t pixclk2gfxclk_c;
1979 uint32_t dcefclk2gfxclk_a;
1980 uint32_t dcefclk2gfxclk_b;
1981 uint32_t dcefclk2gfxclk_c;
1982 uint32_t phyclk2gfxclk_a;
1983 uint32_t phyclk2gfxclk_b;
1984 uint32_t phyclk2gfxclk_c;
1985 uint32_t acg_gb_vdroop_table_a0;
1986 uint32_t acg_gb_vdroop_table_a1;
1987 uint32_t acg_gb_vdroop_table_a2;
1988 uint32_t acg_avfsgb_fuse_table_m1;
1989 uint32_t acg_avfsgb_fuse_table_m2;
1990 uint32_t acg_avfsgb_fuse_table_b;
1991 uint8_t enable_acg_gb_vdroop_table;
1992 uint8_t enable_acg_gb_fuse_table;
1993 uint32_t acg_dispclk2gfxclk_a;
1994 uint32_t acg_dispclk2gfxclk_b;
1995 uint32_t acg_dispclk2gfxclk_c;
1996 uint32_t acg_pixclk2gfxclk_a;
1997 uint32_t acg_pixclk2gfxclk_b;
1998 uint32_t acg_pixclk2gfxclk_c;
1999 uint32_t acg_dcefclk2gfxclk_a;
2000 uint32_t acg_dcefclk2gfxclk_b;
2001 uint32_t acg_dcefclk2gfxclk_c;
2002 uint32_t acg_phyclk2gfxclk_a;
2003 uint32_t acg_phyclk2gfxclk_b;
2004 uint32_t acg_phyclk2gfxclk_c;
2005};
2006
2007/*
2008 ***************************************************************************
2009 Data Table multimedia_info structure
2010 ***************************************************************************
2011*/
2012struct atom_multimedia_info_v2_1
2013{
2014 struct atom_common_table_header table_header;
2015 uint8_t uvdip_min_ver;
2016 uint8_t uvdip_max_ver;
2017 uint8_t vceip_min_ver;
2018 uint8_t vceip_max_ver;
2019 uint16_t uvd_enc_max_input_width_pixels;
2020 uint16_t uvd_enc_max_input_height_pixels;
2021 uint16_t vce_enc_max_input_width_pixels;
2022 uint16_t vce_enc_max_input_height_pixels;
2023 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2024 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2025};
2026
2027
2028/*
2029 ***************************************************************************
2030 Data Table umc_info structure
2031 ***************************************************************************
2032*/
2033struct atom_umc_info_v3_1
2034{
2035 struct atom_common_table_header table_header;
2036 uint32_t ucode_version;
2037 uint32_t ucode_rom_startaddr;
2038 uint32_t ucode_length;
2039 uint16_t umc_reg_init_offset;
2040 uint16_t customer_ucode_name_offset;
2041 uint16_t mclk_ss_percentage;
2042 uint16_t mclk_ss_rate_10hz;
2043 uint8_t umcip_min_ver;
2044 uint8_t umcip_max_ver;
2045 uint8_t vram_type; //enum of atom_dgpu_vram_type
2046 uint8_t umc_config;
2047 uint32_t mem_refclk_10khz;
2048};
2049
2050// umc_info.umc_config
2051enum atom_umc_config_def {
2052 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
2053 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
2054 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
2055 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
2056 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
2057 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
2058};
2059
2060struct atom_umc_info_v3_2
2061{
2062 struct atom_common_table_header table_header;
2063 uint32_t ucode_version;
2064 uint32_t ucode_rom_startaddr;
2065 uint32_t ucode_length;
2066 uint16_t umc_reg_init_offset;
2067 uint16_t customer_ucode_name_offset;
2068 uint16_t mclk_ss_percentage;
2069 uint16_t mclk_ss_rate_10hz;
2070 uint8_t umcip_min_ver;
2071 uint8_t umcip_max_ver;
2072 uint8_t vram_type; //enum of atom_dgpu_vram_type
2073 uint8_t umc_config;
2074 uint32_t mem_refclk_10khz;
2075 uint32_t pstate_uclk_10khz[4];
2076 uint16_t umcgoldenoffset;
2077 uint16_t densitygoldenoffset;
2078};
2079
2080struct atom_umc_info_v3_3
2081{
2082 struct atom_common_table_header table_header;
2083 uint32_t ucode_reserved;
2084 uint32_t ucode_rom_startaddr;
2085 uint32_t ucode_length;
2086 uint16_t umc_reg_init_offset;
2087 uint16_t customer_ucode_name_offset;
2088 uint16_t mclk_ss_percentage;
2089 uint16_t mclk_ss_rate_10hz;
2090 uint8_t umcip_min_ver;
2091 uint8_t umcip_max_ver;
2092 uint8_t vram_type; //enum of atom_dgpu_vram_type
2093 uint8_t umc_config;
2094 uint32_t mem_refclk_10khz;
2095 uint32_t pstate_uclk_10khz[4];
2096 uint16_t umcgoldenoffset;
2097 uint16_t densitygoldenoffset;
2098 uint32_t reserved[4];
2099};
2100
2101/*
2102 ***************************************************************************
2103 Data Table vram_info structure
2104 ***************************************************************************
2105*/
2106struct atom_vram_module_v9 {
2107 // Design Specific Values
2108 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2109 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2110 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2111 uint16_t reserved[3];
2112 uint16_t mem_voltage; // mem_voltage
2113 uint16_t vram_module_size; // Size of atom_vram_module_v9
2114 uint8_t ext_memory_id; // Current memory module ID
2115 uint8_t memory_type; // enum of atom_dgpu_vram_type
2116 uint8_t channel_num; // Number of mem. channels supported in this module
2117 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2118 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2119 uint8_t tunningset_id; // MC phy registers set per.
2120 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2121 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2122 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2123 uint8_t vram_rsd2; // reserved
2124 char dram_pnstring[20]; // part number end with '0'.
2125};
2126
2127struct atom_vram_info_header_v2_3 {
2128 struct atom_common_table_header table_header;
2129 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2130 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2131 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2132 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2133 uint16_t dram_data_remap_tbloffset; // reserved for now
2134 uint16_t tmrs_seq_offset; // offset of HBM tmrs
2135 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2136 uint16_t vram_rsd2;
2137 uint8_t vram_module_num; // indicate number of VRAM module
2138 uint8_t umcip_min_ver;
2139 uint8_t umcip_max_ver;
2140 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2141 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2142};
2143
2144struct atom_umc_register_addr_info{
2145 uint32_t umc_register_addr:24;
2146 uint32_t umc_reg_type_ind:1;
2147 uint32_t umc_reg_rsvd:7;
2148};
2149
2150//atom_umc_register_addr_info.
2151enum atom_umc_register_addr_info_flag{
2152 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
2153};
2154
2155union atom_umc_register_addr_info_access
2156{
2157 struct atom_umc_register_addr_info umc_reg_addr;
2158 uint32_t u32umc_reg_addr;
2159};
2160
2161struct atom_umc_reg_setting_id_config{
2162 uint32_t memclockrange:24;
2163 uint32_t mem_blk_id:8;
2164};
2165
2166union atom_umc_reg_setting_id_config_access
2167{
2168 struct atom_umc_reg_setting_id_config umc_id_access;
2169 uint32_t u32umc_id_access;
2170};
2171
2172struct atom_umc_reg_setting_data_block{
2173 union atom_umc_reg_setting_id_config_access block_id;
2174 uint32_t u32umc_reg_data[1];
2175};
2176
2177struct atom_umc_init_reg_block{
2178 uint16_t umc_reg_num;
2179 uint16_t reserved;
2180 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
2181 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
2182};
2183
2184struct atom_vram_module_v10 {
2185 // Design Specific Values
2186 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2187 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2188 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2189 uint16_t reserved[3];
2190 uint16_t mem_voltage; // mem_voltage
2191 uint16_t vram_module_size; // Size of atom_vram_module_v9
2192 uint8_t ext_memory_id; // Current memory module ID
2193 uint8_t memory_type; // enum of atom_dgpu_vram_type
2194 uint8_t channel_num; // Number of mem. channels supported in this module
2195 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2196 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2197 uint8_t tunningset_id; // MC phy registers set per
2198 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2199 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2200 uint8_t vram_flags; // bit0= bankgroup enable
2201 uint8_t vram_rsd2; // reserved
2202 uint16_t gddr6_mr10; // gddr6 mode register10 value
2203 uint16_t gddr6_mr1; // gddr6 mode register1 value
2204 uint16_t gddr6_mr2; // gddr6 mode register2 value
2205 uint16_t gddr6_mr7; // gddr6 mode register7 value
2206 char dram_pnstring[20]; // part number end with '0'
2207};
2208
2209struct atom_vram_info_header_v2_4 {
2210 struct atom_common_table_header table_header;
2211 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2212 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2213 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2214 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2215 uint16_t dram_data_remap_tbloffset; // reserved for now
2216 uint16_t reserved; // offset of reserved
2217 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2218 uint16_t vram_rsd2;
2219 uint8_t vram_module_num; // indicate number of VRAM module
2220 uint8_t umcip_min_ver;
2221 uint8_t umcip_max_ver;
2222 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2223 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2224};
2225
2226/*
2227 ***************************************************************************
2228 Data Table voltageobject_info structure
2229 ***************************************************************************
2230*/
2231struct atom_i2c_data_entry
2232{
2233 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
2234 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
2235};
2236
2237struct atom_voltage_object_header_v4{
2238 uint8_t voltage_type; //enum atom_voltage_type
2239 uint8_t voltage_mode; //enum atom_voltage_object_mode
2240 uint16_t object_size; //Size of Object
2241};
2242
2243// atom_voltage_object_header_v4.voltage_mode
2244enum atom_voltage_object_mode
2245{
2246 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
2247 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
2248 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
2249 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
2250 VOLTAGE_OBJ_EVV = 8,
2251 VOLTAGE_OBJ_MERGED_POWER = 9,
2252};
2253
2254struct atom_i2c_voltage_object_v4
2255{
2256 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
2257 uint8_t regulator_id; //Indicate Voltage Regulator Id
2258 uint8_t i2c_id;
2259 uint8_t i2c_slave_addr;
2260 uint8_t i2c_control_offset;
2261 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
2262 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
2263 uint8_t reserved[2];
2264 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
2265};
2266
2267// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
2268enum atom_i2c_voltage_control_flag
2269{
2270 VOLTAGE_DATA_ONE_BYTE = 0,
2271 VOLTAGE_DATA_TWO_BYTE = 1,
2272};
2273
2274
2275struct atom_voltage_gpio_map_lut
2276{
2277 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
2278 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
2279};
2280
2281struct atom_gpio_voltage_object_v4
2282{
2283 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
2284 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
2285 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
2286 uint8_t phase_delay_us; // phase delay in unit of micro second
2287 uint8_t reserved;
2288 uint32_t gpio_mask_val; // GPIO Mask value
2289 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
2290};
2291
2292struct atom_svid2_voltage_object_v4
2293{
2294 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
2295 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
2296 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
2297 uint8_t psi0_enable; //
2298 uint8_t maxvstep;
2299 uint8_t telemetry_offset;
2300 uint8_t telemetry_gain;
2301 uint16_t reserved1;
2302};
2303
2304struct atom_merged_voltage_object_v4
2305{
2306 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
2307 uint8_t merged_powerrail_type; //enum atom_voltage_type
2308 uint8_t reserved[3];
2309};
2310
2311union atom_voltage_object_v4{
2312 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
2313 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
2314 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
2315 struct atom_merged_voltage_object_v4 merged_voltage_obj;
2316};
2317
2318struct atom_voltage_objects_info_v4_1
2319{
2320 struct atom_common_table_header table_header;
2321 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
2322};
2323
2324
2325/*
2326 ***************************************************************************
2327 All Command Function structure definition
2328 ***************************************************************************
2329*/
2330
2331/*
2332 ***************************************************************************
2333 Structures used by asic_init
2334 ***************************************************************************
2335*/
2336
2337struct asic_init_engine_parameters
2338{
2339 uint32_t sclkfreqin10khz:24;
2340 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
2341};
2342
2343struct asic_init_mem_parameters
2344{
2345 uint32_t mclkfreqin10khz:24;
2346 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
2347};
2348
2349struct asic_init_parameters_v2_1
2350{
2351 struct asic_init_engine_parameters engineparam;
2352 struct asic_init_mem_parameters memparam;
2353};
2354
2355struct asic_init_ps_allocation_v2_1
2356{
2357 struct asic_init_parameters_v2_1 param;
2358 uint32_t reserved[16];
2359};
2360
2361
2362enum atom_asic_init_engine_flag
2363{
2364 b3NORMAL_ENGINE_INIT = 0,
2365 b3SRIOV_SKIP_ASIC_INIT = 0x02,
2366 b3SRIOV_LOAD_UCODE = 0x40,
2367};
2368
2369enum atom_asic_init_mem_flag
2370{
2371 b3NORMAL_MEM_INIT = 0,
2372 b3DRAM_SELF_REFRESH_EXIT =0x20,
2373};
2374
2375/*
2376 ***************************************************************************
2377 Structures used by setengineclock
2378 ***************************************************************************
2379*/
2380
2381struct set_engine_clock_parameters_v2_1
2382{
2383 uint32_t sclkfreqin10khz:24;
2384 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2385 uint32_t reserved[10];
2386};
2387
2388struct set_engine_clock_ps_allocation_v2_1
2389{
2390 struct set_engine_clock_parameters_v2_1 clockinfo;
2391 uint32_t reserved[10];
2392};
2393
2394
2395enum atom_set_engine_mem_clock_flag
2396{
2397 b3NORMAL_CHANGE_CLOCK = 0,
2398 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
2399 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
2400};
2401
2402/*
2403 ***************************************************************************
2404 Structures used by getengineclock
2405 ***************************************************************************
2406*/
2407struct get_engine_clock_parameter
2408{
2409 uint32_t sclk_10khz; // current engine speed in 10KHz unit
2410 uint32_t reserved;
2411};
2412
2413/*
2414 ***************************************************************************
2415 Structures used by setmemoryclock
2416 ***************************************************************************
2417*/
2418struct set_memory_clock_parameters_v2_1
2419{
2420 uint32_t mclkfreqin10khz:24;
2421 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2422 uint32_t reserved[10];
2423};
2424
2425struct set_memory_clock_ps_allocation_v2_1
2426{
2427 struct set_memory_clock_parameters_v2_1 clockinfo;
2428 uint32_t reserved[10];
2429};
2430
2431
2432/*
2433 ***************************************************************************
2434 Structures used by getmemoryclock
2435 ***************************************************************************
2436*/
2437struct get_memory_clock_parameter
2438{
2439 uint32_t mclk_10khz; // current engine speed in 10KHz unit
2440 uint32_t reserved;
2441};
2442
2443
2444
2445/*
2446 ***************************************************************************
2447 Structures used by setvoltage
2448 ***************************************************************************
2449*/
2450
2451struct set_voltage_parameters_v1_4
2452{
2453 uint8_t voltagetype; /* enum atom_voltage_type */
2454 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
2455 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
2456};
2457
2458//set_voltage_parameters_v2_1.voltagemode
2459enum atom_set_voltage_command{
2460 ATOM_SET_VOLTAGE = 0,
2461 ATOM_INIT_VOLTAGE_REGULATOR = 3,
2462 ATOM_SET_VOLTAGE_PHASE = 4,
2463 ATOM_GET_LEAKAGE_ID = 8,
2464};
2465
2466struct set_voltage_ps_allocation_v1_4
2467{
2468 struct set_voltage_parameters_v1_4 setvoltageparam;
2469 uint32_t reserved[10];
2470};
2471
2472
2473/*
2474 ***************************************************************************
2475 Structures used by computegpuclockparam
2476 ***************************************************************************
2477*/
2478
2479//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
2480enum atom_gpu_clock_type
2481{
2482 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
2483 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
2484 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
2485};
2486
2487struct compute_gpu_clock_input_parameter_v1_8
2488{
2489 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2490 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
2491 uint32_t reserved[5];
2492};
2493
2494
2495struct compute_gpu_clock_output_parameter_v1_8
2496{
2497 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2498 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
2499 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
2500 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
2501 uint16_t pll_ss_slew_frac;
2502 uint8_t pll_ss_enable;
2503 uint8_t reserved;
2504 uint32_t reserved1[2];
2505};
2506
2507
2508
2509/*
2510 ***************************************************************************
2511 Structures used by ReadEfuseValue
2512 ***************************************************************************
2513*/
2514
2515struct read_efuse_input_parameters_v3_1
2516{
2517 uint16_t efuse_start_index;
2518 uint8_t reserved;
2519 uint8_t bitslen;
2520};
2521
2522// ReadEfuseValue input/output parameter
2523union read_efuse_value_parameters_v3_1
2524{
2525 struct read_efuse_input_parameters_v3_1 efuse_info;
2526 uint32_t efusevalue;
2527};
2528
2529
2530/*
2531 ***************************************************************************
2532 Structures used by getsmuclockinfo
2533 ***************************************************************************
2534*/
2535struct atom_get_smu_clock_info_parameters_v3_1
2536{
2537 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
2538 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2539 uint8_t command; // enum of atom_get_smu_clock_info_command
2540 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2541};
2542
2543enum atom_get_smu_clock_info_command
2544{
2545 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
2546 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
2547 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
2548};
2549
2550enum atom_smu9_syspll0_clock_id
2551{
2552 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
2553 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
2554 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2555 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
2556 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
2557 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
2558 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
2559 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
2560 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
2561 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
2562 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
2563};
2564
2565enum atom_smu11_syspll_id {
2566 SMU11_SYSPLL0_ID = 0,
2567 SMU11_SYSPLL1_0_ID = 1,
2568 SMU11_SYSPLL1_1_ID = 2,
2569 SMU11_SYSPLL1_2_ID = 3,
2570 SMU11_SYSPLL2_ID = 4,
2571 SMU11_SYSPLL3_0_ID = 5,
2572 SMU11_SYSPLL3_1_ID = 6,
2573};
2574
2575enum atom_smu11_syspll0_clock_id {
2576 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
2577 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
2578 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2579 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
2580 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
2581 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2582};
2583
2584enum atom_smu11_syspll1_0_clock_id {
2585 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2586};
2587
2588enum atom_smu11_syspll1_1_clock_id {
2589 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2590};
2591
2592enum atom_smu11_syspll1_2_clock_id {
2593 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2594};
2595
2596enum atom_smu11_syspll2_clock_id {
2597 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2598};
2599
2600enum atom_smu11_syspll3_0_clock_id {
2601 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2602 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2603 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2604};
2605
2606enum atom_smu11_syspll3_1_clock_id {
2607 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2608 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2609 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2610};
2611
2612struct atom_get_smu_clock_info_output_parameters_v3_1
2613{
2614 union {
2615 uint32_t smu_clock_freq_hz;
2616 uint32_t syspllvcofreq_10khz;
2617 uint32_t sysspllrefclk_10khz;
2618 }atom_smu_outputclkfreq;
2619};
2620
2621
2622
2623/*
2624 ***************************************************************************
2625 Structures used by dynamicmemorysettings
2626 ***************************************************************************
2627*/
2628
2629enum atom_dynamic_memory_setting_command
2630{
2631 COMPUTE_MEMORY_PLL_PARAM = 1,
2632 COMPUTE_ENGINE_PLL_PARAM = 2,
2633 ADJUST_MC_SETTING_PARAM = 3,
2634};
2635
2636/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
2637struct dynamic_mclk_settings_parameters_v2_1
2638{
2639 uint32_t mclk_10khz:24; //Input= target mclk
2640 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2641 uint32_t reserved;
2642};
2643
2644/* when command = COMPUTE_ENGINE_PLL_PARAM */
2645struct dynamic_sclk_settings_parameters_v2_1
2646{
2647 uint32_t sclk_10khz:24; //Input= target mclk
2648 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2649 uint32_t mclk_10khz;
2650 uint32_t reserved;
2651};
2652
2653union dynamic_memory_settings_parameters_v2_1
2654{
2655 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2656 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2657};
2658
2659
2660
2661/*
2662 ***************************************************************************
2663 Structures used by memorytraining
2664 ***************************************************************************
2665*/
2666
2667enum atom_umc6_0_ucode_function_call_enum_id
2668{
2669 UMC60_UCODE_FUNC_ID_REINIT = 0,
2670 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2671 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2672};
2673
2674
2675struct memory_training_parameters_v2_1
2676{
2677 uint8_t ucode_func_id;
2678 uint8_t ucode_reserved[3];
2679 uint32_t reserved[5];
2680};
2681
2682
2683/*
2684 ***************************************************************************
2685 Structures used by setpixelclock
2686 ***************************************************************************
2687*/
2688
2689struct set_pixel_clock_parameter_v1_7
2690{
2691 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2692
2693 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2694 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2695 // indicate which graphic encoder will be used.
2696 uint8_t encoder_mode; // Encoder mode:
2697 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2698 uint8_t crtc_id; // enum of atom_crtc_def
2699 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2700 uint8_t reserved1[2];
2701 uint32_t reserved2;
2702};
2703
2704//ucMiscInfo
2705enum atom_set_pixel_clock_v1_7_misc_info
2706{
2707 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2708 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2709 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2710 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2711 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2712 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2713 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2714 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2715 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2716 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2717 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2718};
2719
2720/* deep_color_ratio */
2721enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2722{
2723 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2724 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2725 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2726 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2727};
2728
2729/*
2730 ***************************************************************************
2731 Structures used by setdceclock
2732 ***************************************************************************
2733*/
2734
2735// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
2736struct set_dce_clock_parameters_v2_1
2737{
2738 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2739 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2740 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2741 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2742 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2743};
2744
2745//ucDCEClkType
2746enum atom_set_dce_clock_clock_type
2747{
2748 DCE_CLOCK_TYPE_DISPCLK = 0,
2749 DCE_CLOCK_TYPE_DPREFCLK = 1,
2750 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2751};
2752
2753//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2754enum atom_set_dce_clock_dprefclk_flag
2755{
2756 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2757 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2758 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2759 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2760 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2761};
2762
2763//ucDCEClkFlag when ucDCEClkType == PIXCLK
2764enum atom_set_dce_clock_pixclk_flag
2765{
2766 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2767 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2768 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2769 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2770 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2771 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2772};
2773
2774struct set_dce_clock_ps_allocation_v2_1
2775{
2776 struct set_dce_clock_parameters_v2_1 param;
2777 uint32_t ulReserved[2];
2778};
2779
2780
2781/****************************************************************************/
2782// Structures used by BlankCRTC
2783/****************************************************************************/
2784struct blank_crtc_parameters
2785{
2786 uint8_t crtc_id; // enum atom_crtc_def
2787 uint8_t blanking; // enum atom_blank_crtc_command
2788 uint16_t reserved;
2789 uint32_t reserved1;
2790};
2791
2792enum atom_blank_crtc_command
2793{
2794 ATOM_BLANKING = 1,
2795 ATOM_BLANKING_OFF = 0,
2796};
2797
2798/****************************************************************************/
2799// Structures used by enablecrtc
2800/****************************************************************************/
2801struct enable_crtc_parameters
2802{
2803 uint8_t crtc_id; // enum atom_crtc_def
2804 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2805 uint8_t padding[2];
2806};
2807
2808
2809/****************************************************************************/
2810// Structure used by EnableDispPowerGating
2811/****************************************************************************/
2812struct enable_disp_power_gating_parameters_v2_1
2813{
2814 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2815 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2816 uint8_t padding[2];
2817};
2818
2819struct enable_disp_power_gating_ps_allocation
2820{
2821 struct enable_disp_power_gating_parameters_v2_1 param;
2822 uint32_t ulReserved[4];
2823};
2824
2825/****************************************************************************/
2826// Structure used in setcrtc_usingdtdtiming
2827/****************************************************************************/
2828struct set_crtc_using_dtd_timing_parameters
2829{
2830 uint16_t h_size;
2831 uint16_t h_blanking_time;
2832 uint16_t v_size;
2833 uint16_t v_blanking_time;
2834 uint16_t h_syncoffset;
2835 uint16_t h_syncwidth;
2836 uint16_t v_syncoffset;
2837 uint16_t v_syncwidth;
2838 uint16_t modemiscinfo;
2839 uint8_t h_border;
2840 uint8_t v_border;
2841 uint8_t crtc_id; // enum atom_crtc_def
2842 uint8_t encoder_mode; // atom_encode_mode_def
2843 uint8_t padding[2];
2844};
2845
2846
2847/****************************************************************************/
2848// Structures used by processi2cchanneltransaction
2849/****************************************************************************/
2850struct process_i2c_channel_transaction_parameters
2851{
2852 uint8_t i2cspeed_khz;
2853 union {
2854 uint8_t regindex;
2855 uint8_t status; /* enum atom_process_i2c_flag */
2856 } regind_status;
2857 uint16_t i2c_data_out;
2858 uint8_t flag; /* enum atom_process_i2c_status */
2859 uint8_t trans_bytes;
2860 uint8_t slave_addr;
2861 uint8_t i2c_id;
2862};
2863
2864//ucFlag
2865enum atom_process_i2c_flag
2866{
2867 HW_I2C_WRITE = 1,
2868 HW_I2C_READ = 0,
2869 I2C_2BYTE_ADDR = 0x02,
2870 HW_I2C_SMBUS_BYTE_WR = 0x04,
2871};
2872
2873//status
2874enum atom_process_i2c_status
2875{
2876 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2877 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2878};
2879
2880
2881/****************************************************************************/
2882// Structures used by processauxchanneltransaction
2883/****************************************************************************/
2884
2885struct process_aux_channel_transaction_parameters_v1_2
2886{
2887 uint16_t aux_request;
2888 uint16_t dataout;
2889 uint8_t channelid;
2890 union {
2891 uint8_t reply_status;
2892 uint8_t aux_delay;
2893 } aux_status_delay;
2894 uint8_t dataout_len;
2895 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2896};
2897
2898
2899/****************************************************************************/
2900// Structures used by selectcrtc_source
2901/****************************************************************************/
2902
2903struct select_crtc_source_parameters_v2_3
2904{
2905 uint8_t crtc_id; // enum atom_crtc_def
2906 uint8_t encoder_id; // enum atom_dig_def
2907 uint8_t encode_mode; // enum atom_encode_mode_def
2908 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2909};
2910
2911
2912/****************************************************************************/
2913// Structures used by digxencodercontrol
2914/****************************************************************************/
2915
2916// ucAction:
2917enum atom_dig_encoder_control_action
2918{
2919 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2920 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2921 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2922 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2923 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2924 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2925 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2926 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2927 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2928 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2929 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2930 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2931 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2932 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2933};
2934
2935//define ucPanelMode
2936enum atom_dig_encoder_control_panelmode
2937{
2938 DP_PANEL_MODE_DISABLE = 0x00,
2939 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2940 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2941};
2942
2943//ucDigId
2944enum atom_dig_encoder_control_v5_digid
2945{
2946 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2947 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2948 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2949 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2950 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2951 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2952 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2953 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2954};
2955
2956struct dig_encoder_stream_setup_parameters_v1_5
2957{
2958 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2959 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2960 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2961 uint8_t lanenum; // Lane number
2962 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2963 uint8_t bitpercolor;
2964 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2965 uint8_t reserved[2];
2966};
2967
2968struct dig_encoder_link_setup_parameters_v1_5
2969{
2970 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2971 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2972 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2973 uint8_t lanenum; // Lane number
2974 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2975 uint8_t hpd_sel;
2976 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2977 uint8_t reserved[2];
2978};
2979
2980struct dp_panel_mode_set_parameters_v1_5
2981{
2982 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2983 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2984 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2985 uint8_t reserved1;
2986 uint32_t reserved2[2];
2987};
2988
2989struct dig_encoder_generic_cmd_parameters_v1_5
2990{
2991 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2992 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2993 uint8_t reserved1[2];
2994 uint32_t reserved2[2];
2995};
2996
2997union dig_encoder_control_parameters_v1_5
2998{
2999 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
3000 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
3001 struct dig_encoder_link_setup_parameters_v1_5 link_param;
3002 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
3003};
3004
3005/*
3006 ***************************************************************************
3007 Structures used by dig1transmittercontrol
3008 ***************************************************************************
3009*/
3010struct dig_transmitter_control_parameters_v1_6
3011{
3012 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3013 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3014 union {
3015 uint8_t digmode; // enum atom_encode_mode_def
3016 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
3017 } mode_laneset;
3018 uint8_t lanenum; // Lane number 1, 2, 4, 8
3019 uint32_t symclk_10khz; // Symbol Clock in 10Khz
3020 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3021 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3022 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3023 uint8_t reserved;
3024 uint32_t reserved1;
3025};
3026
3027struct dig_transmitter_control_ps_allocation_v1_6
3028{
3029 struct dig_transmitter_control_parameters_v1_6 param;
3030 uint32_t reserved[4];
3031};
3032
3033//ucAction
3034enum atom_dig_transmitter_control_action
3035{
3036 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
3037 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
3038 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
3039 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
3040 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
3041 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
3042 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
3043 ATOM_TRANSMITTER_ACTION_INIT = 7,
3044 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
3045 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
3046 ATOM_TRANSMITTER_ACTION_SETUP = 10,
3047 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
3048 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
3049 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
3050};
3051
3052// digfe_sel
3053enum atom_dig_transmitter_control_digfe_sel
3054{
3055 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
3056 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
3057 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
3058 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
3059 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
3060 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
3061 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
3062};
3063
3064
3065//ucHPDSel
3066enum atom_dig_transmitter_control_hpd_sel
3067{
3068 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
3069 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
3070 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
3071 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
3072 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
3073 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
3074 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
3075};
3076
3077// ucDPLaneSet
3078enum atom_dig_transmitter_control_dplaneset
3079{
3080 DP_LANE_SET__0DB_0_4V = 0x00,
3081 DP_LANE_SET__0DB_0_6V = 0x01,
3082 DP_LANE_SET__0DB_0_8V = 0x02,
3083 DP_LANE_SET__0DB_1_2V = 0x03,
3084 DP_LANE_SET__3_5DB_0_4V = 0x08,
3085 DP_LANE_SET__3_5DB_0_6V = 0x09,
3086 DP_LANE_SET__3_5DB_0_8V = 0x0a,
3087 DP_LANE_SET__6DB_0_4V = 0x10,
3088 DP_LANE_SET__6DB_0_6V = 0x11,
3089 DP_LANE_SET__9_5DB_0_4V = 0x18,
3090};
3091
3092
3093
3094/****************************************************************************/
3095// Structures used by ExternalEncoderControl V2.4
3096/****************************************************************************/
3097
3098struct external_encoder_control_parameters_v2_4
3099{
3100 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
3101 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
3102 uint8_t action; //
3103 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3104 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3105 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
3106 uint8_t hpd_id;
3107};
3108
3109
3110// ucAction
3111enum external_encoder_control_action_def
3112{
3113 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
3114 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
3115 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
3116 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
3117 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
3118 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
3119 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
3120 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
3121};
3122
3123// ucConfig
3124enum external_encoder_control_v2_4_config_def
3125{
3126 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
3127 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
3128 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
3129 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
3130 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
3131 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
3132 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
3133 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
3134 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
3135};
3136
3137struct external_encoder_control_ps_allocation_v2_4
3138{
3139 struct external_encoder_control_parameters_v2_4 sExtEncoder;
3140 uint32_t reserved[2];
3141};
3142
3143
3144/*
3145 ***************************************************************************
3146 AMD ACPI Table
3147
3148 ***************************************************************************
3149*/
3150
3151struct amd_acpi_description_header{
3152 uint32_t signature;
3153 uint32_t tableLength; //Length
3154 uint8_t revision;
3155 uint8_t checksum;
3156 uint8_t oemId[6];
3157 uint8_t oemTableId[8]; //UINT64 OemTableId;
3158 uint32_t oemRevision;
3159 uint32_t creatorId;
3160 uint32_t creatorRevision;
3161};
3162
3163struct uefi_acpi_vfct{
3164 struct amd_acpi_description_header sheader;
3165 uint8_t tableUUID[16]; //0x24
3166 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
3167 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
3168 uint32_t reserved[4]; //0x3C
3169};
3170
3171struct vfct_image_header{
3172 uint32_t pcibus; //0x4C
3173 uint32_t pcidevice; //0x50
3174 uint32_t pcifunction; //0x54
3175 uint16_t vendorid; //0x58
3176 uint16_t deviceid; //0x5A
3177 uint16_t ssvid; //0x5C
3178 uint16_t ssid; //0x5E
3179 uint32_t revision; //0x60
3180 uint32_t imagelength; //0x64
3181};
3182
3183
3184struct gop_vbios_content {
3185 struct vfct_image_header vbiosheader;
3186 uint8_t vbioscontent[1];
3187};
3188
3189struct gop_lib1_content {
3190 struct vfct_image_header lib1header;
3191 uint8_t lib1content[1];
3192};
3193
3194
3195
3196/*
3197 ***************************************************************************
3198 Scratch Register definitions
3199 Each number below indicates which scratch regiser request, Active and
3200 Connect all share the same definitions as display_device_tag defines
3201 ***************************************************************************
3202*/
3203
3204enum scratch_register_def{
3205 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
3206 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
3207 ATOM_ACTIVE_INFO_DEF = 3,
3208 ATOM_LCD_INFO_DEF = 4,
3209 ATOM_DEVICE_REQ_INFO_DEF = 5,
3210 ATOM_ACC_CHANGE_INFO_DEF = 6,
3211 ATOM_PRE_OS_MODE_INFO_DEF = 7,
3212 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
3213 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
3214};
3215
3216enum scratch_device_connect_info_bit_def{
3217 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
3218 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
3219 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
3220 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
3221 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
3222 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
3223 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
3224 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
3225 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
3226};
3227
3228enum scratch_bl_bri_level_info_bit_def{
3229 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
3230#ifndef _H2INC
3231 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
3232 ATOM_DEVICE_DPMS_STATE =0x00010000,
3233#endif
3234};
3235
3236enum scratch_active_info_bits_def{
3237 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
3238 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
3239 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
3240 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
3241 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
3242 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
3243 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
3244 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
3245};
3246
3247enum scratch_device_req_info_bits_def{
3248 ATOM_DISPLAY_LCD1_REQ =0x0002,
3249 ATOM_DISPLAY_DFP1_REQ =0x0008,
3250 ATOM_DISPLAY_DFP2_REQ =0x0080,
3251 ATOM_DISPLAY_DFP3_REQ =0x0200,
3252 ATOM_DISPLAY_DFP4_REQ =0x0400,
3253 ATOM_DISPLAY_DFP5_REQ =0x0800,
3254 ATOM_DISPLAY_DFP6_REQ =0x0040,
3255 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
3256};
3257
3258enum scratch_acc_change_info_bitshift_def{
3259 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
3260 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
3261};
3262
3263enum scratch_acc_change_info_bits_def{
3264 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
3265 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
3266};
3267
3268enum scratch_pre_os_mode_info_bits_def{
3269 ATOM_PRE_OS_MODE_MASK =0x00000003,
3270 ATOM_PRE_OS_MODE_VGA =0x00000000,
3271 ATOM_PRE_OS_MODE_VESA =0x00000001,
3272 ATOM_PRE_OS_MODE_GOP =0x00000002,
3273 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
3274 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
3275 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
3276 ATOM_ASIC_INIT_COMPLETE =0x00000200,
3277#ifndef _H2INC
3278 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
3279#endif
3280};
3281
3282
3283
3284/*
3285 ***************************************************************************
3286 ATOM firmware ID header file
3287 !! Please keep it at end of the atomfirmware.h !!
3288 ***************************************************************************
3289*/
3290#include "atomfirmwareid.h"
3291#pragma pack()
3292
3293#endif
3294