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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017 Marvell
4 *
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
6 */
7
8#ifndef __SAFEXCEL_H__
9#define __SAFEXCEL_H__
10
11#include <crypto/aead.h>
12#include <crypto/algapi.h>
13#include <crypto/internal/hash.h>
14#include <crypto/sha.h>
15#include <crypto/skcipher.h>
16
17#define EIP197_HIA_VERSION_BE 0xca35
18#define EIP197_HIA_VERSION_LE 0x35ca
19#define EIP97_VERSION_LE 0x9e61
20#define EIP196_VERSION_LE 0x3bc4
21#define EIP197_VERSION_LE 0x3ac5
22#define EIP96_VERSION_LE 0x9f60
23#define EIP201_VERSION_LE 0x36c9
24#define EIP206_VERSION_LE 0x31ce
25#define EIP197_REG_LO16(reg) (reg & 0xffff)
26#define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
27#define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
28#define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
29 ((reg >> 4) & 0xf0) | \
30 ((reg >> 12) & 0xf))
31
32/* EIP197 HIA OPTIONS ENCODING */
33#define EIP197_HIA_OPT_HAS_PE_ARB BIT(29)
34
35/* EIP206 OPTIONS ENCODING */
36#define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3)
37
38/* EIP197 OPTIONS ENCODING */
39#define EIP197_OPT_HAS_TRC BIT(31)
40
41/* Static configuration */
42#define EIP197_DEFAULT_RING_SIZE 400
43#define EIP197_MAX_TOKENS 19
44#define EIP197_MAX_RINGS 4
45#define EIP197_FETCH_DEPTH 2
46#define EIP197_MAX_BATCH_SZ 64
47#define EIP197_MAX_RING_AIC 14
48
49#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
50 GFP_KERNEL : GFP_ATOMIC)
51
52/* Custom on-stack requests (for invalidation) */
53#define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
54 sizeof(struct safexcel_cipher_req)
55#define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
56 sizeof(struct safexcel_ahash_req)
57#define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
58 sizeof(struct safexcel_cipher_req)
59#define EIP197_REQUEST_ON_STACK(name, type, size) \
60 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
61 struct type##_request *name = (void *)__##name##_desc
62
63/* Xilinx dev board base offsets */
64#define EIP197_XLX_GPIO_BASE 0x200000
65#define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
66#define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
67#define EIP197_XLX_USER_INT_ENB_MSK 0x2004
68#define EIP197_XLX_USER_INT_ENB_SET 0x2008
69#define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
70#define EIP197_XLX_USER_INT_BLOCK 0x2040
71#define EIP197_XLX_USER_INT_PEND 0x2048
72#define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
73#define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
74#define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
75#define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
76#define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
77#define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
78#define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
79#define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
80
81/* Helper defines for probe function */
82#define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
83
84/* Register base offsets */
85#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
86#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
87#define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
88#define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
89#define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
90#define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
91#define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
92#define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
93#define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
94#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
95#define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
96
97/* EIP197 base offsets */
98#define EIP197_HIA_AIC_BASE 0x90000
99#define EIP197_HIA_AIC_G_BASE 0x90000
100#define EIP197_HIA_AIC_R_BASE 0x90800
101#define EIP197_HIA_AIC_xDR_BASE 0x80000
102#define EIP197_HIA_DFE_BASE 0x8c000
103#define EIP197_HIA_DFE_THR_BASE 0x8c040
104#define EIP197_HIA_DSE_BASE 0x8d000
105#define EIP197_HIA_DSE_THR_BASE 0x8d040
106#define EIP197_HIA_GEN_CFG_BASE 0xf0000
107#define EIP197_PE_BASE 0xa0000
108#define EIP197_GLOBAL_BASE 0xf0000
109
110/* EIP97 base offsets */
111#define EIP97_HIA_AIC_BASE 0x0
112#define EIP97_HIA_AIC_G_BASE 0x0
113#define EIP97_HIA_AIC_R_BASE 0x0
114#define EIP97_HIA_AIC_xDR_BASE 0x0
115#define EIP97_HIA_DFE_BASE 0xf000
116#define EIP97_HIA_DFE_THR_BASE 0xf200
117#define EIP97_HIA_DSE_BASE 0xf400
118#define EIP97_HIA_DSE_THR_BASE 0xf600
119#define EIP97_HIA_GEN_CFG_BASE 0x10000
120#define EIP97_PE_BASE 0x10000
121#define EIP97_GLOBAL_BASE 0x10000
122
123/* CDR/RDR register offsets */
124#define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
125#define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
126#define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
127#define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
128#define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
129#define EIP197_HIA_xDR_RING_SIZE 0x0018
130#define EIP197_HIA_xDR_DESC_SIZE 0x001c
131#define EIP197_HIA_xDR_CFG 0x0020
132#define EIP197_HIA_xDR_DMA_CFG 0x0024
133#define EIP197_HIA_xDR_THRESH 0x0028
134#define EIP197_HIA_xDR_PREP_COUNT 0x002c
135#define EIP197_HIA_xDR_PROC_COUNT 0x0030
136#define EIP197_HIA_xDR_PREP_PNTR 0x0034
137#define EIP197_HIA_xDR_PROC_PNTR 0x0038
138#define EIP197_HIA_xDR_STAT 0x003c
139
140/* register offsets */
141#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
142#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
143#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
144#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
145#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
146#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
147#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
148#define EIP197_HIA_RA_PE_STAT 0x0014
149#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
150#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
151#define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
152#define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
153#define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
154#define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
155#define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
156#define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
157#define EIP197_HIA_AIC_G_ACK 0xf810
158#define EIP197_HIA_MST_CTRL 0xfff4
159#define EIP197_HIA_OPTIONS 0xfff8
160#define EIP197_HIA_VERSION 0xfffc
161#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
162#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
163#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
164#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
165#define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
166#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
167#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
168#define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
169#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
170#define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
171#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
172#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
173#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
174#define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
175#define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
176#define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
177#define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
178#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
179#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
180#define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
181#define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
182#define EIP197_MST_CTRL 0xfff4
183#define EIP197_OPTIONS 0xfff8
184#define EIP197_VERSION 0xfffc
185
186/* EIP197-specific registers, no indirection */
187#define EIP197_CLASSIFICATION_RAMS 0xe0000
188#define EIP197_TRC_CTRL 0xf0800
189#define EIP197_TRC_LASTRES 0xf0804
190#define EIP197_TRC_REGINDEX 0xf0808
191#define EIP197_TRC_PARAMS 0xf0820
192#define EIP197_TRC_FREECHAIN 0xf0824
193#define EIP197_TRC_PARAMS2 0xf0828
194#define EIP197_TRC_ECCCTRL 0xf0830
195#define EIP197_TRC_ECCSTAT 0xf0834
196#define EIP197_TRC_ECCADMINSTAT 0xf0838
197#define EIP197_TRC_ECCDATASTAT 0xf083c
198#define EIP197_TRC_ECCDATA 0xf0840
199#define EIP197_STRC_CONFIG 0xf43f0
200#define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
201#define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
202#define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
203#define EIP197_FLUE_OFFSETS 0xf6808
204#define EIP197_FLUE_ARC4_OFFSET 0xf680c
205#define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
206#define EIP197_CS_RAM_CTRL 0xf7ff0
207
208/* EIP197_HIA_xDR_DESC_SIZE */
209#define EIP197_xDR_DESC_MODE_64BIT BIT(31)
210
211/* EIP197_HIA_xDR_DMA_CFG */
212#define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
213#define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
214#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
215#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
216#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
217
218/* EIP197_HIA_CDR_THRESH */
219#define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
220#define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
221#define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
222#define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
223
224/* EIP197_HIA_RDR_THRESH */
225#define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
226#define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
227#define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
228
229/* EIP197_HIA_xDR_PREP_COUNT */
230#define EIP197_xDR_PREP_CLR_COUNT BIT(31)
231
232/* EIP197_HIA_xDR_PROC_COUNT */
233#define EIP197_xDR_PROC_xD_PKT_OFFSET 24
234#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
235#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
236#define EIP197_xDR_PROC_CLR_COUNT BIT(31)
237
238/* EIP197_HIA_xDR_STAT */
239#define EIP197_xDR_DMA_ERR BIT(0)
240#define EIP197_xDR_PREP_CMD_THRES BIT(1)
241#define EIP197_xDR_ERR BIT(2)
242#define EIP197_xDR_THRESH BIT(4)
243#define EIP197_xDR_TIMEOUT BIT(5)
244
245#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
246#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
247
248/* EIP197_HIA_OPTIONS */
249#define EIP197_N_RINGS_OFFSET 0
250#define EIP197_N_RINGS_MASK GENMASK(3, 0)
251#define EIP197_N_PES_OFFSET 4
252#define EIP197_N_PES_MASK GENMASK(4, 0)
253#define EIP97_N_PES_MASK GENMASK(2, 0)
254#define EIP197_HWDATAW_OFFSET 25
255#define EIP197_HWDATAW_MASK GENMASK(3, 0)
256#define EIP97_HWDATAW_MASK GENMASK(2, 0)
257#define EIP197_CFSIZE_OFFSET 9
258#define EIP197_CFSIZE_ADJUST 4
259#define EIP97_CFSIZE_OFFSET 8
260#define EIP197_CFSIZE_MASK GENMASK(2, 0)
261#define EIP97_CFSIZE_MASK GENMASK(3, 0)
262#define EIP197_RFSIZE_OFFSET 12
263#define EIP197_RFSIZE_ADJUST 4
264#define EIP97_RFSIZE_OFFSET 12
265#define EIP197_RFSIZE_MASK GENMASK(2, 0)
266#define EIP97_RFSIZE_MASK GENMASK(3, 0)
267
268/* EIP197_HIA_AIC_R_ENABLE_CTRL */
269#define EIP197_CDR_IRQ(n) BIT((n) * 2)
270#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
271
272/* EIP197_HIA_DFE/DSE_CFG */
273#define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
274#define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
275#define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
276#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
277#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
278#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
279#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
280#define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29))
281#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
282#define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31)
283
284/* EIP197_HIA_DFE/DSE_THR_CTRL */
285#define EIP197_DxE_THR_CTRL_EN BIT(30)
286#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
287
288/* EIP197_PE_ICE_PUE/FPP_CTRL */
289#define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
290#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
291#define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
292
293/* EIP197_HIA_AIC_G_ENABLED_STAT */
294#define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
295#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
296#define EIP197_G_IRQ_RING BIT(16)
297#define EIP197_G_IRQ_PE(n) BIT((n) + 20)
298
299/* EIP197_HIA_MST_CTRL */
300#define RD_CACHE_3BITS 0x5
301#define WR_CACHE_3BITS 0x3
302#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
303#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
304#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
305#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
306#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
307#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
308#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
309#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
310
311/* EIP197_PE_IN_DBUF/TBUF_THRES */
312#define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
313#define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
314
315/* EIP197_PE_OUT_DBUF_THRES */
316#define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
317#define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
318
319/* EIP197_PE_ICE_SCRATCH_CTRL */
320#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
321#define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
322#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
323#define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
324
325/* EIP197_PE_ICE_SCRATCH_RAM */
326#define EIP197_NUM_OF_SCRATCH_BLOCKS 32
327
328/* EIP197_PE_ICE_PUE/FPP_CTRL */
329#define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
330#define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
331#define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
332
333/* EIP197_PE_ICE_RAM_CTRL */
334#define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
335#define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
336
337/* EIP197_PE_EIP96_TOKEN_CTRL */
338#define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
339#define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
340#define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
341
342/* EIP197_PE_EIP96_FUNCTION_EN */
343#define EIP197_FUNCTION_ALL 0xffffffff
344
345/* EIP197_PE_EIP96_CONTEXT_CTRL */
346#define EIP197_CONTEXT_SIZE(n) (n)
347#define EIP197_ADDRESS_MODE BIT(8)
348#define EIP197_CONTROL_MODE BIT(9)
349
350/* EIP197_PE_EIP96_TOKEN_CTRL2 */
351#define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3)
352
353/* EIP197_STRC_CONFIG */
354#define EIP197_STRC_CONFIG_INIT BIT(31)
355#define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8)
356#define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
357
358/* EIP197_FLUE_CONFIG */
359#define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
360
361/* Context Control */
362struct safexcel_context_record {
363 __le32 control0;
364 __le32 control1;
365
366 __le32 data[40];
367} __packed;
368
369/* control0 */
370#define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
371#define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
372#define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
373#define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
374#define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
375#define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
376#define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
377#define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
378#define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
379#define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
380#define CONTEXT_CONTROL_RESTART_HASH BIT(4)
381#define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
382#define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
383#define CONTEXT_CONTROL_KEY_EN BIT(16)
384#define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
385#define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
386#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
387#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
388#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
389#define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
390#define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
391#define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
392#define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
393#define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
394#define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
395#define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
396#define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
397#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
398#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
399#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
400#define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
401#define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
402#define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
403#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
404#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
405#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
406#define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
407#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
408#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
409#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
410#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
411#define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
412#define CONTEXT_CONTROL_INV_FR (0x5 << 24)
413#define CONTEXT_CONTROL_INV_TR (0x6 << 24)
414
415/* control1 */
416#define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
417#define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
418#define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
419#define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
420#define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
421#define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
422#define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
423#define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
424#define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
425#define CONTEXT_CONTROL_IV0 BIT(5)
426#define CONTEXT_CONTROL_IV1 BIT(6)
427#define CONTEXT_CONTROL_IV2 BIT(7)
428#define CONTEXT_CONTROL_IV3 BIT(8)
429#define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
430#define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
431#define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
432#define CONTEXT_CONTROL_HASH_STORE BIT(19)
433
434#define EIP197_XCM_MODE_GCM 1
435#define EIP197_XCM_MODE_CCM 2
436
437#define EIP197_AEAD_TYPE_IPSEC_ESP 2
438#define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3
439#define EIP197_AEAD_IPSEC_IV_SIZE 8
440#define EIP197_AEAD_IPSEC_NONCE_SIZE 4
441#define EIP197_AEAD_IPSEC_COUNTER_SIZE 4
442#define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3
443
444/* The hash counter given to the engine in the context has a granularity of
445 * 64 bits.
446 */
447#define EIP197_COUNTER_BLOCK_SIZE 64
448
449/* EIP197_CS_RAM_CTRL */
450#define EIP197_TRC_ENABLE_0 BIT(4)
451#define EIP197_TRC_ENABLE_1 BIT(5)
452#define EIP197_TRC_ENABLE_2 BIT(6)
453#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
454#define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
455#define EIP197_CS_BANKSEL_OFS 12
456
457/* EIP197_TRC_PARAMS */
458#define EIP197_TRC_PARAMS_SW_RESET BIT(0)
459#define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
460#define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
461#define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
462#define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
463
464/* EIP197_TRC_FREECHAIN */
465#define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
466#define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
467
468/* EIP197_TRC_PARAMS2 */
469#define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
470#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
471
472/* Cache helpers */
473#define EIP197_MIN_DSIZE 1024
474#define EIP197_MIN_ASIZE 8
475#define EIP197_CS_TRC_REC_WC 64
476#define EIP197_CS_RC_SIZE (4 * sizeof(u32))
477#define EIP197_CS_RC_NEXT(x) (x)
478#define EIP197_CS_RC_PREV(x) ((x) << 10)
479#define EIP197_RC_NULL 0x3ff
480
481/* Result data */
482struct result_data_desc {
483 u32 packet_length:17;
484 u32 error_code:15;
485
486 u8 bypass_length:4;
487 u8 e15:1;
488 u16 rsvd0;
489 u8 hash_bytes:1;
490 u8 hash_length:6;
491 u8 generic_bytes:1;
492 u8 checksum:1;
493 u8 next_header:1;
494 u8 length:1;
495
496 u16 application_id;
497 u16 rsvd1;
498
499 u32 rsvd2[5];
500} __packed;
501
502
503/* Basic Result Descriptor format */
504struct safexcel_result_desc {
505 u32 particle_size:17;
506 u8 rsvd0:3;
507 u8 descriptor_overflow:1;
508 u8 buffer_overflow:1;
509 u8 last_seg:1;
510 u8 first_seg:1;
511 u16 result_size:8;
512
513 u32 rsvd1;
514
515 u32 data_lo;
516 u32 data_hi;
517} __packed;
518
519/*
520 * The EIP(1)97 only needs to fetch the descriptor part of
521 * the result descriptor, not the result token part!
522 */
523#define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
524 sizeof(u32))
525#define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
526 sizeof(u32))
527
528struct safexcel_token {
529 u32 packet_length:17;
530 u8 stat:2;
531 u16 instructions:9;
532 u8 opcode:4;
533} __packed;
534
535#define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
536
537#define EIP197_TOKEN_CTX_OFFSET(x) (x)
538#define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
539#define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
540
541#define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
542#define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
543#define EIP197_TOKEN_OPCODE_DIRECTION 0x0
544#define EIP197_TOKEN_OPCODE_INSERT 0x2
545#define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
546#define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
547#define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
548#define EIP197_TOKEN_OPCODE_VERIFY 0xd
549#define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
550#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
551
552static inline void eip197_noop_token(struct safexcel_token *token)
553{
554 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
555 token->packet_length = BIT(2);
556}
557
558/* Instructions */
559#define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
560#define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
561#define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
562#define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
563#define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
564#define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
565#define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
566#define EIP197_TOKEN_INS_LAST BIT(8)
567
568/* Processing Engine Control Data */
569struct safexcel_control_data_desc {
570 u32 packet_length:17;
571 u16 options:13;
572 u8 type:2;
573
574 u16 application_id;
575 u16 rsvd;
576
577 u8 refresh:2;
578 u32 context_lo:30;
579 u32 context_hi;
580
581 u32 control0;
582 u32 control1;
583
584 u32 token[EIP197_MAX_TOKENS];
585} __packed;
586
587#define EIP197_OPTION_MAGIC_VALUE BIT(0)
588#define EIP197_OPTION_64BIT_CTX BIT(1)
589#define EIP197_OPTION_RC_AUTO (0x2 << 3)
590#define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
591#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
592#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
593
594#define EIP197_TYPE_EXTENDED 0x3
595
596/* Basic Command Descriptor format */
597struct safexcel_command_desc {
598 u32 particle_size:17;
599 u8 rsvd0:5;
600 u8 last_seg:1;
601 u8 first_seg:1;
602 u16 additional_cdata_size:8;
603
604 u32 rsvd1;
605
606 u32 data_lo;
607 u32 data_hi;
608
609 struct safexcel_control_data_desc control_data;
610} __packed;
611
612#define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
613 sizeof(u32))
614
615/*
616 * Internal structures & functions
617 */
618
619#define EIP197_FW_TERMINAL_NOPS 2
620#define EIP197_FW_START_POLLCNT 16
621#define EIP197_FW_PUE_READY 0x14
622#define EIP197_FW_FPP_READY 0x18
623
624enum eip197_fw {
625 FW_IFPP = 0,
626 FW_IPUE,
627 FW_NB
628};
629
630struct safexcel_desc_ring {
631 void *base;
632 void *base_end;
633 dma_addr_t base_dma;
634
635 /* write and read pointers */
636 void *write;
637 void *read;
638
639 /* descriptor element offset */
640 unsigned offset;
641};
642
643enum safexcel_alg_type {
644 SAFEXCEL_ALG_TYPE_SKCIPHER,
645 SAFEXCEL_ALG_TYPE_AEAD,
646 SAFEXCEL_ALG_TYPE_AHASH,
647};
648
649struct safexcel_config {
650 u32 pes;
651 u32 rings;
652
653 u32 cd_size;
654 u32 cd_offset;
655
656 u32 rd_size;
657 u32 rd_offset;
658 u32 res_offset;
659};
660
661struct safexcel_work_data {
662 struct work_struct work;
663 struct safexcel_crypto_priv *priv;
664 int ring;
665};
666
667struct safexcel_ring {
668 spinlock_t lock;
669
670 struct workqueue_struct *workqueue;
671 struct safexcel_work_data work_data;
672
673 /* command/result rings */
674 struct safexcel_desc_ring cdr;
675 struct safexcel_desc_ring rdr;
676
677 /* result ring crypto API request */
678 struct crypto_async_request **rdr_req;
679
680 /* queue */
681 struct crypto_queue queue;
682 spinlock_t queue_lock;
683
684 /* Number of requests in the engine. */
685 int requests;
686
687 /* The ring is currently handling at least one request */
688 bool busy;
689
690 /* Store for current requests when bailing out of the dequeueing
691 * function when no enough resources are available.
692 */
693 struct crypto_async_request *req;
694 struct crypto_async_request *backlog;
695};
696
697/* EIP integration context flags */
698enum safexcel_eip_version {
699 /* Platform (EIP integration context) specifier */
700 EIP97IES_MRVL,
701 EIP197B_MRVL,
702 EIP197D_MRVL,
703 EIP197_DEVBRD
704};
705
706/* Priority we use for advertising our algorithms */
707#define SAFEXCEL_CRA_PRIORITY 300
708
709/* SM3 digest result for zero length message */
710#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
711 "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
712 "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
713 "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
714
715/* EIP algorithm presence flags */
716enum safexcel_eip_algorithms {
717 SAFEXCEL_ALG_BC0 = BIT(5),
718 SAFEXCEL_ALG_SM4 = BIT(6),
719 SAFEXCEL_ALG_SM3 = BIT(7),
720 SAFEXCEL_ALG_CHACHA20 = BIT(8),
721 SAFEXCEL_ALG_POLY1305 = BIT(9),
722 SAFEXCEL_SEQMASK_256 = BIT(10),
723 SAFEXCEL_SEQMASK_384 = BIT(11),
724 SAFEXCEL_ALG_AES = BIT(12),
725 SAFEXCEL_ALG_AES_XFB = BIT(13),
726 SAFEXCEL_ALG_DES = BIT(15),
727 SAFEXCEL_ALG_DES_XFB = BIT(16),
728 SAFEXCEL_ALG_ARC4 = BIT(18),
729 SAFEXCEL_ALG_AES_XTS = BIT(20),
730 SAFEXCEL_ALG_WIRELESS = BIT(21),
731 SAFEXCEL_ALG_MD5 = BIT(22),
732 SAFEXCEL_ALG_SHA1 = BIT(23),
733 SAFEXCEL_ALG_SHA2_256 = BIT(25),
734 SAFEXCEL_ALG_SHA2_512 = BIT(26),
735 SAFEXCEL_ALG_XCBC_MAC = BIT(27),
736 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
737 SAFEXCEL_ALG_GHASH = BIT(30),
738 SAFEXCEL_ALG_SHA3 = BIT(31),
739};
740
741struct safexcel_register_offsets {
742 u32 hia_aic;
743 u32 hia_aic_g;
744 u32 hia_aic_r;
745 u32 hia_aic_xdr;
746 u32 hia_dfe;
747 u32 hia_dfe_thr;
748 u32 hia_dse;
749 u32 hia_dse_thr;
750 u32 hia_gen_cfg;
751 u32 pe;
752 u32 global;
753};
754
755enum safexcel_flags {
756 EIP197_TRC_CACHE = BIT(0),
757 SAFEXCEL_HW_EIP197 = BIT(1),
758 EIP197_PE_ARB = BIT(2),
759 EIP197_ICE = BIT(3),
760 EIP197_SIMPLE_TRC = BIT(4),
761};
762
763struct safexcel_hwconfig {
764 enum safexcel_eip_algorithms algo_flags;
765 int hwver;
766 int hiaver;
767 int ppver;
768 int pever;
769 int hwdataw;
770 int hwcfsize;
771 int hwrfsize;
772 int hwnumpes;
773 int hwnumrings;
774 int hwnumraic;
775};
776
777struct safexcel_crypto_priv {
778 void __iomem *base;
779 struct device *dev;
780 struct clk *clk;
781 struct clk *reg_clk;
782 struct safexcel_config config;
783
784 enum safexcel_eip_version version;
785 struct safexcel_register_offsets offsets;
786 struct safexcel_hwconfig hwconfig;
787 u32 flags;
788
789 /* context DMA pool */
790 struct dma_pool *context_pool;
791
792 atomic_t ring_used;
793
794 struct safexcel_ring *ring;
795};
796
797struct safexcel_context {
798 int (*send)(struct crypto_async_request *req, int ring,
799 int *commands, int *results);
800 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
801 struct crypto_async_request *req, bool *complete,
802 int *ret);
803 struct safexcel_context_record *ctxr;
804 dma_addr_t ctxr_dma;
805
806 int ring;
807 bool needs_inv;
808 bool exit_inv;
809};
810
811#define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
812
813struct safexcel_ahash_export_state {
814 u64 len;
815 u64 processed;
816
817 u32 digest;
818
819 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
820 u8 cache[HASH_CACHE_SIZE];
821};
822
823/*
824 * Template structure to describe the algorithms in order to register them.
825 * It also has the purpose to contain our private structure and is actually
826 * the only way I know in this framework to avoid having global pointers...
827 */
828struct safexcel_alg_template {
829 struct safexcel_crypto_priv *priv;
830 enum safexcel_alg_type type;
831 enum safexcel_eip_algorithms algo_mask;
832 union {
833 struct skcipher_alg skcipher;
834 struct aead_alg aead;
835 struct ahash_alg ahash;
836 } alg;
837};
838
839struct safexcel_inv_result {
840 struct completion completion;
841 int error;
842};
843
844void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
845int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
846 void *rdp);
847void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
848int safexcel_invalidate_cache(struct crypto_async_request *async,
849 struct safexcel_crypto_priv *priv,
850 dma_addr_t ctxr_dma, int ring);
851int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
852 struct safexcel_desc_ring *cdr,
853 struct safexcel_desc_ring *rdr);
854int safexcel_select_ring(struct safexcel_crypto_priv *priv);
855void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
856 struct safexcel_desc_ring *ring);
857void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
858void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
859 struct safexcel_desc_ring *ring);
860struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
861 int ring_id,
862 bool first, bool last,
863 dma_addr_t data, u32 len,
864 u32 full_data_len,
865 dma_addr_t context);
866struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
867 int ring_id,
868 bool first, bool last,
869 dma_addr_t data, u32 len);
870int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
871 int ring);
872int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
873 int ring,
874 struct safexcel_result_desc *rdesc);
875void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
876 int ring,
877 struct safexcel_result_desc *rdesc,
878 struct crypto_async_request *req);
879inline struct crypto_async_request *
880safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
881void safexcel_inv_complete(struct crypto_async_request *req, int error);
882int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen,
883 void *istate, void *ostate);
884
885/* available algorithms */
886extern struct safexcel_alg_template safexcel_alg_ecb_des;
887extern struct safexcel_alg_template safexcel_alg_cbc_des;
888extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
889extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
890extern struct safexcel_alg_template safexcel_alg_ecb_aes;
891extern struct safexcel_alg_template safexcel_alg_cbc_aes;
892extern struct safexcel_alg_template safexcel_alg_cfb_aes;
893extern struct safexcel_alg_template safexcel_alg_ofb_aes;
894extern struct safexcel_alg_template safexcel_alg_ctr_aes;
895extern struct safexcel_alg_template safexcel_alg_md5;
896extern struct safexcel_alg_template safexcel_alg_sha1;
897extern struct safexcel_alg_template safexcel_alg_sha224;
898extern struct safexcel_alg_template safexcel_alg_sha256;
899extern struct safexcel_alg_template safexcel_alg_sha384;
900extern struct safexcel_alg_template safexcel_alg_sha512;
901extern struct safexcel_alg_template safexcel_alg_hmac_md5;
902extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
903extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
904extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
905extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
906extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
907extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
908extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
909extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
910extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
911extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
912extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
913extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
914extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
915extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
916extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
917extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
918extern struct safexcel_alg_template safexcel_alg_xts_aes;
919extern struct safexcel_alg_template safexcel_alg_gcm;
920extern struct safexcel_alg_template safexcel_alg_ccm;
921extern struct safexcel_alg_template safexcel_alg_crc32;
922extern struct safexcel_alg_template safexcel_alg_cbcmac;
923extern struct safexcel_alg_template safexcel_alg_xcbcmac;
924extern struct safexcel_alg_template safexcel_alg_cmac;
925extern struct safexcel_alg_template safexcel_alg_chacha20;
926extern struct safexcel_alg_template safexcel_alg_chachapoly;
927extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
928extern struct safexcel_alg_template safexcel_alg_sm3;
929extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
930extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
931extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
932extern struct safexcel_alg_template safexcel_alg_ofb_sm4;
933extern struct safexcel_alg_template safexcel_alg_cfb_sm4;
934extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
935extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
936extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
937extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
938extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
939extern struct safexcel_alg_template safexcel_alg_sha3_224;
940extern struct safexcel_alg_template safexcel_alg_sha3_256;
941extern struct safexcel_alg_template safexcel_alg_sha3_384;
942extern struct safexcel_alg_template safexcel_alg_sha3_512;
943extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
944extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
945extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
946extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
947extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
948extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
949extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
950extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
951extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
952extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
953extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
954extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
955extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
956extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
957extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
958extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
959
960#endif