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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11#ifndef __ARM64_KVM_EMULATE_H__
12#define __ARM64_KVM_EMULATE_H__
13
14#include <linux/kvm_host.h>
15
16#include <asm/debug-monitors.h>
17#include <asm/esr.h>
18#include <asm/kvm_arm.h>
19#include <asm/kvm_hyp.h>
20#include <asm/kvm_mmio.h>
21#include <asm/ptrace.h>
22#include <asm/cputype.h>
23#include <asm/virt.h>
24
25unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
26unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
27void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
28
29bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
30void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
31
32void kvm_inject_undefined(struct kvm_vcpu *vcpu);
33void kvm_inject_vabt(struct kvm_vcpu *vcpu);
34void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
35void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
36void kvm_inject_undef32(struct kvm_vcpu *vcpu);
37void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
38void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
39
40static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
41{
42 return !(vcpu->arch.hcr_el2 & HCR_RW);
43}
44
45static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
46{
47 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
48 if (is_kernel_in_hyp_mode())
49 vcpu->arch.hcr_el2 |= HCR_E2H;
50 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
51 /* route synchronous external abort exceptions to EL2 */
52 vcpu->arch.hcr_el2 |= HCR_TEA;
53 /* trap error record accesses */
54 vcpu->arch.hcr_el2 |= HCR_TERR;
55 }
56
57 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
58 vcpu->arch.hcr_el2 |= HCR_FWB;
59 } else {
60 /*
61 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
62 * get set in SCTLR_EL1 such that we can detect when the guest
63 * MMU gets turned on and do the necessary cache maintenance
64 * then.
65 */
66 vcpu->arch.hcr_el2 |= HCR_TVM;
67 }
68
69 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
70 vcpu->arch.hcr_el2 &= ~HCR_RW;
71
72 /*
73 * TID3: trap feature register accesses that we virtualise.
74 * For now this is conditional, since no AArch32 feature regs
75 * are currently virtualised.
76 */
77 if (!vcpu_el1_is_32bit(vcpu))
78 vcpu->arch.hcr_el2 |= HCR_TID3;
79
80 if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
81 vcpu_el1_is_32bit(vcpu))
82 vcpu->arch.hcr_el2 |= HCR_TID2;
83}
84
85static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
86{
87 return (unsigned long *)&vcpu->arch.hcr_el2;
88}
89
90static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
91{
92 vcpu->arch.hcr_el2 &= ~HCR_TWE;
93 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count))
94 vcpu->arch.hcr_el2 &= ~HCR_TWI;
95 else
96 vcpu->arch.hcr_el2 |= HCR_TWI;
97}
98
99static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
100{
101 vcpu->arch.hcr_el2 |= HCR_TWE;
102 vcpu->arch.hcr_el2 |= HCR_TWI;
103}
104
105static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
106{
107 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
108}
109
110static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
111{
112 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
113}
114
115static inline void vcpu_ptrauth_setup_lazy(struct kvm_vcpu *vcpu)
116{
117 if (vcpu_has_ptrauth(vcpu))
118 vcpu_ptrauth_disable(vcpu);
119}
120
121static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
122{
123 return vcpu->arch.vsesr_el2;
124}
125
126static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
127{
128 vcpu->arch.vsesr_el2 = vsesr;
129}
130
131static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
132{
133 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
134}
135
136static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
137{
138 return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
139}
140
141static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
142{
143 if (vcpu->arch.sysregs_loaded_on_cpu)
144 return read_sysreg_el1(SYS_ELR);
145 else
146 return *__vcpu_elr_el1(vcpu);
147}
148
149static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
150{
151 if (vcpu->arch.sysregs_loaded_on_cpu)
152 write_sysreg_el1(v, SYS_ELR);
153 else
154 *__vcpu_elr_el1(vcpu) = v;
155}
156
157static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
158{
159 return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
160}
161
162static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
163{
164 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
165}
166
167static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
168{
169 if (vcpu_mode_is_32bit(vcpu))
170 return kvm_condition_valid32(vcpu);
171
172 return true;
173}
174
175static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
176{
177 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
178}
179
180/*
181 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
182 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
183 * AArch32 with banked registers.
184 */
185static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
186 u8 reg_num)
187{
188 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
189}
190
191static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
192 unsigned long val)
193{
194 if (reg_num != 31)
195 vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
196}
197
198static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
199{
200 if (vcpu_mode_is_32bit(vcpu))
201 return vcpu_read_spsr32(vcpu);
202
203 if (vcpu->arch.sysregs_loaded_on_cpu)
204 return read_sysreg_el1(SYS_SPSR);
205 else
206 return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
207}
208
209static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
210{
211 if (vcpu_mode_is_32bit(vcpu)) {
212 vcpu_write_spsr32(vcpu, v);
213 return;
214 }
215
216 if (vcpu->arch.sysregs_loaded_on_cpu)
217 write_sysreg_el1(v, SYS_SPSR);
218 else
219 vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
220}
221
222static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
223{
224 u32 mode;
225
226 if (vcpu_mode_is_32bit(vcpu)) {
227 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
228 return mode > PSR_AA32_MODE_USR;
229 }
230
231 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
232
233 return mode != PSR_MODE_EL0t;
234}
235
236static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
237{
238 return vcpu->arch.fault.esr_el2;
239}
240
241static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
242{
243 u32 esr = kvm_vcpu_get_hsr(vcpu);
244
245 if (esr & ESR_ELx_CV)
246 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
247
248 return -1;
249}
250
251static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
252{
253 return vcpu->arch.fault.far_el2;
254}
255
256static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
257{
258 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
259}
260
261static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
262{
263 return vcpu->arch.fault.disr_el1;
264}
265
266static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
267{
268 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
269}
270
271static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
272{
273 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
274}
275
276static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
277{
278 return kvm_vcpu_get_hsr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
279}
280
281static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
282{
283 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
284}
285
286static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
287{
288 return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
289}
290
291static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
292{
293 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
294}
295
296static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
297{
298 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
299 kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
300}
301
302static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
303{
304 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
305}
306
307static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
308{
309 return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
310}
311
312/* This one is not specific to Data Abort */
313static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
314{
315 return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
316}
317
318static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
319{
320 return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
321}
322
323static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
324{
325 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
326}
327
328static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
329{
330 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
331}
332
333static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
334{
335 return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
336}
337
338static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
339{
340 switch (kvm_vcpu_trap_get_fault(vcpu)) {
341 case FSC_SEA:
342 case FSC_SEA_TTW0:
343 case FSC_SEA_TTW1:
344 case FSC_SEA_TTW2:
345 case FSC_SEA_TTW3:
346 case FSC_SECC:
347 case FSC_SECC_TTW0:
348 case FSC_SECC_TTW1:
349 case FSC_SECC_TTW2:
350 case FSC_SECC_TTW3:
351 return true;
352 default:
353 return false;
354 }
355}
356
357static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
358{
359 u32 esr = kvm_vcpu_get_hsr(vcpu);
360 return ESR_ELx_SYS64_ISS_RT(esr);
361}
362
363static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
364{
365 if (kvm_vcpu_trap_is_iabt(vcpu))
366 return false;
367
368 return kvm_vcpu_dabt_iswrite(vcpu);
369}
370
371static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
372{
373 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
374}
375
376static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
377{
378 return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG;
379}
380
381static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
382 bool flag)
383{
384 if (flag)
385 vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
386 else
387 vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG;
388}
389
390static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
391{
392 if (vcpu_mode_is_32bit(vcpu)) {
393 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
394 } else {
395 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
396 sctlr |= (1 << 25);
397 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
398 }
399}
400
401static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
402{
403 if (vcpu_mode_is_32bit(vcpu))
404 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
405
406 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
407}
408
409static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
410 unsigned long data,
411 unsigned int len)
412{
413 if (kvm_vcpu_is_be(vcpu)) {
414 switch (len) {
415 case 1:
416 return data & 0xff;
417 case 2:
418 return be16_to_cpu(data & 0xffff);
419 case 4:
420 return be32_to_cpu(data & 0xffffffff);
421 default:
422 return be64_to_cpu(data);
423 }
424 } else {
425 switch (len) {
426 case 1:
427 return data & 0xff;
428 case 2:
429 return le16_to_cpu(data & 0xffff);
430 case 4:
431 return le32_to_cpu(data & 0xffffffff);
432 default:
433 return le64_to_cpu(data);
434 }
435 }
436
437 return data; /* Leave LE untouched */
438}
439
440static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
441 unsigned long data,
442 unsigned int len)
443{
444 if (kvm_vcpu_is_be(vcpu)) {
445 switch (len) {
446 case 1:
447 return data & 0xff;
448 case 2:
449 return cpu_to_be16(data & 0xffff);
450 case 4:
451 return cpu_to_be32(data & 0xffffffff);
452 default:
453 return cpu_to_be64(data);
454 }
455 } else {
456 switch (len) {
457 case 1:
458 return data & 0xff;
459 case 2:
460 return cpu_to_le16(data & 0xffff);
461 case 4:
462 return cpu_to_le32(data & 0xffffffff);
463 default:
464 return cpu_to_le64(data);
465 }
466 }
467
468 return data; /* Leave LE untouched */
469}
470
471static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
472{
473 if (vcpu_mode_is_32bit(vcpu))
474 kvm_skip_instr32(vcpu, is_wide_instr);
475 else
476 *vcpu_pc(vcpu) += 4;
477
478 /* advance the singlestep state machine */
479 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
480}
481
482/*
483 * Skip an instruction which has been emulated at hyp while most guest sysregs
484 * are live.
485 */
486static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
487{
488 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
489 vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
490
491 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
492
493 write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
494 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
495}
496
497#endif /* __ARM64_KVM_EMULATE_H__ */