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1XICS interrupt controller 2 3Device type supported: KVM_DEV_TYPE_XICS 4 5Groups: 6 1. KVM_DEV_XICS_GRP_SOURCES 7 Attributes: One per interrupt source, indexed by the source number. 8 9 2. KVM_DEV_XICS_GRP_CTRL 10 Attributes: 11 2.1 KVM_DEV_XICS_NR_SERVERS (write only) 12 The kvm_device_attr.addr points to a __u32 value which is the number of 13 interrupt server numbers (ie, highest possible vcpu id plus one). 14 Errors: 15 -EINVAL: Value greater than KVM_MAX_VCPU_ID. 16 -EFAULT: Invalid user pointer for attr->addr. 17 -EBUSY: A vcpu is already connected to the device. 18 19This device emulates the XICS (eXternal Interrupt Controller 20Specification) defined in PAPR. The XICS has a set of interrupt 21sources, each identified by a 20-bit source number, and a set of 22Interrupt Control Presentation (ICP) entities, also called "servers", 23each associated with a virtual CPU. 24 25The ICP entities are created by enabling the KVM_CAP_IRQ_ARCH 26capability for each vcpu, specifying KVM_CAP_IRQ_XICS in args[0] and 27the interrupt server number (i.e. the vcpu number from the XICS's 28point of view) in args[1] of the kvm_enable_cap struct. Each ICP has 2964 bits of state which can be read and written using the 30KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit 31state word has the following bitfields, starting at the 32least-significant end of the word: 33 34* Unused, 16 bits 35 36* Pending interrupt priority, 8 bits 37 Zero is the highest priority, 255 means no interrupt is pending. 38 39* Pending IPI (inter-processor interrupt) priority, 8 bits 40 Zero is the highest priority, 255 means no IPI is pending. 41 42* Pending interrupt source number, 24 bits 43 Zero means no interrupt pending, 2 means an IPI is pending 44 45* Current processor priority, 8 bits 46 Zero is the highest priority, meaning no interrupts can be 47 delivered, and 255 is the lowest priority. 48 49Each source has 64 bits of state that can be read and written using 50the KVM_GET_DEVICE_ATTR and KVM_SET_DEVICE_ATTR ioctls, specifying the 51KVM_DEV_XICS_GRP_SOURCES attribute group, with the attribute number being 52the interrupt source number. The 64 bit state word has the following 53bitfields, starting from the least-significant end of the word: 54 55* Destination (server number), 32 bits 56 This specifies where the interrupt should be sent, and is the 57 interrupt server number specified for the destination vcpu. 58 59* Priority, 8 bits 60 This is the priority specified for this interrupt source, where 0 is 61 the highest priority and 255 is the lowest. An interrupt with a 62 priority of 255 will never be delivered. 63 64* Level sensitive flag, 1 bit 65 This bit is 1 for a level-sensitive interrupt source, or 0 for 66 edge-sensitive (or MSI). 67 68* Masked flag, 1 bit 69 This bit is set to 1 if the interrupt is masked (cannot be delivered 70 regardless of its priority), for example by the ibm,int-off RTAS 71 call, or 0 if it is not masked. 72 73* Pending flag, 1 bit 74 This bit is 1 if the source has a pending interrupt, otherwise 0. 75 76Only one XICS instance may be created per VM.