tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1Qualcomm Technologies, Inc. IPQ8074 TLMM block
2
3This binding describes the Top Level Mode Multiplexer block found in the
4IPQ8074 platform.
5
6- compatible:
7 Usage: required
8 Value type: <string>
9 Definition: must be "qcom,ipq8074-pinctrl"
10
11- reg:
12 Usage: required
13 Value type: <prop-encoded-array>
14 Definition: the base address and size of the TLMM register space.
15
16- interrupts:
17 Usage: required
18 Value type: <prop-encoded-array>
19 Definition: should specify the TLMM summary IRQ.
20
21- interrupt-controller:
22 Usage: required
23 Value type: <none>
24 Definition: identifies this node as an interrupt controller
25
26- #interrupt-cells:
27 Usage: required
28 Value type: <u32>
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
31
32- gpio-controller:
33 Usage: required
34 Value type: <none>
35 Definition: identifies this node as a gpio controller
36
37- #gpio-cells:
38 Usage: required
39 Value type: <u32>
40 Definition: must be 2. Specifying the pin number and flags, as defined
41 in <dt-bindings/gpio/gpio.h>
42
43- gpio-ranges:
44 Usage: required
45 Definition: see ../gpio/gpio.txt
46
47- gpio-reserved-ranges:
48 Usage: optional
49 Definition: see ../gpio/gpio.txt
50
51Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52a general description of GPIO and interrupt bindings.
53
54Please refer to pinctrl-bindings.txt in this directory for details of the
55common pinctrl bindings used by client devices, including the meaning of the
56phrase "pin configuration node".
57
58The pin configuration nodes act as a container for an arbitrary number of
59subnodes. Each of these subnodes represents some desired configuration for a
60pin, a group, or a list of pins or groups. This configuration can include the
61mux function to select on those pin(s)/group(s), and various pin configuration
62parameters, such as pull-up, drive strength, etc.
63
64
65PIN CONFIGURATION NODES:
66
67The name of each subnode is not important; all subnodes should be enumerated
68and processed purely based on their content.
69
70Each subnode only affects those parameters that are explicitly listed. In
71other words, a subnode that lists a mux function but no pin configuration
72parameters implies no information about any pin configuration parameters.
73Similarly, a pin subnode that describes a pullup parameter implies no
74information about e.g. the mux function.
75
76
77The following generic properties as defined in pinctrl-bindings.txt are valid
78to specify in a pin configuration subnode:
79
80- pins:
81 Usage: required
82 Value type: <string-array>
83 Definition: List of gpio pins affected by the properties specified in
84 this subnode. Valid pins are:
85 gpio0-gpio69
86
87- function:
88 Usage: required
89 Value type: <string>
90 Definition: Specify the alternative function to be configured for the
91 specified pins. Functions are only valid for gpio pins.
92 Valid values are:
93 atest_char, atest_char0, atest_char1, atest_char2,
94 atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
95 audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
96 audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
97 blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
98 blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
99 blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
100 blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
101 blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1,
102 cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en,
103 ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0,
104 mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc,
105 mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk,
106 pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync,
107 pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1,
108 pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
109 qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
110 qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
111 qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
112 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
113 qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
114 qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b,
115 qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a,
116 wci2b, wci2c, wci2d
117
118- bias-disable:
119 Usage: optional
120 Value type: <none>
121 Definition: The specified pins should be configured as no pull.
122
123- bias-pull-down:
124 Usage: optional
125 Value type: <none>
126 Definition: The specified pins should be configured as pull down.
127
128- bias-pull-up:
129 Usage: optional
130 Value type: <none>
131 Definition: The specified pins should be configured as pull up.
132
133- output-high:
134 Usage: optional
135 Value type: <none>
136 Definition: The specified pins are configured in output mode, driven
137 high.
138
139- output-low:
140 Usage: optional
141 Value type: <none>
142 Definition: The specified pins are configured in output mode, driven
143 low.
144
145- drive-strength:
146 Usage: optional
147 Value type: <u32>
148 Definition: Selects the drive strength for the specified pins, in mA.
149 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
150
151Example:
152
153 tlmm: pinctrl@1000000 {
154 compatible = "qcom,ipq8074-pinctrl";
155 reg = <0x1000000 0x300000>;
156 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
157 gpio-controller;
158 #gpio-cells = <2>;
159 gpio-ranges = <&tlmm 0 0 70>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
162
163 uart2: uart2-default {
164 mux {
165 pins = "gpio23", "gpio24";
166 function = "blsp4_uart1";
167 };
168
169 rx {
170 pins = "gpio23";
171 drive-strength = <4>;
172 bias-disable;
173 };
174
175 tx {
176 pins = "gpio24";
177 drive-strength = <2>;
178 bias-pull-up;
179 };
180 };
181 };