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1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include <linux/types.h>
42
43/*
44 * VIRTIO_GPU_CMD_CTX_*
45 * VIRTIO_GPU_CMD_*_3D
46 */
47#define VIRTIO_GPU_F_VIRGL 0
48
49/*
50 * VIRTIO_GPU_CMD_GET_EDID
51 */
52#define VIRTIO_GPU_F_EDID 1
53
54enum virtio_gpu_ctrl_type {
55 VIRTIO_GPU_UNDEFINED = 0,
56
57 /* 2d commands */
58 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
59 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
60 VIRTIO_GPU_CMD_RESOURCE_UNREF,
61 VIRTIO_GPU_CMD_SET_SCANOUT,
62 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
63 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
64 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
65 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
66 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
67 VIRTIO_GPU_CMD_GET_CAPSET,
68 VIRTIO_GPU_CMD_GET_EDID,
69
70 /* 3d commands */
71 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
72 VIRTIO_GPU_CMD_CTX_DESTROY,
73 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
74 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
75 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
76 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
77 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
78 VIRTIO_GPU_CMD_SUBMIT_3D,
79
80 /* cursor commands */
81 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
82 VIRTIO_GPU_CMD_MOVE_CURSOR,
83
84 /* success responses */
85 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
86 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
87 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
88 VIRTIO_GPU_RESP_OK_CAPSET,
89 VIRTIO_GPU_RESP_OK_EDID,
90
91 /* error responses */
92 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
93 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
94 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
95 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
96 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
97 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
98};
99
100#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
101
102struct virtio_gpu_ctrl_hdr {
103 __le32 type;
104 __le32 flags;
105 __le64 fence_id;
106 __le32 ctx_id;
107 __le32 padding;
108};
109
110/* data passed in the cursor vq */
111
112struct virtio_gpu_cursor_pos {
113 __le32 scanout_id;
114 __le32 x;
115 __le32 y;
116 __le32 padding;
117};
118
119/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
120struct virtio_gpu_update_cursor {
121 struct virtio_gpu_ctrl_hdr hdr;
122 struct virtio_gpu_cursor_pos pos; /* update & move */
123 __le32 resource_id; /* update only */
124 __le32 hot_x; /* update only */
125 __le32 hot_y; /* update only */
126 __le32 padding;
127};
128
129/* data passed in the control vq, 2d related */
130
131struct virtio_gpu_rect {
132 __le32 x;
133 __le32 y;
134 __le32 width;
135 __le32 height;
136};
137
138/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
139struct virtio_gpu_resource_unref {
140 struct virtio_gpu_ctrl_hdr hdr;
141 __le32 resource_id;
142 __le32 padding;
143};
144
145/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
146struct virtio_gpu_resource_create_2d {
147 struct virtio_gpu_ctrl_hdr hdr;
148 __le32 resource_id;
149 __le32 format;
150 __le32 width;
151 __le32 height;
152};
153
154/* VIRTIO_GPU_CMD_SET_SCANOUT */
155struct virtio_gpu_set_scanout {
156 struct virtio_gpu_ctrl_hdr hdr;
157 struct virtio_gpu_rect r;
158 __le32 scanout_id;
159 __le32 resource_id;
160};
161
162/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
163struct virtio_gpu_resource_flush {
164 struct virtio_gpu_ctrl_hdr hdr;
165 struct virtio_gpu_rect r;
166 __le32 resource_id;
167 __le32 padding;
168};
169
170/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
171struct virtio_gpu_transfer_to_host_2d {
172 struct virtio_gpu_ctrl_hdr hdr;
173 struct virtio_gpu_rect r;
174 __le64 offset;
175 __le32 resource_id;
176 __le32 padding;
177};
178
179struct virtio_gpu_mem_entry {
180 __le64 addr;
181 __le32 length;
182 __le32 padding;
183};
184
185/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
186struct virtio_gpu_resource_attach_backing {
187 struct virtio_gpu_ctrl_hdr hdr;
188 __le32 resource_id;
189 __le32 nr_entries;
190};
191
192/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
193struct virtio_gpu_resource_detach_backing {
194 struct virtio_gpu_ctrl_hdr hdr;
195 __le32 resource_id;
196 __le32 padding;
197};
198
199/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
200#define VIRTIO_GPU_MAX_SCANOUTS 16
201struct virtio_gpu_resp_display_info {
202 struct virtio_gpu_ctrl_hdr hdr;
203 struct virtio_gpu_display_one {
204 struct virtio_gpu_rect r;
205 __le32 enabled;
206 __le32 flags;
207 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
208};
209
210/* data passed in the control vq, 3d related */
211
212struct virtio_gpu_box {
213 __le32 x, y, z;
214 __le32 w, h, d;
215};
216
217/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
218struct virtio_gpu_transfer_host_3d {
219 struct virtio_gpu_ctrl_hdr hdr;
220 struct virtio_gpu_box box;
221 __le64 offset;
222 __le32 resource_id;
223 __le32 level;
224 __le32 stride;
225 __le32 layer_stride;
226};
227
228/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
229#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
230struct virtio_gpu_resource_create_3d {
231 struct virtio_gpu_ctrl_hdr hdr;
232 __le32 resource_id;
233 __le32 target;
234 __le32 format;
235 __le32 bind;
236 __le32 width;
237 __le32 height;
238 __le32 depth;
239 __le32 array_size;
240 __le32 last_level;
241 __le32 nr_samples;
242 __le32 flags;
243 __le32 padding;
244};
245
246/* VIRTIO_GPU_CMD_CTX_CREATE */
247struct virtio_gpu_ctx_create {
248 struct virtio_gpu_ctrl_hdr hdr;
249 __le32 nlen;
250 __le32 padding;
251 char debug_name[64];
252};
253
254/* VIRTIO_GPU_CMD_CTX_DESTROY */
255struct virtio_gpu_ctx_destroy {
256 struct virtio_gpu_ctrl_hdr hdr;
257};
258
259/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
260struct virtio_gpu_ctx_resource {
261 struct virtio_gpu_ctrl_hdr hdr;
262 __le32 resource_id;
263 __le32 padding;
264};
265
266/* VIRTIO_GPU_CMD_SUBMIT_3D */
267struct virtio_gpu_cmd_submit {
268 struct virtio_gpu_ctrl_hdr hdr;
269 __le32 size;
270 __le32 padding;
271};
272
273#define VIRTIO_GPU_CAPSET_VIRGL 1
274#define VIRTIO_GPU_CAPSET_VIRGL2 2
275
276/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
277struct virtio_gpu_get_capset_info {
278 struct virtio_gpu_ctrl_hdr hdr;
279 __le32 capset_index;
280 __le32 padding;
281};
282
283/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
284struct virtio_gpu_resp_capset_info {
285 struct virtio_gpu_ctrl_hdr hdr;
286 __le32 capset_id;
287 __le32 capset_max_version;
288 __le32 capset_max_size;
289 __le32 padding;
290};
291
292/* VIRTIO_GPU_CMD_GET_CAPSET */
293struct virtio_gpu_get_capset {
294 struct virtio_gpu_ctrl_hdr hdr;
295 __le32 capset_id;
296 __le32 capset_version;
297};
298
299/* VIRTIO_GPU_RESP_OK_CAPSET */
300struct virtio_gpu_resp_capset {
301 struct virtio_gpu_ctrl_hdr hdr;
302 __u8 capset_data[];
303};
304
305/* VIRTIO_GPU_CMD_GET_EDID */
306struct virtio_gpu_cmd_get_edid {
307 struct virtio_gpu_ctrl_hdr hdr;
308 __le32 scanout;
309 __le32 padding;
310};
311
312/* VIRTIO_GPU_RESP_OK_EDID */
313struct virtio_gpu_resp_edid {
314 struct virtio_gpu_ctrl_hdr hdr;
315 __le32 size;
316 __le32 padding;
317 __u8 edid[1024];
318};
319
320#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
321
322struct virtio_gpu_config {
323 __u32 events_read;
324 __u32 events_clear;
325 __u32 num_scanouts;
326 __u32 num_capsets;
327};
328
329/* simple formats for fbcon/X use */
330enum virtio_gpu_formats {
331 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
332 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
333 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
334 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
335
336 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
337 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
338
339 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
340 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
341};
342
343#endif