tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/list.h>
21#include <linux/iommu.h>
22#include <linux/types.h>
23#include <linux/of_graph.h>
24#include <linux/of_device.h>
25#include <linux/sizes.h>
26#include <linux/kthread.h>
27
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_fb_helper.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36struct msm_kms;
37struct msm_gpu;
38struct msm_mmu;
39struct msm_mdss;
40struct msm_rd_state;
41struct msm_perf_state;
42struct msm_gem_submit;
43struct msm_fence_context;
44struct msm_gem_address_space;
45struct msm_gem_vma;
46
47#define MAX_CRTCS 8
48#define MAX_PLANES 20
49#define MAX_ENCODERS 8
50#define MAX_BRIDGES 8
51#define MAX_CONNECTORS 8
52
53#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
54
55struct msm_file_private {
56 rwlock_t queuelock;
57 struct list_head submitqueues;
58 int queueid;
59 struct msm_gem_address_space *aspace;
60};
61
62enum msm_mdp_plane_property {
63 PLANE_PROP_ZPOS,
64 PLANE_PROP_ALPHA,
65 PLANE_PROP_PREMULTIPLIED,
66 PLANE_PROP_MAX_NUM
67};
68
69#define MSM_GPU_MAX_RINGS 4
70#define MAX_H_TILES_PER_DISPLAY 2
71
72/**
73 * enum msm_display_caps - features/capabilities supported by displays
74 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
75 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
76 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
77 * @MSM_DISPLAY_CAP_EDID: EDID supported
78 */
79enum msm_display_caps {
80 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
81 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
82 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
83 MSM_DISPLAY_CAP_EDID = BIT(3),
84};
85
86/**
87 * enum msm_event_wait - type of HW events to wait for
88 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
89 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
90 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
91 */
92enum msm_event_wait {
93 MSM_ENC_COMMIT_DONE = 0,
94 MSM_ENC_TX_COMPLETE,
95 MSM_ENC_VBLANK,
96};
97
98/**
99 * struct msm_display_topology - defines a display topology pipeline
100 * @num_lm: number of layer mixers used
101 * @num_enc: number of compression encoder blocks used
102 * @num_intf: number of interfaces the panel is mounted on
103 */
104struct msm_display_topology {
105 u32 num_lm;
106 u32 num_enc;
107 u32 num_intf;
108};
109
110/**
111 * struct msm_display_info - defines display properties
112 * @intf_type: DRM_MODE_ENCODER_ type
113 * @capabilities: Bitmask of display flags
114 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
115 * @h_tile_instance: Controller instance used per tile. Number of elements is
116 * based on num_of_h_tiles
117 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
118 * used instead of panel TE in cmd mode panels
119 */
120struct msm_display_info {
121 int intf_type;
122 uint32_t capabilities;
123 uint32_t num_of_h_tiles;
124 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
125 bool is_te_using_watchdog_timer;
126};
127
128/* Commit/Event thread specific structure */
129struct msm_drm_thread {
130 struct drm_device *dev;
131 struct task_struct *thread;
132 unsigned int crtc_id;
133 struct kthread_worker worker;
134};
135
136struct msm_drm_private {
137
138 struct drm_device *dev;
139
140 struct msm_kms *kms;
141
142 /* subordinate devices, if present: */
143 struct platform_device *gpu_pdev;
144
145 /* top level MDSS wrapper device (for MDP5/DPU only) */
146 struct msm_mdss *mdss;
147
148 /* possibly this should be in the kms component, but it is
149 * shared by both mdp4 and mdp5..
150 */
151 struct hdmi *hdmi;
152
153 /* eDP is for mdp5 only, but kms has not been created
154 * when edp_bind() and edp_init() are called. Here is the only
155 * place to keep the edp instance.
156 */
157 struct msm_edp *edp;
158
159 /* DSI is shared by mdp4 and mdp5 */
160 struct msm_dsi *dsi[2];
161
162 /* when we have more than one 'msm_gpu' these need to be an array: */
163 struct msm_gpu *gpu;
164 struct msm_file_private *lastctx;
165 /* gpu is only set on open(), but we need this info earlier */
166 bool is_a2xx;
167
168 struct drm_fb_helper *fbdev;
169
170 struct msm_rd_state *rd; /* debugfs to dump all submits */
171 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
172 struct msm_perf_state *perf;
173
174 /* list of GEM objects: */
175 struct list_head inactive_list;
176
177 /* worker for delayed free of objects: */
178 struct work_struct free_work;
179 struct llist_head free_list;
180
181 struct workqueue_struct *wq;
182
183 unsigned int num_planes;
184 struct drm_plane *planes[MAX_PLANES];
185
186 unsigned int num_crtcs;
187 struct drm_crtc *crtcs[MAX_CRTCS];
188
189 struct msm_drm_thread event_thread[MAX_CRTCS];
190
191 unsigned int num_encoders;
192 struct drm_encoder *encoders[MAX_ENCODERS];
193
194 unsigned int num_bridges;
195 struct drm_bridge *bridges[MAX_BRIDGES];
196
197 unsigned int num_connectors;
198 struct drm_connector *connectors[MAX_CONNECTORS];
199
200 /* Properties */
201 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
202
203 /* VRAM carveout, used when no IOMMU: */
204 struct {
205 unsigned long size;
206 dma_addr_t paddr;
207 /* NOTE: mm managed at the page level, size is in # of pages
208 * and position mm_node->start is in # of pages:
209 */
210 struct drm_mm mm;
211 spinlock_t lock; /* Protects drm_mm node allocation/removal */
212 } vram;
213
214 struct notifier_block vmap_notifier;
215 struct shrinker shrinker;
216
217 struct drm_atomic_state *pm_state;
218};
219
220struct msm_format {
221 uint32_t pixel_format;
222};
223
224struct msm_pending_timer;
225
226int msm_atomic_prepare_fb(struct drm_plane *plane,
227 struct drm_plane_state *new_state);
228void msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
229 struct msm_kms *kms, int crtc_idx);
230void msm_atomic_commit_tail(struct drm_atomic_state *state);
231struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
232void msm_atomic_state_clear(struct drm_atomic_state *state);
233void msm_atomic_state_free(struct drm_atomic_state *state);
234
235int msm_gem_init_vma(struct msm_gem_address_space *aspace,
236 struct msm_gem_vma *vma, int npages);
237void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
238 struct msm_gem_vma *vma);
239void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
240 struct msm_gem_vma *vma);
241int msm_gem_map_vma(struct msm_gem_address_space *aspace,
242 struct msm_gem_vma *vma, int prot,
243 struct sg_table *sgt, int npages);
244void msm_gem_close_vma(struct msm_gem_address_space *aspace,
245 struct msm_gem_vma *vma);
246
247void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
248
249struct msm_gem_address_space *
250msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
251 const char *name);
252
253struct msm_gem_address_space *
254msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu,
255 const char *name, uint64_t va_start, uint64_t va_end);
256
257int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
258void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
259
260bool msm_use_mmu(struct drm_device *dev);
261
262void msm_gem_submit_free(struct msm_gem_submit *submit);
263int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
264 struct drm_file *file);
265
266void msm_gem_shrinker_init(struct drm_device *dev);
267void msm_gem_shrinker_cleanup(struct drm_device *dev);
268
269int msm_gem_mmap_obj(struct drm_gem_object *obj,
270 struct vm_area_struct *vma);
271int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
272vm_fault_t msm_gem_fault(struct vm_fault *vmf);
273uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
274int msm_gem_get_iova(struct drm_gem_object *obj,
275 struct msm_gem_address_space *aspace, uint64_t *iova);
276int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
277 struct msm_gem_address_space *aspace, uint64_t *iova);
278uint64_t msm_gem_iova(struct drm_gem_object *obj,
279 struct msm_gem_address_space *aspace);
280void msm_gem_unpin_iova(struct drm_gem_object *obj,
281 struct msm_gem_address_space *aspace);
282struct page **msm_gem_get_pages(struct drm_gem_object *obj);
283void msm_gem_put_pages(struct drm_gem_object *obj);
284int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
285 struct drm_mode_create_dumb *args);
286int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
287 uint32_t handle, uint64_t *offset);
288struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
289void *msm_gem_prime_vmap(struct drm_gem_object *obj);
290void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
291int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
292struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
293 struct dma_buf_attachment *attach, struct sg_table *sg);
294int msm_gem_prime_pin(struct drm_gem_object *obj);
295void msm_gem_prime_unpin(struct drm_gem_object *obj);
296void *msm_gem_get_vaddr(struct drm_gem_object *obj);
297void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
298void msm_gem_put_vaddr(struct drm_gem_object *obj);
299int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
300int msm_gem_sync_object(struct drm_gem_object *obj,
301 struct msm_fence_context *fctx, bool exclusive);
302void msm_gem_move_to_active(struct drm_gem_object *obj,
303 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
304void msm_gem_move_to_inactive(struct drm_gem_object *obj);
305int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
306int msm_gem_cpu_fini(struct drm_gem_object *obj);
307void msm_gem_free_object(struct drm_gem_object *obj);
308int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
309 uint32_t size, uint32_t flags, uint32_t *handle, char *name);
310struct drm_gem_object *msm_gem_new(struct drm_device *dev,
311 uint32_t size, uint32_t flags);
312struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
313 uint32_t size, uint32_t flags);
314void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
315 uint32_t flags, struct msm_gem_address_space *aspace,
316 struct drm_gem_object **bo, uint64_t *iova);
317void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
318 uint32_t flags, struct msm_gem_address_space *aspace,
319 struct drm_gem_object **bo, uint64_t *iova);
320void msm_gem_kernel_put(struct drm_gem_object *bo,
321 struct msm_gem_address_space *aspace, bool locked);
322struct drm_gem_object *msm_gem_import(struct drm_device *dev,
323 struct dma_buf *dmabuf, struct sg_table *sgt);
324void msm_gem_free_work(struct work_struct *work);
325
326__printf(2, 3)
327void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
328
329int msm_framebuffer_prepare(struct drm_framebuffer *fb,
330 struct msm_gem_address_space *aspace);
331void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
332 struct msm_gem_address_space *aspace);
333uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
334 struct msm_gem_address_space *aspace, int plane);
335struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
336const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
337struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
338 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
339struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
340 int w, int h, int p, uint32_t format);
341
342struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
343void msm_fbdev_free(struct drm_device *dev);
344
345struct hdmi;
346int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
347 struct drm_encoder *encoder);
348void __init msm_hdmi_register(void);
349void __exit msm_hdmi_unregister(void);
350
351struct msm_edp;
352void __init msm_edp_register(void);
353void __exit msm_edp_unregister(void);
354int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
355 struct drm_encoder *encoder);
356
357struct msm_dsi;
358#ifdef CONFIG_DRM_MSM_DSI
359void __init msm_dsi_register(void);
360void __exit msm_dsi_unregister(void);
361int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
362 struct drm_encoder *encoder);
363#else
364static inline void __init msm_dsi_register(void)
365{
366}
367static inline void __exit msm_dsi_unregister(void)
368{
369}
370static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
371 struct drm_device *dev,
372 struct drm_encoder *encoder)
373{
374 return -EINVAL;
375}
376#endif
377
378void __init msm_mdp_register(void);
379void __exit msm_mdp_unregister(void);
380void __init msm_dpu_register(void);
381void __exit msm_dpu_unregister(void);
382
383#ifdef CONFIG_DEBUG_FS
384void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
385void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
386void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
387int msm_debugfs_late_init(struct drm_device *dev);
388int msm_rd_debugfs_init(struct drm_minor *minor);
389void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
390__printf(3, 4)
391void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
392 const char *fmt, ...);
393int msm_perf_debugfs_init(struct drm_minor *minor);
394void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
395#else
396static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
397__printf(3, 4)
398static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
399 const char *fmt, ...) {}
400static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
401static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
402#endif
403
404struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
405
406struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
407 const char *name);
408void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
409 const char *dbgname);
410void msm_writel(u32 data, void __iomem *addr);
411u32 msm_readl(const void __iomem *addr);
412
413struct msm_gpu_submitqueue;
414int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
415struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
416 u32 id);
417int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
418 u32 prio, u32 flags, u32 *id);
419int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
420 struct drm_msm_submitqueue_query *args);
421int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
422void msm_submitqueue_close(struct msm_file_private *ctx);
423
424void msm_submitqueue_destroy(struct kref *kref);
425
426
427#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
428#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
429
430static inline int align_pitch(int width, int bpp)
431{
432 int bytespp = (bpp + 7) / 8;
433 /* adreno needs pitch aligned to 32 pixels: */
434 return bytespp * ALIGN(width, 32);
435}
436
437/* for the generated headers: */
438#define INVALID_IDX(idx) ({BUG(); 0;})
439#define fui(x) ({BUG(); 0;})
440#define util_float_to_half(x) ({BUG(); 0;})
441
442
443#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
444
445/* for conditionally setting boolean flag(s): */
446#define COND(bool, val) ((bool) ? (val) : 0)
447
448static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
449{
450 ktime_t now = ktime_get();
451 unsigned long remaining_jiffies;
452
453 if (ktime_compare(*timeout, now) < 0) {
454 remaining_jiffies = 0;
455 } else {
456 ktime_t rem = ktime_sub(*timeout, now);
457 struct timespec ts = ktime_to_timespec(rem);
458 remaining_jiffies = timespec_to_jiffies(&ts);
459 }
460
461 return remaining_jiffies;
462}
463
464#endif /* __MSM_DRV_H__ */