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1* Texas Instruments - dp83867 Giga bit ethernet phy
2
3Required properties:
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
6 for applicable values. Required only if interface type is
7 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
8 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
9 for applicable values. Required only if interface type is
10 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
11 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
12 for applicable values
13
14Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays
15 will be left at their default values, as set by the PHY's pin strapping.
16 The default strapping will use a delay of 2.00 ns. Thus
17 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
18 internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree
19 should use "rgmii-id" if internal delays are desired as this may be
20 changed in future to cause "rgmii" mode to disable delays.
21
22Optional property:
23 - ti,min-output-impedance - MAC Interface Impedance control to set
24 the programmable output impedance to
25 minimum value (35 ohms).
26 - ti,max-output-impedance - MAC Interface Impedance control to set
27 the programmable output impedance to
28 maximum value (70 ohms).
29 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
30 board has RX_DV/RX_CTRL pin strapped in
31 mode 1 or 2. To ensure PHY operation,
32 there are specific actions that
33 software needs to take when this pin is
34 strapped in these modes. See data manual
35 for details.
36 - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
37 for applicable values. The CLK_OUT pin can also
38 be disabled by this property. When omitted, the
39 PHY's default will be left as is.
40 - ti,sgmii-ref-clock-output-enable - This denotes which
41 SGMII configuration is used (4 or 6-wire modes).
42 Some MACs work with differential SGMII clock.
43 See data manual for details.
44
45Note: ti,min-output-impedance and ti,max-output-impedance are mutually
46 exclusive. When both properties are present ti,max-output-impedance
47 takes precedence.
48
49Default child nodes are standard Ethernet PHY device
50nodes as described in Documentation/devicetree/bindings/net/phy.txt
51
52Example:
53
54 ethernet-phy@0 {
55 reg = <0>;
56 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
57 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
58 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
59 };
60
61Datasheet can be found:
62http://www.ti.com/product/DP83867IR/datasheet