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1Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the 2Video Engine (VE) in Allwinner literature. 3 4The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting 5from the DRAM base. This requires specific memory allocation and handling. 6 7Required properties: 8- compatible : must be one of the following compatibles: 9 - "allwinner,sun4i-a10-video-engine" 10 - "allwinner,sun5i-a13-video-engine" 11 - "allwinner,sun7i-a20-video-engine" 12 - "allwinner,sun8i-a33-video-engine" 13 - "allwinner,sun8i-h3-video-engine" 14 - "allwinner,sun50i-a64-video-engine" 15 - "allwinner,sun50i-h5-video-engine" 16 - "allwinner,sun50i-h6-video-engine" 17- reg : register base and length of VE; 18- clocks : list of clock specifiers, corresponding to entries in 19 the clock-names property; 20- clock-names : should contain "ahb", "mod" and "ram" entries; 21- resets : phandle for reset; 22- interrupts : VE interrupt number; 23- allwinner,sram : SRAM region to use with the VE. 24 25Optional properties: 26- memory-region : CMA pool to use for buffers allocation instead of the 27 default CMA pool. 28 29Example: 30 31reserved-memory { 32 #address-cells = <1>; 33 #size-cells = <1>; 34 ranges; 35 36 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ 37 cma_pool: default-pool { 38 compatible = "shared-dma-pool"; 39 size = <0x6000000>; 40 alloc-ranges = <0x4a000000 0x6000000>; 41 reusable; 42 linux,cma-default; 43 }; 44}; 45 46video-codec@1c0e000 { 47 compatible = "allwinner,sun7i-a20-video-engine"; 48 reg = <0x01c0e000 0x1000>; 49 50 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, 51 <&ccu CLK_DRAM_VE>; 52 clock-names = "ahb", "mod", "ram"; 53 54 resets = <&ccu RST_VE>; 55 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 56 allwinner,sram = <&ve_sram 1>; 57};