tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 *
5 */
6
7#ifndef __MTK_CMDQ_MAILBOX_H__
8#define __MTK_CMDQ_MAILBOX_H__
9
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/types.h>
13
14#define CMDQ_INST_SIZE 8 /* instruction is 64-bit */
15#define CMDQ_SUBSYS_SHIFT 16
16#define CMDQ_OP_CODE_SHIFT 24
17#define CMDQ_JUMP_PASS CMDQ_INST_SIZE
18
19#define CMDQ_WFE_UPDATE BIT(31)
20#define CMDQ_WFE_WAIT BIT(15)
21#define CMDQ_WFE_WAIT_VALUE 0x1
22
23/*
24 * CMDQ_CODE_MASK:
25 * set write mask
26 * format: op mask
27 * CMDQ_CODE_WRITE:
28 * write value into target register
29 * format: op subsys address value
30 * CMDQ_CODE_JUMP:
31 * jump by offset
32 * format: op offset
33 * CMDQ_CODE_WFE:
34 * wait for event and clear
35 * it is just clear if no wait
36 * format: [wait] op event update:1 to_wait:1 wait:1
37 * [clear] op event update:1 to_wait:0 wait:0
38 * CMDQ_CODE_EOC:
39 * end of command
40 * format: op irq_flag
41 */
42enum cmdq_code {
43 CMDQ_CODE_MASK = 0x02,
44 CMDQ_CODE_WRITE = 0x04,
45 CMDQ_CODE_JUMP = 0x10,
46 CMDQ_CODE_WFE = 0x20,
47 CMDQ_CODE_EOC = 0x40,
48};
49
50enum cmdq_cb_status {
51 CMDQ_CB_NORMAL = 0,
52 CMDQ_CB_ERROR
53};
54
55struct cmdq_cb_data {
56 enum cmdq_cb_status sta;
57 void *data;
58};
59
60typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data);
61
62struct cmdq_task_cb {
63 cmdq_async_flush_cb cb;
64 void *data;
65};
66
67struct cmdq_pkt {
68 void *va_base;
69 dma_addr_t pa_base;
70 size_t cmd_buf_size; /* command occupied size */
71 size_t buf_size; /* real buffer size */
72 struct cmdq_task_cb cb;
73 struct cmdq_task_cb async_cb;
74 void *cl;
75};
76
77#endif /* __MTK_CMDQ_MAILBOX_H__ */