Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __REG_BITS_2700G_
3#define __REG_BITS_2700G_
4
5/* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
6#define UData(Data) ((unsigned long) (Data))
7#define Fld(Size, Shft) (((Size) << 16) + (Shft))
8#define FSize(Field) ((Field) >> 16)
9#define FShft(Field) ((Field) & 0x0000FFFF)
10#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
11#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
12#define F1stBit(Field) (UData (1) << FShft (Field))
13
14#define SYSRST_RST (1 << 0)
15
16/* SYSCLKSRC - SYSCLK Source Control Register */
17#define SYSCLKSRC_SEL Fld(2,0)
18#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
19#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
20#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
21
22/* PIXCLKSRC - PIXCLK Source Control Register */
23#define PIXCLKSRC_SEL Fld(2,0)
24#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
25#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
26#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
27
28/* Clock Disable Register */
29#define CLKSLEEP_SLP (1 << 0)
30
31/* Core PLL Control Register */
32#define CORE_PLL_M Fld(6,7)
33#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
34#define CORE_PLL_N Fld(3,4)
35#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
36#define CORE_PLL_P Fld(3,1)
37#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
38#define CORE_PLL_EN (1 << 0)
39
40/* Display PLL Control Register */
41#define DISP_PLL_M Fld(6,7)
42#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
43#define DISP_PLL_N Fld(3,4)
44#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
45#define DISP_PLL_P Fld(3,1)
46#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
47#define DISP_PLL_EN (1 << 0)
48
49/* PLL status register */
50#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
51#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
52#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
53#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
54
55/* Video and scale clock control register */
56#define VOVRCLK_EN (1 << 0)
57
58/* Pixel clock control register */
59#define PIXCLK_EN (1 << 0)
60
61/* Memory clock control register */
62#define MEMCLK_EN (1 << 0)
63
64/* MBX clock control register */
65#define MBXCLK_DIV Fld(2,2)
66#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
67#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
68#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
69#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
70#define MBXCLK_EN Fld(2,0)
71#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
72#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
73#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
74
75/* M24 clock control register */
76#define M24CLK_DIV Fld(2,1)
77#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
78#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
79#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
80#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
81#define M24CLK_EN (1 << 0)
82
83/* SDRAM clock control register */
84#define SDCLK_EN (1 << 0)
85
86/* PixClk Divisor Register */
87#define PIXCLKDIV_PD Fld(9,0)
88#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
89
90/* LCD Config control register */
91#define LCDCFG_IN_FMT Fld(3,28)
92#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
93#define LCDCFG_LCD1DEN_POL (1 << 27)
94#define LCDCFG_LCD1FCLK_POL (1 << 26)
95#define LCDCFG_LCD1LCLK_POL (1 << 25)
96#define LCDCFG_LCD1D_POL (1 << 24)
97#define LCDCFG_LCD2DEN_POL (1 << 23)
98#define LCDCFG_LCD2FCLK_POL (1 << 22)
99#define LCDCFG_LCD2LCLK_POL (1 << 21)
100#define LCDCFG_LCD2D_POL (1 << 20)
101#define LCDCFG_LCD1_TS (1 << 19)
102#define LCDCFG_LCD1D_DS (1 << 18)
103#define LCDCFG_LCD1C_DS (1 << 17)
104#define LCDCFG_LCD1_IS_IN (1 << 16)
105#define LCDCFG_LCD2_TS (1 << 3)
106#define LCDCFG_LCD2D_DS (1 << 2)
107#define LCDCFG_LCD2C_DS (1 << 1)
108#define LCDCFG_LCD2_IS_IN (1 << 0)
109
110/* On-Die Frame Buffer Power Control Register */
111#define ODFBPWR_SLOW (1 << 2)
112#define ODFBPWR_MODE Fld(2,0)
113#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
114#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
115#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
116#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
117
118/* On-Die Frame Buffer Power State Status Register */
119#define ODFBSTAT_ACT (1 << 2)
120#define ODFBSTAT_SLP (1 << 1)
121#define ODFBSTAT_SDN (1 << 0)
122
123/* LMRST - Local Memory (SDRAM) Reset */
124#define LMRST_MC_RST (1 << 0)
125
126/* LMCFG - Local Memory (SDRAM) Configuration Register */
127#define LMCFG_LMC_DS (1 << 5)
128#define LMCFG_LMD_DS (1 << 4)
129#define LMCFG_LMA_DS (1 << 3)
130#define LMCFG_LMC_TS (1 << 2)
131#define LMCFG_LMD_TS (1 << 1)
132#define LMCFG_LMA_TS (1 << 0)
133
134/* LMPWR - Local Memory (SDRAM) Power Control Register */
135#define LMPWR_MC_PWR_CNT Fld(2,0)
136#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
137#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
138#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
139
140/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
141#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
142#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
143#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
144#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
145
146/* LMTYPE - Local Memory (SDRAM) Type Register */
147#define LMTYPE_CASLAT Fld(3,10)
148#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
149#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
150#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
151#define LMTYPE_BKSZ Fld(2,8)
152#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
153#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
154#define LMTYPE_ROWSZ Fld(4,4)
155#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
156#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
157#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
158#define LMTYPE_COLSZ Fld(4,0)
159#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
160#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
161#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
162#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
163#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
164#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
165
166/* LMTIM - Local Memory (SDRAM) Timing Register */
167#define LMTIM_TRAS Fld(4,16)
168#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
169#define LMTIM_TRP Fld(4,12)
170#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
171#define LMTIM_TRCD Fld(4,8)
172#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
173#define LMTIM_TRC Fld(4,4)
174#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
175#define LMTIM_TDPL Fld(4,0)
176#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
177
178/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
179#define LMREFRESH_TREF Fld(2,0)
180#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
181
182/* GSCTRL - Graphics surface control register */
183#define GSCTRL_LUT_EN (1 << 31)
184#define GSCTRL_GPIXFMT Fld(4,27)
185#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
186#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
187#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
188#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
189#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
190#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
191#define GSCTRL_GAMMA_EN (1 << 26)
192
193#define GSCTRL_GSWIDTH Fld(11,11)
194#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
195 (((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
196
197#define GSCTRL_GSHEIGHT Fld(11,0)
198#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
199 (((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
200
201/* GBBASE fileds */
202#define GBBASE_GLALPHA Fld(8,24)
203#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
204
205#define GBBASE_COLKEY Fld(24,0)
206#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
207
208/* GDRCTRL fields */
209#define GDRCTRL_PIXDBL (1 << 31)
210#define GDRCTRL_PIXHLV (1 << 30)
211#define GDRCTRL_LNDBL (1 << 29)
212#define GDRCTRL_LNHLV (1 << 28)
213#define GDRCTRL_COLKEYM Fld(24,0)
214#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
215
216/* GSCADR graphics stream control address register fields */
217#define GSCADR_STR_EN (1 << 31)
218#define GSCADR_COLKEY_EN (1 << 30)
219#define GSCADR_COLKEYSRC (1 << 29)
220#define GSCADR_BLEND_M Fld(2,27)
221#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
222#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
223#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
224#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
225#define GSCADR_BLEND_POS Fld(2,24)
226#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
227#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
228#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
229#define GSCADR_GBASE_ADR Fld(23,0)
230#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
231
232/* GSADR graphics stride address register fields */
233#define GSADR_SRCSTRIDE Fld(10,22)
234#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
235#define GSADR_XSTART Fld(11,11)
236#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
237#define GSADR_YSTART Fld(11,0)
238#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
239
240/* GPLUT graphics palette register fields */
241#define GPLUT_LUTADR Fld(8,24)
242#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
243#define GPLUT_LUTDATA Fld(24,0)
244#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
245
246/* VSCTRL - Video Surface Control Register */
247#define VSCTRL_VPIXFMT Fld(4,27)
248#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
249#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
250#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
251#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
252#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
253#define VSCTRL_GAMMA_EN (1 << 26)
254#define VSCTRL_CSC_EN (1 << 25)
255#define VSCTRL_COSITED (1 << 22)
256#define VSCTRL_VSWIDTH Fld(11,11)
257#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
258 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
259#define VSCTRL_VSHEIGHT Fld(11,0)
260#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
261 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
262
263/* VBBASE - Video Blending Base Register */
264#define VBBASE_GLALPHA Fld(8,24)
265#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
266
267#define VBBASE_COLKEY Fld(24,0)
268#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
269
270/* VCMSK - Video Color Key Mask Register */
271#define VCMSK_COLKEY_M Fld(24,0)
272#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
273
274/* VSCADR - Video Stream Control Rddress Register */
275#define VSCADR_STR_EN (1 << 31)
276#define VSCADR_COLKEY_EN (1 << 30)
277#define VSCADR_COLKEYSRC (1 << 29)
278#define VSCADR_BLEND_M Fld(2,27)
279#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
280#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
281#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
282#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
283#define VSCADR_BLEND_POS Fld(2,24)
284#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
285#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
286#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
287#define VSCADR_VBASE_ADR Fld(23,0)
288#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
289
290/* VUBASE - Video U Base Register */
291#define VUBASE_UVHALFSTR (1 << 31)
292#define VUBASE_UBASE_ADR Fld(24,0)
293#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
294
295/* VVBASE - Video V Base Register */
296#define VVBASE_VBASE_ADR Fld(24,0)
297#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
298
299/* VSADR - Video Stride Address Register */
300#define VSADR_SRCSTRIDE Fld(10,22)
301#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
302#define VSADR_XSTART Fld(11,11)
303#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
304#define VSADR_YSTART Fld(11,0)
305#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
306
307/* VSCTRL - Video Surface Control Register */
308#define VSCTRL_VPIXFMT Fld(4,27)
309#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
310#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
311#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
312#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
313#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
314#define VSCTRL_GAMMA_EN (1 << 26)
315#define VSCTRL_CSC_EN (1 << 25)
316#define VSCTRL_COSITED (1 << 22)
317#define VSCTRL_VSWIDTH Fld(11,11)
318#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
319 (((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
320#define VSCTRL_VSHEIGHT Fld(11,0)
321#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
322 (((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
323
324/* VBBASE - Video Blending Base Register */
325#define VBBASE_GLALPHA Fld(8,24)
326#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
327
328#define VBBASE_COLKEY Fld(24,0)
329#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
330
331/* VCMSK - Video Color Key Mask Register */
332#define VCMSK_COLKEY_M Fld(24,0)
333#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
334
335/* VSCADR - Video Stream Control Rddress Register */
336#define VSCADR_STR_EN (1 << 31)
337#define VSCADR_COLKEY_EN (1 << 30)
338#define VSCADR_COLKEYSRC (1 << 29)
339#define VSCADR_BLEND_M Fld(2,27)
340#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
341#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
342#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
343#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
344#define VSCADR_BLEND_POS Fld(2,24)
345#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
346#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
347#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
348#define VSCADR_VBASE_ADR Fld(23,0)
349#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
350
351/* VUBASE - Video U Base Register */
352#define VUBASE_UVHALFSTR (1 << 31)
353#define VUBASE_UBASE_ADR Fld(24,0)
354#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
355
356/* VVBASE - Video V Base Register */
357#define VVBASE_VBASE_ADR Fld(24,0)
358#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
359
360/* VSADR - Video Stride Address Register */
361#define VSADR_SRCSTRIDE Fld(10,22)
362#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
363#define VSADR_XSTART Fld(11,11)
364#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
365#define VSADR_YSTART Fld(11,0)
366#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
367
368/* HCCTRL - Hardware Cursor Register fields */
369#define HCCTRL_CUR_EN (1 << 31)
370#define HCCTRL_COLKEY_EN (1 << 29)
371#define HCCTRL_COLKEYSRC (1 << 28)
372#define HCCTRL_BLEND_M Fld(2,26)
373#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
374#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
375#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
376#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
377#define HCCTRL_CPIXFMT Fld(3,23)
378#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
379#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
380#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
381#define HCCTRL_CBASE_ADR Fld(23,0)
382#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
383
384/* HCSIZE Hardware Cursor Size Register fields */
385#define HCSIZE_BLEND_POS Fld(2,29)
386#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
387#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
388#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
389#define HCSIZE_CWIDTH Fld(3,16)
390#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
391#define HCSIZE_CHEIGHT Fld(3,0)
392#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
393
394/* HCPOS Hardware Cursor Position Register fields */
395#define HCPOS_SWITCHSRC (1 << 30)
396#define HCPOS_CURBLINK Fld(6,24)
397#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
398#define HCPOS_XSTART Fld(12,12)
399#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
400#define HCPOS_YSTART Fld(12,0)
401#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
402
403/* HCBADR Hardware Cursor Blend Address Register */
404#define HCBADR_GLALPHA Fld(8,24)
405#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
406#define HCBADR_COLKEY Fld(24,0)
407#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
408
409/* HCCKMSK - Hardware Cursor Color Key Mask Register */
410#define HCCKMSK_COLKEY_M Fld(24,0)
411#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
412
413/* DSCTRL - Display sync control register */
414#define DSCTRL_SYNCGEN_EN (1 << 31)
415#define DSCTRL_DPL_RST (1 << 29)
416#define DSCTRL_PWRDN_M (1 << 28)
417#define DSCTRL_UPDSYNCCNT (1 << 26)
418#define DSCTRL_UPDINTCNT (1 << 25)
419#define DSCTRL_UPDCNT (1 << 24)
420#define DSCTRL_UPDWAIT Fld(4,16)
421#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
422#define DSCTRL_CLKPOL (1 << 11)
423#define DSCTRL_CSYNC_EN (1 << 10)
424#define DSCTRL_VS_SLAVE (1 << 7)
425#define DSCTRL_HS_SLAVE (1 << 6)
426#define DSCTRL_BLNK_POL (1 << 5)
427#define DSCTRL_BLNK_DIS (1 << 4)
428#define DSCTRL_VS_POL (1 << 3)
429#define DSCTRL_VS_DIS (1 << 2)
430#define DSCTRL_HS_POL (1 << 1)
431#define DSCTRL_HS_DIS (1 << 0)
432
433/* DHT01 - Display horizontal timing register 01 */
434#define DHT01_HBPS Fld(12,16)
435#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
436#define DHT01_HT Fld(12,0)
437#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
438
439/* DHT02 - Display horizontal timing register 02 */
440#define DHT02_HAS Fld(12,16)
441#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
442#define DHT02_HLBS Fld(12,0)
443#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
444
445/* DHT03 - Display horizontal timing register 03 */
446#define DHT03_HFPS Fld(12,16)
447#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
448#define DHT03_HRBS Fld(12,0)
449#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
450
451/* DVT01 - Display vertical timing register 01 */
452#define DVT01_VBPS Fld(12,16)
453#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
454#define DVT01_VT Fld(12,0)
455#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
456
457/* DVT02 - Display vertical timing register 02 */
458#define DVT02_VAS Fld(12,16)
459#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
460#define DVT02_VTBS Fld(12,0)
461#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
462
463/* DVT03 - Display vertical timing register 03 */
464#define DVT03_VFPS Fld(12,16)
465#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
466#define DVT03_VBBS Fld(12,0)
467#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
468
469/* DVECTRL - display vertical event control register */
470#define DVECTRL_VEVENT Fld(12,16)
471#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
472#define DVECTRL_VFETCH Fld(12,0)
473#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
474
475/* DHDET - display horizontal DE timing register */
476#define DHDET_HDES Fld(12,16)
477#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
478#define DHDET_HDEF Fld(12,0)
479#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
480
481/* DVDET - display vertical DE timing register */
482#define DVDET_VDES Fld(12,16)
483#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
484#define DVDET_VDEF Fld(12,0)
485#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
486
487/* DODMSK - display output data mask register */
488#define DODMSK_MASK_LVL (1 << 31)
489#define DODMSK_BLNK_LVL (1 << 30)
490#define DODMSK_MASK_B Fld(8,16)
491#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
492#define DODMSK_MASK_G Fld(8,8)
493#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
494#define DODMSK_MASK_R Fld(8,0)
495#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
496
497/* DBCOL - display border color control register */
498#define DBCOL_BORDCOL Fld(24,0)
499#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
500
501/* DVLNUM - display vertical line number register */
502#define DVLNUM_VLINE Fld(12,0)
503#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
504
505/* DMCTRL - Display Memory Control Register */
506#define DMCTRL_MEM_REF Fld(2,30)
507#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
508#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
509#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
510#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
511#define DMCTRL_UV_THRHLD Fld(6,24)
512#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
513#define DMCTRL_V_THRHLD Fld(7,16)
514#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
515#define DMCTRL_D_THRHLD Fld(7,8)
516#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
517#define DMCTRL_BURSTLEN Fld(6,0)
518#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
519
520/* DINTRS - Display Interrupt Status Register */
521#define DINTRS_CUR_OR_S (1 << 18)
522#define DINTRS_STR2_OR_S (1 << 17)
523#define DINTRS_STR1_OR_S (1 << 16)
524#define DINTRS_CUR_UR_S (1 << 6)
525#define DINTRS_STR2_UR_S (1 << 5)
526#define DINTRS_STR1_UR_S (1 << 4)
527#define DINTRS_VEVENT1_S (1 << 3)
528#define DINTRS_VEVENT0_S (1 << 2)
529#define DINTRS_HBLNK1_S (1 << 1)
530#define DINTRS_HBLNK0_S (1 << 0)
531
532/* DINTRE - Display Interrupt Enable Register */
533#define DINTRE_CUR_OR_EN (1 << 18)
534#define DINTRE_STR2_OR_EN (1 << 17)
535#define DINTRE_STR1_OR_EN (1 << 16)
536#define DINTRE_CUR_UR_EN (1 << 6)
537#define DINTRE_STR2_UR_EN (1 << 5)
538#define DINTRE_STR1_UR_EN (1 << 4)
539#define DINTRE_VEVENT1_EN (1 << 3)
540#define DINTRE_VEVENT0_EN (1 << 2)
541#define DINTRE_HBLNK1_EN (1 << 1)
542#define DINTRE_HBLNK0_EN (1 << 0)
543
544/* DINTRS - Display Interrupt Status Register */
545#define DINTRS_CUR_OR_S (1 << 18)
546#define DINTRS_STR2_OR_S (1 << 17)
547#define DINTRS_STR1_OR_S (1 << 16)
548#define DINTRS_CUR_UR_S (1 << 6)
549#define DINTRS_STR2_UR_S (1 << 5)
550#define DINTRS_STR1_UR_S (1 << 4)
551#define DINTRS_VEVENT1_S (1 << 3)
552#define DINTRS_VEVENT0_S (1 << 2)
553#define DINTRS_HBLNK1_S (1 << 1)
554#define DINTRS_HBLNK0_S (1 << 0)
555
556/* DINTRE - Display Interrupt Enable Register */
557#define DINTRE_CUR_OR_EN (1 << 18)
558#define DINTRE_STR2_OR_EN (1 << 17)
559#define DINTRE_STR1_OR_EN (1 << 16)
560#define DINTRE_CUR_UR_EN (1 << 6)
561#define DINTRE_STR2_UR_EN (1 << 5)
562#define DINTRE_STR1_UR_EN (1 << 4)
563#define DINTRE_VEVENT1_EN (1 << 3)
564#define DINTRE_VEVENT0_EN (1 << 2)
565#define DINTRE_HBLNK1_EN (1 << 1)
566#define DINTRE_HBLNK0_EN (1 << 0)
567
568
569/* DLSTS - display load status register */
570#define DLSTS_RLD_ADONE (1 << 23)
571/* #define DLSTS_RLD_ADOUT Fld(23,0) */
572
573/* DLLCTRL - display list load control register */
574#define DLLCTRL_RLD_ADRLN Fld(8,24)
575#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
576
577/* CLIPCTRL - Clipping Control Register */
578#define CLIPCTRL_HSKIP Fld(11,16)
579#define Clipctrl_Hskip ((x) << FShft(CLIPCTRL_HSKIP))
580#define CLIPCTRL_VSKIP Fld(11,0)
581#define Clipctrl_Vskip ((x) << FShft(CLIPCTRL_VSKIP))
582
583/* SPOCTRL - Scale Pitch/Order Control Register */
584#define SPOCTRL_H_SC_BP (1 << 31)
585#define SPOCTRL_V_SC_BP (1 << 30)
586#define SPOCTRL_HV_SC_OR (1 << 29)
587#define SPOCTRL_VS_UR_C (1 << 27)
588#define SPOCTRL_VORDER Fld(2,16)
589#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
590#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
591#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
592#define SPOCTRL_VPITCH Fld(16,0)
593#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
594
595/* SVCTRL - Scale Vertical Control Register */
596#define SVCTRL_INITIAL1 Fld(16,16)
597#define Svctrl_Initial1(x) ((x) << FShft(SVCTRL_INITIAL1))
598#define SVCTRL_INITIAL2 Fld(16,0)
599#define Svctrl_Initial2(x) ((x) << FShft(SVCTRL_INITIAL2))
600
601/* SHCTRL - Scale Horizontal Control Register */
602#define SHCTRL_HINITIAL Fld(16,16)
603#define Shctrl_Hinitial(x) ((x) << FShft(SHCTRL_HINITIAL))
604#define SHCTRL_HDECIM (1 << 15)
605#define SHCTRL_HPITCH Fld(15,0)
606#define Shctrl_Hpitch(x) ((x) << FShft(SHCTRL_HPITCH))
607
608/* SSSIZE - Scale Surface Size Register */
609#define SSSIZE_SC_WIDTH Fld(11,16)
610#define Sssize_Sc_Width(x) ((x) << FShft(SSSIZE_SC_WIDTH))
611#define SSSIZE_SC_HEIGHT Fld(11,0)
612#define Sssize_Sc_Height(x) ((x) << FShft(SSSIZE_SC_HEIGHT))
613
614#endif /* __REG_BITS_2700G_ */