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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7#define PCI_FIND_CAP_TTL 48
8
9#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
10
11extern const unsigned char pcie_link_speed[];
12extern bool pci_early_dump;
13
14bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
15
16/* Functions internal to the PCI core code */
17
18int pci_create_sysfs_dev_files(struct pci_dev *pdev);
19void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
20#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
21static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
22{ return; }
23static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
24{ return; }
25#else
26void pci_create_firmware_label_files(struct pci_dev *pdev);
27void pci_remove_firmware_label_files(struct pci_dev *pdev);
28#endif
29void pci_cleanup_rom(struct pci_dev *dev);
30
31enum pci_mmap_api {
32 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
33 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
34};
35int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
36 enum pci_mmap_api mmap_api);
37
38int pci_probe_reset_function(struct pci_dev *dev);
39int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
40int pci_bus_error_reset(struct pci_dev *dev);
41
42/**
43 * struct pci_platform_pm_ops - Firmware PM callbacks
44 *
45 * @bridge_d3: Does the bridge allow entering into D3
46 *
47 * @is_manageable: returns 'true' if given device is power manageable by the
48 * platform firmware
49 *
50 * @set_state: invokes the platform firmware to set the device's power state
51 *
52 * @get_state: queries the platform firmware for a device's current power state
53 *
54 * @refresh_state: asks the platform to refresh the device's power state data
55 *
56 * @choose_state: returns PCI power state of given device preferred by the
57 * platform; to be used during system-wide transitions from a
58 * sleeping state to the working state and vice versa
59 *
60 * @set_wakeup: enables/disables wakeup capability for the device
61 *
62 * @need_resume: returns 'true' if the given device (which is currently
63 * suspended) needs to be resumed to be configured for system
64 * wakeup.
65 *
66 * If given platform is generally capable of power managing PCI devices, all of
67 * these callbacks are mandatory.
68 */
69struct pci_platform_pm_ops {
70 bool (*bridge_d3)(struct pci_dev *dev);
71 bool (*is_manageable)(struct pci_dev *dev);
72 int (*set_state)(struct pci_dev *dev, pci_power_t state);
73 pci_power_t (*get_state)(struct pci_dev *dev);
74 void (*refresh_state)(struct pci_dev *dev);
75 pci_power_t (*choose_state)(struct pci_dev *dev);
76 int (*set_wakeup)(struct pci_dev *dev, bool enable);
77 bool (*need_resume)(struct pci_dev *dev);
78};
79
80int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
81void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
82void pci_refresh_power_state(struct pci_dev *dev);
83void pci_power_up(struct pci_dev *dev);
84void pci_disable_enabled_device(struct pci_dev *dev);
85int pci_finish_runtime_suspend(struct pci_dev *dev);
86void pcie_clear_root_pme_status(struct pci_dev *dev);
87int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
88void pci_pme_restore(struct pci_dev *dev);
89bool pci_dev_need_resume(struct pci_dev *dev);
90void pci_dev_adjust_pme(struct pci_dev *dev);
91void pci_dev_complete_resume(struct pci_dev *pci_dev);
92void pci_config_pm_runtime_get(struct pci_dev *dev);
93void pci_config_pm_runtime_put(struct pci_dev *dev);
94void pci_pm_init(struct pci_dev *dev);
95void pci_ea_init(struct pci_dev *dev);
96void pci_allocate_cap_save_buffers(struct pci_dev *dev);
97void pci_free_cap_save_buffers(struct pci_dev *dev);
98bool pci_bridge_d3_possible(struct pci_dev *dev);
99void pci_bridge_d3_update(struct pci_dev *dev);
100
101static inline void pci_wakeup_event(struct pci_dev *dev)
102{
103 /* Wait 100 ms before the system can be put into a sleep state. */
104 pm_wakeup_event(&dev->dev, 100);
105}
106
107static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
108{
109 return !!(pci_dev->subordinate);
110}
111
112static inline bool pci_power_manageable(struct pci_dev *pci_dev)
113{
114 /*
115 * Currently we allow normal PCI devices and PCI bridges transition
116 * into D3 if their bridge_d3 is set.
117 */
118 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
119}
120
121int pci_vpd_init(struct pci_dev *dev);
122void pci_vpd_release(struct pci_dev *dev);
123void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
124void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
125
126/* PCI /proc functions */
127#ifdef CONFIG_PROC_FS
128int pci_proc_attach_device(struct pci_dev *dev);
129int pci_proc_detach_device(struct pci_dev *dev);
130int pci_proc_detach_bus(struct pci_bus *bus);
131#else
132static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
133static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
134static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
135#endif
136
137/* Functions for PCI Hotplug drivers to use */
138int pci_hp_add_bridge(struct pci_dev *dev);
139
140#ifdef HAVE_PCI_LEGACY
141void pci_create_legacy_files(struct pci_bus *bus);
142void pci_remove_legacy_files(struct pci_bus *bus);
143#else
144static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
145static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
146#endif
147
148/* Lock for read/write access to pci device and bus lists */
149extern struct rw_semaphore pci_bus_sem;
150extern struct mutex pci_slot_mutex;
151
152extern raw_spinlock_t pci_lock;
153
154extern unsigned int pci_pm_d3_delay;
155
156#ifdef CONFIG_PCI_MSI
157void pci_no_msi(void);
158#else
159static inline void pci_no_msi(void) { }
160#endif
161
162static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
163{
164 u16 control;
165
166 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
167 control &= ~PCI_MSI_FLAGS_ENABLE;
168 if (enable)
169 control |= PCI_MSI_FLAGS_ENABLE;
170 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
171}
172
173static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
174{
175 u16 ctrl;
176
177 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
178 ctrl &= ~clear;
179 ctrl |= set;
180 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
181}
182
183void pci_realloc_get_opt(char *);
184
185static inline int pci_no_d1d2(struct pci_dev *dev)
186{
187 unsigned int parent_dstates = 0;
188
189 if (dev->bus->self)
190 parent_dstates = dev->bus->self->no_d1d2;
191 return (dev->no_d1d2 || parent_dstates);
192
193}
194extern const struct attribute_group *pci_dev_groups[];
195extern const struct attribute_group *pcibus_groups[];
196extern const struct device_type pci_dev_type;
197extern const struct attribute_group *pci_bus_groups[];
198
199
200/**
201 * pci_match_one_device - Tell if a PCI device structure has a matching
202 * PCI device id structure
203 * @id: single PCI device id structure to match
204 * @dev: the PCI device structure to match against
205 *
206 * Returns the matching pci_device_id structure or %NULL if there is no match.
207 */
208static inline const struct pci_device_id *
209pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
210{
211 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
212 (id->device == PCI_ANY_ID || id->device == dev->device) &&
213 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
214 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
215 !((id->class ^ dev->class) & id->class_mask))
216 return id;
217 return NULL;
218}
219
220/* PCI slot sysfs helper code */
221#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
222
223extern struct kset *pci_slots_kset;
224
225struct pci_slot_attribute {
226 struct attribute attr;
227 ssize_t (*show)(struct pci_slot *, char *);
228 ssize_t (*store)(struct pci_slot *, const char *, size_t);
229};
230#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
231
232enum pci_bar_type {
233 pci_bar_unknown, /* Standard PCI BAR probe */
234 pci_bar_io, /* An I/O port BAR */
235 pci_bar_mem32, /* A 32-bit memory BAR */
236 pci_bar_mem64, /* A 64-bit memory BAR */
237};
238
239int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
240bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
241 int crs_timeout);
242bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
243 int crs_timeout);
244int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
245
246int pci_setup_device(struct pci_dev *dev);
247int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
248 struct resource *res, unsigned int reg);
249void pci_configure_ari(struct pci_dev *dev);
250void __pci_bus_size_bridges(struct pci_bus *bus,
251 struct list_head *realloc_head);
252void __pci_bus_assign_resources(const struct pci_bus *bus,
253 struct list_head *realloc_head,
254 struct list_head *fail_head);
255bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
256
257void pci_reassigndev_resource_alignment(struct pci_dev *dev);
258void pci_disable_bridge_window(struct pci_dev *dev);
259
260/* PCIe link information */
261#define PCIE_SPEED2STR(speed) \
262 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
263 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
264 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
265 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
266 "Unknown speed")
267
268/* PCIe speed to Mb/s reduced by encoding overhead */
269#define PCIE_SPEED2MBS_ENC(speed) \
270 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
271 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
272 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
273 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
274 0)
275
276enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
277enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
278u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
279 enum pcie_link_width *width);
280void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
281void pcie_report_downtraining(struct pci_dev *dev);
282
283/* Single Root I/O Virtualization */
284struct pci_sriov {
285 int pos; /* Capability position */
286 int nres; /* Number of resources */
287 u32 cap; /* SR-IOV Capabilities */
288 u16 ctrl; /* SR-IOV Control */
289 u16 total_VFs; /* Total VFs associated with the PF */
290 u16 initial_VFs; /* Initial VFs associated with the PF */
291 u16 num_VFs; /* Number of VFs available */
292 u16 offset; /* First VF Routing ID offset */
293 u16 stride; /* Following VF stride */
294 u16 vf_device; /* VF device ID */
295 u32 pgsz; /* Page size for BAR alignment */
296 u8 link; /* Function Dependency Link */
297 u8 max_VF_buses; /* Max buses consumed by VFs */
298 u16 driver_max_VFs; /* Max num VFs driver supports */
299 struct pci_dev *dev; /* Lowest numbered PF */
300 struct pci_dev *self; /* This PF */
301 u32 class; /* VF device */
302 u8 hdr_type; /* VF header type */
303 u16 subsystem_vendor; /* VF subsystem vendor */
304 u16 subsystem_device; /* VF subsystem device */
305 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
306 bool drivers_autoprobe; /* Auto probing of VFs by driver */
307};
308
309/**
310 * pci_dev_set_io_state - Set the new error state if possible.
311 *
312 * @dev - pci device to set new error_state
313 * @new - the state we want dev to be in
314 *
315 * Must be called with device_lock held.
316 *
317 * Returns true if state has been changed to the requested state.
318 */
319static inline bool pci_dev_set_io_state(struct pci_dev *dev,
320 pci_channel_state_t new)
321{
322 bool changed = false;
323
324 device_lock_assert(&dev->dev);
325 switch (new) {
326 case pci_channel_io_perm_failure:
327 switch (dev->error_state) {
328 case pci_channel_io_frozen:
329 case pci_channel_io_normal:
330 case pci_channel_io_perm_failure:
331 changed = true;
332 break;
333 }
334 break;
335 case pci_channel_io_frozen:
336 switch (dev->error_state) {
337 case pci_channel_io_frozen:
338 case pci_channel_io_normal:
339 changed = true;
340 break;
341 }
342 break;
343 case pci_channel_io_normal:
344 switch (dev->error_state) {
345 case pci_channel_io_frozen:
346 case pci_channel_io_normal:
347 changed = true;
348 break;
349 }
350 break;
351 }
352 if (changed)
353 dev->error_state = new;
354 return changed;
355}
356
357static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
358{
359 device_lock(&dev->dev);
360 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
361 device_unlock(&dev->dev);
362
363 return 0;
364}
365
366static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
367{
368 return dev->error_state == pci_channel_io_perm_failure;
369}
370
371/* pci_dev priv_flags */
372#define PCI_DEV_ADDED 0
373
374static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
375{
376 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
377}
378
379static inline bool pci_dev_is_added(const struct pci_dev *dev)
380{
381 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
382}
383
384#ifdef CONFIG_PCIEAER
385#include <linux/aer.h>
386
387#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
388
389struct aer_err_info {
390 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
391 int error_dev_num;
392
393 unsigned int id:16;
394
395 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
396 unsigned int __pad1:5;
397 unsigned int multi_error_valid:1;
398
399 unsigned int first_error:5;
400 unsigned int __pad2:2;
401 unsigned int tlp_header_valid:1;
402
403 unsigned int status; /* COR/UNCOR Error Status */
404 unsigned int mask; /* COR/UNCOR Error Mask */
405 struct aer_header_log_regs tlp; /* TLP Header */
406};
407
408int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
409void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
410#endif /* CONFIG_PCIEAER */
411
412#ifdef CONFIG_PCIE_DPC
413void pci_save_dpc_state(struct pci_dev *dev);
414void pci_restore_dpc_state(struct pci_dev *dev);
415#else
416static inline void pci_save_dpc_state(struct pci_dev *dev) {}
417static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
418#endif
419
420#ifdef CONFIG_PCI_ATS
421void pci_restore_ats_state(struct pci_dev *dev);
422#else
423static inline void pci_restore_ats_state(struct pci_dev *dev)
424{
425}
426#endif /* CONFIG_PCI_ATS */
427
428#ifdef CONFIG_PCI_IOV
429int pci_iov_init(struct pci_dev *dev);
430void pci_iov_release(struct pci_dev *dev);
431void pci_iov_remove(struct pci_dev *dev);
432void pci_iov_update_resource(struct pci_dev *dev, int resno);
433resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
434void pci_restore_iov_state(struct pci_dev *dev);
435int pci_iov_bus_range(struct pci_bus *bus);
436
437#else
438static inline int pci_iov_init(struct pci_dev *dev)
439{
440 return -ENODEV;
441}
442static inline void pci_iov_release(struct pci_dev *dev)
443
444{
445}
446static inline void pci_iov_remove(struct pci_dev *dev)
447{
448}
449static inline void pci_restore_iov_state(struct pci_dev *dev)
450{
451}
452static inline int pci_iov_bus_range(struct pci_bus *bus)
453{
454 return 0;
455}
456
457#endif /* CONFIG_PCI_IOV */
458
459unsigned long pci_cardbus_resource_alignment(struct resource *);
460
461static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
462 struct resource *res)
463{
464#ifdef CONFIG_PCI_IOV
465 int resno = res - dev->resource;
466
467 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
468 return pci_sriov_resource_alignment(dev, resno);
469#endif
470 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
471 return pci_cardbus_resource_alignment(res);
472 return resource_alignment(res);
473}
474
475void pci_enable_acs(struct pci_dev *dev);
476#ifdef CONFIG_PCI_QUIRKS
477int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
478int pci_dev_specific_enable_acs(struct pci_dev *dev);
479int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
480#else
481static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
482 u16 acs_flags)
483{
484 return -ENOTTY;
485}
486static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
487{
488 return -ENOTTY;
489}
490static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
491{
492 return -ENOTTY;
493}
494#endif
495
496/* PCI error reporting and recovery */
497void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
498 u32 service);
499
500bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
501#ifdef CONFIG_PCIEASPM
502void pcie_aspm_init_link_state(struct pci_dev *pdev);
503void pcie_aspm_exit_link_state(struct pci_dev *pdev);
504void pcie_aspm_pm_state_change(struct pci_dev *pdev);
505void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
506#else
507static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
508static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
509static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
510static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
511#endif
512
513#ifdef CONFIG_PCIEASPM_DEBUG
514void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
515void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
516#else
517static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
518static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
519#endif
520
521#ifdef CONFIG_PCIE_PTM
522void pci_ptm_init(struct pci_dev *dev);
523#else
524static inline void pci_ptm_init(struct pci_dev *dev) { }
525#endif
526
527struct pci_dev_reset_methods {
528 u16 vendor;
529 u16 device;
530 int (*reset)(struct pci_dev *dev, int probe);
531};
532
533#ifdef CONFIG_PCI_QUIRKS
534int pci_dev_specific_reset(struct pci_dev *dev, int probe);
535#else
536static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
537{
538 return -ENOTTY;
539}
540#endif
541
542#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
543int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
544 struct resource *res);
545#endif
546
547u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
548int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
549int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
550static inline u64 pci_rebar_size_to_bytes(int size)
551{
552 return 1ULL << (size + 20);
553}
554
555struct device_node;
556
557#ifdef CONFIG_OF
558int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
559int of_get_pci_domain_nr(struct device_node *node);
560int of_pci_get_max_link_speed(struct device_node *node);
561
562#else
563static inline int
564of_pci_parse_bus_range(struct device_node *node, struct resource *res)
565{
566 return -EINVAL;
567}
568
569static inline int
570of_get_pci_domain_nr(struct device_node *node)
571{
572 return -1;
573}
574
575static inline int
576of_pci_get_max_link_speed(struct device_node *node)
577{
578 return -EINVAL;
579}
580#endif /* CONFIG_OF */
581
582#if defined(CONFIG_OF_ADDRESS)
583int devm_of_pci_get_host_bridge_resources(struct device *dev,
584 unsigned char busno, unsigned char bus_max,
585 struct list_head *resources, resource_size_t *io_base);
586#else
587static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
588 unsigned char busno, unsigned char bus_max,
589 struct list_head *resources, resource_size_t *io_base)
590{
591 return -EINVAL;
592}
593#endif
594
595#ifdef CONFIG_PCIEAER
596void pci_no_aer(void);
597void pci_aer_init(struct pci_dev *dev);
598void pci_aer_exit(struct pci_dev *dev);
599extern const struct attribute_group aer_stats_attr_group;
600void pci_aer_clear_fatal_status(struct pci_dev *dev);
601void pci_aer_clear_device_status(struct pci_dev *dev);
602#else
603static inline void pci_no_aer(void) { }
604static inline void pci_aer_init(struct pci_dev *d) { }
605static inline void pci_aer_exit(struct pci_dev *d) { }
606static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
607static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
608#endif
609
610#endif /* DRIVERS_PCI_H */