Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

at v5.3 371 lines 17 kB view raw
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (c) 2018, Intel Corporation. */ 3 4/* Machine-generated file */ 5 6#ifndef _ICE_HW_AUTOGEN_H_ 7#define _ICE_HW_AUTOGEN_H_ 8 9#define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096)) 10#define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096)) 11#define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096)) 12#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4)) 13#define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4)) 14#define QTX_COMM_HEAD_HEAD_S 0 15#define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0) 16#define PF_FW_ARQBAH 0x00080180 17#define PF_FW_ARQBAL 0x00080080 18#define PF_FW_ARQH 0x00080380 19#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0) 20#define PF_FW_ARQLEN 0x00080280 21#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 22#define PF_FW_ARQLEN_ARQVFE_M BIT(28) 23#define PF_FW_ARQLEN_ARQOVFL_M BIT(29) 24#define PF_FW_ARQLEN_ARQCRIT_M BIT(30) 25#define PF_FW_ARQLEN_ARQENABLE_M BIT(31) 26#define PF_FW_ARQT 0x00080480 27#define PF_FW_ATQBAH 0x00080100 28#define PF_FW_ATQBAL 0x00080000 29#define PF_FW_ATQH 0x00080300 30#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0) 31#define PF_FW_ATQLEN 0x00080200 32#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 33#define PF_FW_ATQLEN_ATQVFE_M BIT(28) 34#define PF_FW_ATQLEN_ATQOVFL_M BIT(29) 35#define PF_FW_ATQLEN_ATQCRIT_M BIT(30) 36#define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4)) 37#define PF_FW_ATQLEN_ATQENABLE_M BIT(31) 38#define PF_FW_ATQT 0x00080400 39#define PF_MBX_ARQBAH 0x0022E400 40#define PF_MBX_ARQBAL 0x0022E380 41#define PF_MBX_ARQH 0x0022E500 42#define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0) 43#define PF_MBX_ARQLEN 0x0022E480 44#define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0) 45#define PF_MBX_ARQLEN_ARQENABLE_M BIT(31) 46#define PF_MBX_ARQT 0x0022E580 47#define PF_MBX_ATQBAH 0x0022E180 48#define PF_MBX_ATQBAL 0x0022E100 49#define PF_MBX_ATQH 0x0022E280 50#define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0) 51#define PF_MBX_ATQLEN 0x0022E200 52#define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0) 53#define PF_MBX_ATQLEN_ATQENABLE_M BIT(31) 54#define PF_MBX_ATQT 0x0022E300 55#define PRTDCB_GENS 0x00083020 56#define PRTDCB_GENS_DCBX_STATUS_S 0 57#define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0) 58#define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256)) 59#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0 60#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, 0) 61#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8 62#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M ICE_M(0x3F, 8) 63#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16 64#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M ICE_M(0x3F, 16) 65#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24 66#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M ICE_M(0x3F, 24) 67#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4)) 68#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0 69#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0) 70#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30 71#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30) 72#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4)) 73#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0 74#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0) 75#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30 76#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30) 77#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4)) 78#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0 79#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0) 80#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30 81#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30) 82#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4)) 83#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0 84#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0) 85#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30 86#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30) 87#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) 88#define QRXFLXP_CNTXT_RXDID_IDX_S 0 89#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0) 90#define QRXFLXP_CNTXT_RXDID_PRIO_S 8 91#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8) 92#define GLGEN_RSTAT 0x000B8188 93#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0) 94#define GLGEN_RSTCTL 0x000B8180 95#define GLGEN_RSTCTL_GRSTDEL_S 0 96#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S) 97#define GLGEN_RSTAT_RESET_TYPE_S 2 98#define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2) 99#define GLGEN_RTRIG 0x000B8190 100#define GLGEN_RTRIG_CORER_M BIT(0) 101#define GLGEN_RTRIG_GLOBR_M BIT(1) 102#define GLGEN_STAT 0x000B612C 103#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) 104#define PFGEN_CTRL 0x00091000 105#define PFGEN_CTRL_PFSWR_M BIT(0) 106#define PFGEN_STATE 0x00088000 107#define PRTGEN_STATUS 0x000B8100 108#define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4)) 109#define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4)) 110#define VPGEN_VFRSTAT_VFRD_M BIT(0) 111#define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4)) 112#define VPGEN_VFRTRIG_VFSWR_M BIT(0) 113#define PFHMC_ERRORDATA 0x00520500 114#define PFHMC_ERRORINFO 0x00520400 115#define GLINT_CTL 0x0016CC54 116#define GLINT_CTL_DIS_AUTOMASK_M BIT(0) 117#define GLINT_CTL_ITR_GRAN_200_S 16 118#define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16) 119#define GLINT_CTL_ITR_GRAN_100_S 20 120#define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20) 121#define GLINT_CTL_ITR_GRAN_50_S 24 122#define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24) 123#define GLINT_CTL_ITR_GRAN_25_S 28 124#define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28) 125#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) 126#define GLINT_DYN_CTL_INTENA_M BIT(0) 127#define GLINT_DYN_CTL_CLEARPBA_M BIT(1) 128#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2) 129#define GLINT_DYN_CTL_ITR_INDX_S 3 130#define GLINT_DYN_CTL_INTERVAL_S 5 131#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25) 132#define GLINT_DYN_CTL_INTENA_MSK_M BIT(31) 133#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4)) 134#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) 135#define GLINT_RATE_INTRL_ENA_M BIT(6) 136#define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4)) 137#define GLINT_VECT2FUNC_VF_NUM_S 0 138#define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0) 139#define GLINT_VECT2FUNC_PF_NUM_S 12 140#define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12) 141#define GLINT_VECT2FUNC_IS_PF_S 16 142#define GLINT_VECT2FUNC_IS_PF_M BIT(16) 143#define PFINT_FW_CTL 0x0016C800 144#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 145#define PFINT_FW_CTL_ITR_INDX_S 11 146#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11) 147#define PFINT_FW_CTL_CAUSE_ENA_M BIT(30) 148#define PFINT_MBX_CTL 0x0016B280 149#define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 150#define PFINT_MBX_CTL_ITR_INDX_S 11 151#define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11) 152#define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30) 153#define PFINT_OICR 0x0016CA00 154#define PFINT_OICR_ECC_ERR_M BIT(16) 155#define PFINT_OICR_MAL_DETECT_M BIT(19) 156#define PFINT_OICR_GRST_M BIT(20) 157#define PFINT_OICR_PCI_EXCEPTION_M BIT(21) 158#define PFINT_OICR_HMC_ERR_M BIT(26) 159#define PFINT_OICR_PE_CRITERR_M BIT(28) 160#define PFINT_OICR_VFLR_M BIT(29) 161#define PFINT_OICR_SWINT_M BIT(31) 162#define PFINT_OICR_CTL 0x0016CA80 163#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0) 164#define PFINT_OICR_CTL_ITR_INDX_S 11 165#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11) 166#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30) 167#define PFINT_OICR_ENA 0x0016C900 168#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4)) 169#define QINT_RQCTL_MSIX_INDX_S 0 170#define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 171#define QINT_RQCTL_ITR_INDX_S 11 172#define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11) 173#define QINT_RQCTL_CAUSE_ENA_M BIT(30) 174#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4)) 175#define QINT_TQCTL_MSIX_INDX_S 0 176#define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0) 177#define QINT_TQCTL_ITR_INDX_S 11 178#define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11) 179#define QINT_TQCTL_CAUSE_ENA_M BIT(30) 180#define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4)) 181#define VPINT_ALLOC_FIRST_S 0 182#define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0) 183#define VPINT_ALLOC_LAST_S 12 184#define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12) 185#define VPINT_ALLOC_VALID_M BIT(31) 186#define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4)) 187#define VPINT_ALLOC_PCI_FIRST_S 0 188#define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0) 189#define VPINT_ALLOC_PCI_LAST_S 12 190#define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12) 191#define VPINT_ALLOC_PCI_VALID_M BIT(31) 192#define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4)) 193#define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30) 194#define GLLAN_RCTL_0 0x002941F8 195#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4)) 196#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4)) 197#define QRX_CTRL_MAX_INDEX 2047 198#define QRX_CTRL_QENA_REQ_S 0 199#define QRX_CTRL_QENA_REQ_M BIT(0) 200#define QRX_CTRL_QENA_STAT_S 2 201#define QRX_CTRL_QENA_STAT_M BIT(2) 202#define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4)) 203#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4)) 204#define QRX_TAIL_MAX_INDEX 2047 205#define QRX_TAIL_TAIL_S 0 206#define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0) 207#define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4)) 208#define VPLAN_RX_QBASE_VFFIRSTQ_S 0 209#define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0) 210#define VPLAN_RX_QBASE_VFNUMQ_S 16 211#define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 212#define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4)) 213#define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0) 214#define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4)) 215#define VPLAN_TX_QBASE_VFFIRSTQ_S 0 216#define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0) 217#define VPLAN_TX_QBASE_VFNUMQ_S 16 218#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16) 219#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4)) 220#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0) 221#define GL_MDET_RX 0x00294C00 222#define GL_MDET_RX_QNUM_S 0 223#define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0) 224#define GL_MDET_RX_VF_NUM_S 15 225#define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15) 226#define GL_MDET_RX_PF_NUM_S 23 227#define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23) 228#define GL_MDET_RX_MAL_TYPE_S 26 229#define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26) 230#define GL_MDET_RX_VALID_M BIT(31) 231#define GL_MDET_TX_PQM 0x002D2E00 232#define GL_MDET_TX_PQM_PF_NUM_S 0 233#define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0) 234#define GL_MDET_TX_PQM_VF_NUM_S 4 235#define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4) 236#define GL_MDET_TX_PQM_QNUM_S 12 237#define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12) 238#define GL_MDET_TX_PQM_MAL_TYPE_S 26 239#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26) 240#define GL_MDET_TX_PQM_VALID_M BIT(31) 241#define GL_MDET_TX_TCLAN 0x000FC068 242#define GL_MDET_TX_TCLAN_QNUM_S 0 243#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0) 244#define GL_MDET_TX_TCLAN_VF_NUM_S 15 245#define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15) 246#define GL_MDET_TX_TCLAN_PF_NUM_S 23 247#define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23) 248#define GL_MDET_TX_TCLAN_MAL_TYPE_S 26 249#define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26) 250#define GL_MDET_TX_TCLAN_VALID_M BIT(31) 251#define PF_MDET_RX 0x00294280 252#define PF_MDET_RX_VALID_M BIT(0) 253#define PF_MDET_TX_PQM 0x002D2C80 254#define PF_MDET_TX_PQM_VALID_M BIT(0) 255#define PF_MDET_TX_TCLAN 0x000FC000 256#define PF_MDET_TX_TCLAN_VALID_M BIT(0) 257#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4)) 258#define VP_MDET_RX_VALID_M BIT(0) 259#define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4)) 260#define VP_MDET_TX_PQM_VALID_M BIT(0) 261#define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4)) 262#define VP_MDET_TX_TCLAN_VALID_M BIT(0) 263#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) 264#define VP_MDET_TX_TDPU_VALID_M BIT(0) 265#define GLNVM_FLA 0x000B6108 266#define GLNVM_FLA_LOCKED_M BIT(6) 267#define GLNVM_GENS 0x000B6100 268#define GLNVM_GENS_SR_SIZE_S 5 269#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5) 270#define GLNVM_ULD 0x000B6008 271#define GLNVM_ULD_CORER_DONE_M BIT(3) 272#define GLNVM_ULD_GLOBR_DONE_M BIT(4) 273#define GLPCI_CNF2 0x000BE004 274#define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1) 275#define PF_FUNC_RID 0x0009E880 276#define PF_FUNC_RID_FUNC_NUM_S 0 277#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0) 278#define PF_PCI_CIAA 0x0009E580 279#define PF_PCI_CIAA_VF_NUM_S 12 280#define PF_PCI_CIAD 0x0009E500 281#define GL_PWR_MODE_CTL 0x000B820C 282#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30 283#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30) 284#define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8)) 285#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8)) 286#define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8)) 287#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8)) 288#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8)) 289#define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8)) 290#define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8)) 291#define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8)) 292#define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8)) 293#define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8)) 294#define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8)) 295#define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8)) 296#define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8)) 297#define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8)) 298#define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8)) 299#define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8)) 300#define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8)) 301#define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8)) 302#define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8)) 303#define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8)) 304#define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8)) 305#define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8)) 306#define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8)) 307#define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8)) 308#define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8)) 309#define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8)) 310#define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8)) 311#define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8)) 312#define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8)) 313#define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8)) 314#define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8)) 315#define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8)) 316#define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8)) 317#define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8)) 318#define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8)) 319#define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8)) 320#define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8)) 321#define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8)) 322#define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8)) 323#define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8)) 324#define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8)) 325#define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8)) 326#define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8)) 327#define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8)) 328#define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8)) 329#define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8)) 330#define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8)) 331#define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8)) 332#define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64)) 333#define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64)) 334#define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64)) 335#define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64)) 336#define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8)) 337#define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8)) 338#define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8)) 339#define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8)) 340#define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8)) 341#define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64)) 342#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8)) 343#define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8)) 344#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8)) 345#define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8)) 346#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8)) 347#define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8)) 348#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8)) 349#define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8)) 350#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8)) 351#define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8)) 352#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8)) 353#define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8)) 354#define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8)) 355#define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8)) 356#define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8)) 357#define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8)) 358#define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8)) 359#define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4)) 360#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4)) 361#define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8)) 362#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8)) 363#define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8)) 364#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8)) 365#define PF_VT_PFALLOC_HIF 0x0009DD80 366#define VSIQF_HKEY_MAX_INDEX 12 367#define VSIQF_HLUT_MAX_INDEX 15 368#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) 369#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1) 370 371#endif /* _ICE_HW_AUTOGEN_H_ */