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Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26#include "amdgpu_socbb.h"
27
28struct common_firmware_header {
29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
31 uint16_t header_version_major; /* header version */
32 uint16_t header_version_minor; /* header version */
33 uint16_t ip_version_major; /* IP version */
34 uint16_t ip_version_minor; /* IP version */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
39};
40
41/* version_major=1, version_minor=0 */
42struct mc_firmware_header_v1_0 {
43 struct common_firmware_header header;
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46};
47
48/* version_major=1, version_minor=0 */
49struct smc_firmware_header_v1_0 {
50 struct common_firmware_header header;
51 uint32_t ucode_start_addr;
52};
53
54/* version_major=2, version_minor=0 */
55struct smc_firmware_header_v2_0 {
56 struct smc_firmware_header_v1_0 v1_0;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
58 uint32_t ppt_size_bytes; /* soft pptable size */
59};
60
61struct smc_soft_pptable_entry {
62 uint32_t id;
63 uint32_t ppt_offset_bytes;
64 uint32_t ppt_size_bytes;
65};
66
67/* version_major=2, version_minor=1 */
68struct smc_firmware_header_v2_1 {
69 struct smc_firmware_header_v1_0 v1_0;
70 uint32_t pptable_count;
71 uint32_t pptable_entry_offset;
72};
73
74/* version_major=1, version_minor=0 */
75struct psp_firmware_header_v1_0 {
76 struct common_firmware_header header;
77 uint32_t ucode_feature_version;
78 uint32_t sos_offset_bytes;
79 uint32_t sos_size_bytes;
80};
81
82/* version_major=1, version_minor=1 */
83struct psp_firmware_header_v1_1 {
84 struct psp_firmware_header_v1_0 v1_0;
85 uint32_t toc_header_version;
86 uint32_t toc_offset_bytes;
87 uint32_t toc_size_bytes;
88 uint32_t kdb_header_version;
89 uint32_t kdb_offset_bytes;
90 uint32_t kdb_size_bytes;
91};
92
93/* version_major=1, version_minor=0 */
94struct ta_firmware_header_v1_0 {
95 struct common_firmware_header header;
96 uint32_t ta_xgmi_ucode_version;
97 uint32_t ta_xgmi_offset_bytes;
98 uint32_t ta_xgmi_size_bytes;
99 uint32_t ta_ras_ucode_version;
100 uint32_t ta_ras_offset_bytes;
101 uint32_t ta_ras_size_bytes;
102};
103
104/* version_major=1, version_minor=0 */
105struct gfx_firmware_header_v1_0 {
106 struct common_firmware_header header;
107 uint32_t ucode_feature_version;
108 uint32_t jt_offset; /* jt location */
109 uint32_t jt_size; /* size of jt */
110};
111
112/* version_major=1, version_minor=0 */
113struct mes_firmware_header_v1_0 {
114 struct common_firmware_header header;
115 uint32_t mes_ucode_version;
116 uint32_t mes_ucode_size_bytes;
117 uint32_t mes_ucode_offset_bytes;
118 uint32_t mes_ucode_data_version;
119 uint32_t mes_ucode_data_size_bytes;
120 uint32_t mes_ucode_data_offset_bytes;
121 uint32_t mes_uc_start_addr_lo;
122 uint32_t mes_uc_start_addr_hi;
123 uint32_t mes_data_start_addr_lo;
124 uint32_t mes_data_start_addr_hi;
125};
126
127/* version_major=1, version_minor=0 */
128struct rlc_firmware_header_v1_0 {
129 struct common_firmware_header header;
130 uint32_t ucode_feature_version;
131 uint32_t save_and_restore_offset;
132 uint32_t clear_state_descriptor_offset;
133 uint32_t avail_scratch_ram_locations;
134 uint32_t master_pkt_description_offset;
135};
136
137/* version_major=2, version_minor=0 */
138struct rlc_firmware_header_v2_0 {
139 struct common_firmware_header header;
140 uint32_t ucode_feature_version;
141 uint32_t jt_offset; /* jt location */
142 uint32_t jt_size; /* size of jt */
143 uint32_t save_and_restore_offset;
144 uint32_t clear_state_descriptor_offset;
145 uint32_t avail_scratch_ram_locations;
146 uint32_t reg_restore_list_size;
147 uint32_t reg_list_format_start;
148 uint32_t reg_list_format_separate_start;
149 uint32_t starting_offsets_start;
150 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
151 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
152 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
153 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
154 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
155 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
156 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
157 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
158};
159
160/* version_major=2, version_minor=1 */
161struct rlc_firmware_header_v2_1 {
162 struct rlc_firmware_header_v2_0 v2_0;
163 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
164 uint32_t save_restore_list_cntl_ucode_ver;
165 uint32_t save_restore_list_cntl_feature_ver;
166 uint32_t save_restore_list_cntl_size_bytes;
167 uint32_t save_restore_list_cntl_offset_bytes;
168 uint32_t save_restore_list_gpm_ucode_ver;
169 uint32_t save_restore_list_gpm_feature_ver;
170 uint32_t save_restore_list_gpm_size_bytes;
171 uint32_t save_restore_list_gpm_offset_bytes;
172 uint32_t save_restore_list_srm_ucode_ver;
173 uint32_t save_restore_list_srm_feature_ver;
174 uint32_t save_restore_list_srm_size_bytes;
175 uint32_t save_restore_list_srm_offset_bytes;
176};
177
178/* version_major=1, version_minor=0 */
179struct sdma_firmware_header_v1_0 {
180 struct common_firmware_header header;
181 uint32_t ucode_feature_version;
182 uint32_t ucode_change_version;
183 uint32_t jt_offset; /* jt location */
184 uint32_t jt_size; /* size of jt */
185};
186
187/* version_major=1, version_minor=1 */
188struct sdma_firmware_header_v1_1 {
189 struct sdma_firmware_header_v1_0 v1_0;
190 uint32_t digest_size;
191};
192
193/* gpu info payload */
194struct gpu_info_firmware_v1_0 {
195 uint32_t gc_num_se;
196 uint32_t gc_num_cu_per_sh;
197 uint32_t gc_num_sh_per_se;
198 uint32_t gc_num_rb_per_se;
199 uint32_t gc_num_tccs;
200 uint32_t gc_num_gprs;
201 uint32_t gc_num_max_gs_thds;
202 uint32_t gc_gs_table_depth;
203 uint32_t gc_gsprim_buff_depth;
204 uint32_t gc_parameter_cache_depth;
205 uint32_t gc_double_offchip_lds_buffer;
206 uint32_t gc_wave_size;
207 uint32_t gc_max_waves_per_simd;
208 uint32_t gc_max_scratch_slots_per_cu;
209 uint32_t gc_lds_size;
210};
211
212struct gpu_info_firmware_v1_1 {
213 struct gpu_info_firmware_v1_0 v1_0;
214 uint32_t num_sc_per_sh;
215 uint32_t num_packer_per_sc;
216};
217
218/* gpu info payload
219 * version_major=1, version_minor=1 */
220struct gpu_info_firmware_v1_2 {
221 struct gpu_info_firmware_v1_1 v1_1;
222 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
223};
224
225/* version_major=1, version_minor=0 */
226struct gpu_info_firmware_header_v1_0 {
227 struct common_firmware_header header;
228 uint16_t version_major; /* version */
229 uint16_t version_minor; /* version */
230};
231
232/* version_major=1, version_minor=0 */
233struct dmcu_firmware_header_v1_0 {
234 struct common_firmware_header header;
235 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
236 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
237};
238
239/* header is fixed size */
240union amdgpu_firmware_header {
241 struct common_firmware_header common;
242 struct mc_firmware_header_v1_0 mc;
243 struct smc_firmware_header_v1_0 smc;
244 struct smc_firmware_header_v2_0 smc_v2_0;
245 struct psp_firmware_header_v1_0 psp;
246 struct psp_firmware_header_v1_1 psp_v1_1;
247 struct ta_firmware_header_v1_0 ta;
248 struct gfx_firmware_header_v1_0 gfx;
249 struct rlc_firmware_header_v1_0 rlc;
250 struct rlc_firmware_header_v2_0 rlc_v2_0;
251 struct rlc_firmware_header_v2_1 rlc_v2_1;
252 struct sdma_firmware_header_v1_0 sdma;
253 struct sdma_firmware_header_v1_1 sdma_v1_1;
254 struct gpu_info_firmware_header_v1_0 gpu_info;
255 struct dmcu_firmware_header_v1_0 dmcu;
256 uint8_t raw[0x100];
257};
258
259/*
260 * fw loading support
261 */
262enum AMDGPU_UCODE_ID {
263 AMDGPU_UCODE_ID_SDMA0 = 0,
264 AMDGPU_UCODE_ID_SDMA1,
265 AMDGPU_UCODE_ID_CP_CE,
266 AMDGPU_UCODE_ID_CP_PFP,
267 AMDGPU_UCODE_ID_CP_ME,
268 AMDGPU_UCODE_ID_CP_MEC1,
269 AMDGPU_UCODE_ID_CP_MEC1_JT,
270 AMDGPU_UCODE_ID_CP_MEC2,
271 AMDGPU_UCODE_ID_CP_MEC2_JT,
272 AMDGPU_UCODE_ID_CP_MES,
273 AMDGPU_UCODE_ID_CP_MES_DATA,
274 AMDGPU_UCODE_ID_RLC_G,
275 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
276 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
277 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
278 AMDGPU_UCODE_ID_STORAGE,
279 AMDGPU_UCODE_ID_SMC,
280 AMDGPU_UCODE_ID_UVD,
281 AMDGPU_UCODE_ID_UVD1,
282 AMDGPU_UCODE_ID_VCE,
283 AMDGPU_UCODE_ID_VCN,
284 AMDGPU_UCODE_ID_DMCU_ERAM,
285 AMDGPU_UCODE_ID_DMCU_INTV,
286 AMDGPU_UCODE_ID_VCN0_RAM,
287 AMDGPU_UCODE_ID_VCN1_RAM,
288 AMDGPU_UCODE_ID_MAXIMUM,
289};
290
291/* engine firmware status */
292enum AMDGPU_UCODE_STATUS {
293 AMDGPU_UCODE_STATUS_INVALID,
294 AMDGPU_UCODE_STATUS_NOT_LOADED,
295 AMDGPU_UCODE_STATUS_LOADED,
296};
297
298enum amdgpu_firmware_load_type {
299 AMDGPU_FW_LOAD_DIRECT = 0,
300 AMDGPU_FW_LOAD_SMU,
301 AMDGPU_FW_LOAD_PSP,
302 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
303};
304
305/* conform to smu_ucode_xfer_cz.h */
306#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
307#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
308#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
309#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
310#define AMDGPU_CPME_UCODE_LOADED 0x00000010
311#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
312#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
313#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
314
315/* amdgpu firmware info */
316struct amdgpu_firmware_info {
317 /* ucode ID */
318 enum AMDGPU_UCODE_ID ucode_id;
319 /* request_firmware */
320 const struct firmware *fw;
321 /* starting mc address */
322 uint64_t mc_addr;
323 /* kernel linear address */
324 void *kaddr;
325 /* ucode_size_bytes */
326 uint32_t ucode_size;
327 /* starting tmr mc address */
328 uint32_t tmr_mc_addr_lo;
329 uint32_t tmr_mc_addr_hi;
330};
331
332struct amdgpu_firmware {
333 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
334 enum amdgpu_firmware_load_type load_type;
335 struct amdgpu_bo *fw_buf;
336 unsigned int fw_size;
337 unsigned int max_ucodes;
338 /* firmwares are loaded by psp instead of smu from vega10 */
339 const struct amdgpu_psp_funcs *funcs;
340 struct amdgpu_bo *rbuf;
341 struct mutex mutex;
342
343 /* gpu info firmware data pointer */
344 const struct firmware *gpu_info_fw;
345
346 void *fw_buf_ptr;
347 uint64_t fw_buf_mc;
348};
349
350void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
351void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
352void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
353void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
354void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
355void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
356void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
357int amdgpu_ucode_validate(const struct firmware *fw);
358bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
359 uint16_t hdr_major, uint16_t hdr_minor);
360
361int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
362int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
363int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
364void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
365void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
366
367enum amdgpu_firmware_load_type
368amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
369
370#endif