Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_CACHE_H
6#define __ASM_CACHE_H
7
8#include <asm/cputype.h>
9
10#define CTR_L1IP_SHIFT 14
11#define CTR_L1IP_MASK 3
12#define CTR_DMINLINE_SHIFT 16
13#define CTR_IMINLINE_SHIFT 0
14#define CTR_ERG_SHIFT 20
15#define CTR_CWG_SHIFT 24
16#define CTR_CWG_MASK 15
17#define CTR_IDC_SHIFT 28
18#define CTR_DIC_SHIFT 29
19
20#define CTR_CACHE_MINLINE_MASK \
21 (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
22
23#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
24
25#define ICACHE_POLICY_VPIPT 0
26#define ICACHE_POLICY_VIPT 2
27#define ICACHE_POLICY_PIPT 3
28
29#define L1_CACHE_SHIFT (6)
30#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
31
32
33#define CLIDR_LOUU_SHIFT 27
34#define CLIDR_LOC_SHIFT 24
35#define CLIDR_LOUIS_SHIFT 21
36
37#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
38#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
39#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
40
41/*
42 * Memory returned by kmalloc() may be used for DMA, so we must make
43 * sure that all such allocations are cache aligned. Otherwise,
44 * unrelated code may cause parts of the buffer to be read into the
45 * cache before the transfer is done, causing old data to be seen by
46 * the CPU.
47 */
48#define ARCH_DMA_MINALIGN (128)
49
50#ifdef CONFIG_KASAN_SW_TAGS
51#define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
52#endif
53
54#ifndef __ASSEMBLY__
55
56#include <linux/bitops.h>
57
58#define ICACHEF_ALIASING 0
59#define ICACHEF_VPIPT 1
60extern unsigned long __icache_flags;
61
62/*
63 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
64 * permitted in the I-cache.
65 */
66static inline int icache_is_aliasing(void)
67{
68 return test_bit(ICACHEF_ALIASING, &__icache_flags);
69}
70
71static inline int icache_is_vpipt(void)
72{
73 return test_bit(ICACHEF_VPIPT, &__icache_flags);
74}
75
76static inline u32 cache_type_cwg(void)
77{
78 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
79}
80
81#define __read_mostly __attribute__((__section__(".data..read_mostly")))
82
83static inline int cache_line_size_of_cpu(void)
84{
85 u32 cwg = cache_type_cwg();
86
87 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
88}
89
90int cache_line_size(void);
91
92/*
93 * Read the effective value of CTR_EL0.
94 *
95 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
96 * section D10.2.33 "CTR_EL0, Cache Type Register" :
97 *
98 * CTR_EL0.IDC reports the data cache clean requirements for
99 * instruction to data coherence.
100 *
101 * 0 - dcache clean to PoU is required unless :
102 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
103 * 1 - dcache clean to PoU is not required for i-to-d coherence.
104 *
105 * This routine provides the CTR_EL0 with the IDC field updated to the
106 * effective state.
107 */
108static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
109{
110 u32 ctr = read_cpuid_cachetype();
111
112 if (!(ctr & BIT(CTR_IDC_SHIFT))) {
113 u64 clidr = read_sysreg(clidr_el1);
114
115 if (CLIDR_LOC(clidr) == 0 ||
116 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
117 ctr |= BIT(CTR_IDC_SHIFT);
118 }
119
120 return ctr;
121}
122
123#endif /* __ASSEMBLY__ */
124
125#endif