tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/hardware/iop3xx.h
4 *
5 * Intel IOP32X and IOP33X register definitions
6 *
7 * Author: Rory Bolt <rorybolt@pacbell.net>
8 * Copyright (C) 2002 Rory Bolt
9 * Copyright (C) 2004 Intel Corp.
10 */
11
12#ifndef __IOP3XX_H
13#define __IOP3XX_H
14
15/*
16 * IOP3XX GPIO handling
17 */
18#define IOP3XX_GPIO_LINE(x) (x)
19
20#ifndef __ASSEMBLY__
21extern int init_atu;
22extern int iop3xx_get_init_atu(void);
23#endif
24
25
26/*
27 * IOP3XX processor registers
28 */
29#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
30#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
31#define IOP3XX_PERIPHERAL_SIZE 0x00002000
32#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
33 IOP3XX_PERIPHERAL_SIZE - 1)
34#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
35 IOP3XX_PERIPHERAL_SIZE - 1)
36#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
37 (IOP3XX_PERIPHERAL_PHYS_BASE\
38 - IOP3XX_PERIPHERAL_VIRT_BASE))
39#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
40
41/* Address Translation Unit */
42#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
43#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
44#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
45#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
46#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
47#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
48#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
49#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
50#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
51#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
52#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
53#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
54#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
55#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
56#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
57#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
58#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
59#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
60#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
61#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
62#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
63#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
64#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
65#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
66#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
67#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
68#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
69#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
70#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
71#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
72#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
73#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
74#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
75#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
76#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
77#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
78#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
79#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
80#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
81#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
82#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
83#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
84#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
85#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
86#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
87#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
88#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
89#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
90#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
91#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
92#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
93#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
94#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
95#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
96#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
97#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
98#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
99#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
100#define IOP3XX_ATUCR_OUT_EN (1 << 1)
101
102#define IOP3XX_INIT_ATU_DEFAULT 0
103#define IOP3XX_INIT_ATU_DISABLE -1
104#define IOP3XX_INIT_ATU_ENABLE 1
105
106/* Messaging Unit */
107#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
108#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
109#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
110#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
111#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
112#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
113#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
114#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
115#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
116#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
117#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
118#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
119#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
120#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
121#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
122#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
123#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
124#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
125#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
126#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
127#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
128
129/* DMA Controller */
130#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
131 (0x400 + (chan << 6)))
132#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
133
134/* Peripheral bus interface */
135#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
136#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
137#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
138#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
139#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
140#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
141#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
142#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
143#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
144#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
145#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
146#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
147#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
148#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
149#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
150#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
151#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
152
153/* Peripheral performance monitoring unit */
154#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
155#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
156#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
157#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
158/* PERCR0 DOESN'T EXIST - index from 1! */
159#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
160
161/* Timers */
162#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
163#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
164#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
165#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
166#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
167#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
168#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
169#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
170#define IOP_TMR_EN 0x02
171#define IOP_TMR_RELOAD 0x04
172#define IOP_TMR_PRIVILEGED 0x08
173#define IOP_TMR_RATIO_1_1 0x00
174
175/* Watchdog timer definitions */
176#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
177#define IOP_WDTCR_EN 0xe1e1e1e1
178/* iop3xx does not support stopping the watchdog, so we just re-arm */
179#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM)
180#define IOP_WDTCR_DIS (IOP_WDTCR_EN)
181
182/* Application accelerator unit */
183#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
184#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
185
186/* I2C bus interface unit */
187#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
188#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
189#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
190#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
191#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
192#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
193#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
194#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
195#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
196#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
197
198
199/*
200 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
201 */
202#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
203#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
204
205#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
206#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
207
208#ifndef __ASSEMBLY__
209
210#include <linux/types.h>
211#include <linux/reboot.h>
212
213void iop3xx_map_io(void);
214void iop_init_cp6_handler(void);
215void iop_init_time(unsigned long tickrate);
216void iop3xx_restart(enum reboot_mode, const char *);
217
218static inline u32 read_tmr0(void)
219{
220 u32 val;
221 asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
222 return val;
223}
224
225static inline void write_tmr0(u32 val)
226{
227 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
228}
229
230static inline void write_tmr1(u32 val)
231{
232 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
233}
234
235static inline u32 read_tcr0(void)
236{
237 u32 val;
238 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
239 return val;
240}
241
242static inline void write_tcr0(u32 val)
243{
244 asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
245}
246
247static inline u32 read_tcr1(void)
248{
249 u32 val;
250 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
251 return val;
252}
253
254static inline void write_tcr1(u32 val)
255{
256 asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
257}
258
259static inline void write_trr0(u32 val)
260{
261 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
262}
263
264static inline void write_trr1(u32 val)
265{
266 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
267}
268
269static inline void write_tisr(u32 val)
270{
271 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
272}
273
274static inline u32 read_wdtcr(void)
275{
276 u32 val;
277 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
278 return val;
279}
280static inline void write_wdtcr(u32 val)
281{
282 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
283}
284
285extern unsigned long get_iop_tick_rate(void);
286
287/* only iop13xx has these registers, we define these to present a
288 * common register interface for the iop_wdt driver.
289 */
290#define IOP_RCSR_WDT (0)
291static inline u32 read_rcsr(void)
292{
293 return 0;
294}
295static inline void write_wdtsr(u32 val)
296{
297 do { } while (0);
298}
299
300extern struct platform_device iop3xx_dma_0_channel;
301extern struct platform_device iop3xx_dma_1_channel;
302extern struct platform_device iop3xx_aau_channel;
303extern struct platform_device iop3xx_i2c0_device;
304extern struct platform_device iop3xx_i2c1_device;
305extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup;
306extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup;
307
308#endif
309
310
311#endif