tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017-2018 MediaTek Inc.
4 *
5 * Author: Sean Wang <sean.wang@mediatek.com>
6 *
7 */
8
9#include "pinctrl-moore.h"
10
11#define MT7622_PIN(_number, _name) \
12 MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
13
14static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
15 PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
16 PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
17 PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
18 PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
19 PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
20 PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
21 PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
22 PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
23 PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
24 PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
25 PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
26 PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
27 PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
28 PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
29 PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
30 PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
31 PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
32 PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
33 PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
34 PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
35 PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
36 PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
37 PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
38 PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
39 PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
40 PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
41};
42
43static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
44 PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
45};
46
47static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
48 PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
49};
50
51static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
52 PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
53};
54
55static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
56 PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
57 PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
58 PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
59 PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
60 PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
61 PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
62 PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
63};
64
65static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
66 PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
67 PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
68 PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
69 PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
70 PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
71 PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
72 PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
73};
74
75static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
76 PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
77 PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
78 PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
79 PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
80 PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
81 PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
82 PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
83};
84
85static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
86 PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
87 PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
88 PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
89 PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
90 PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
91 PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
92 PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
93};
94
95static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
96 PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
97 PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
98 PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
99 PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
100 PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
101 PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
102 PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
103};
104
105static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
106 PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
107 PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
108 PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
109 PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
110 PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
111 PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
112 PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
113};
114
115static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
116 PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
117 PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
118 PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
119 PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
120 PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
121 PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
122 PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
123};
124
125static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
126 PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
127 PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
128 PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
129 PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
130 PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
131 PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
132 PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
133 PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
134 PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
135 PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
136 PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
137 PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
138};
139
140static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
141 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
142 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
143 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
144 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
145 [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
146 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
147 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
148 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
149 [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
150 [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
151 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
152 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
153};
154
155static const struct mtk_pin_desc mt7622_pins[] = {
156 MT7622_PIN(0, "GPIO_A"),
157 MT7622_PIN(1, "I2S1_IN"),
158 MT7622_PIN(2, "I2S1_OUT"),
159 MT7622_PIN(3, "I2S_BCLK"),
160 MT7622_PIN(4, "I2S_WS"),
161 MT7622_PIN(5, "I2S_MCLK"),
162 MT7622_PIN(6, "TXD0"),
163 MT7622_PIN(7, "RXD0"),
164 MT7622_PIN(8, "SPI_WP"),
165 MT7622_PIN(9, "SPI_HOLD"),
166 MT7622_PIN(10, "SPI_CLK"),
167 MT7622_PIN(11, "SPI_MOSI"),
168 MT7622_PIN(12, "SPI_MISO"),
169 MT7622_PIN(13, "SPI_CS"),
170 MT7622_PIN(14, "I2C_SDA"),
171 MT7622_PIN(15, "I2C_SCL"),
172 MT7622_PIN(16, "I2S2_IN"),
173 MT7622_PIN(17, "I2S3_IN"),
174 MT7622_PIN(18, "I2S4_IN"),
175 MT7622_PIN(19, "I2S2_OUT"),
176 MT7622_PIN(20, "I2S3_OUT"),
177 MT7622_PIN(21, "I2S4_OUT"),
178 MT7622_PIN(22, "GPIO_B"),
179 MT7622_PIN(23, "MDC"),
180 MT7622_PIN(24, "MDIO"),
181 MT7622_PIN(25, "G2_TXD0"),
182 MT7622_PIN(26, "G2_TXD1"),
183 MT7622_PIN(27, "G2_TXD2"),
184 MT7622_PIN(28, "G2_TXD3"),
185 MT7622_PIN(29, "G2_TXEN"),
186 MT7622_PIN(30, "G2_TXC"),
187 MT7622_PIN(31, "G2_RXD0"),
188 MT7622_PIN(32, "G2_RXD1"),
189 MT7622_PIN(33, "G2_RXD2"),
190 MT7622_PIN(34, "G2_RXD3"),
191 MT7622_PIN(35, "G2_RXDV"),
192 MT7622_PIN(36, "G2_RXC"),
193 MT7622_PIN(37, "NCEB"),
194 MT7622_PIN(38, "NWEB"),
195 MT7622_PIN(39, "NREB"),
196 MT7622_PIN(40, "NDL4"),
197 MT7622_PIN(41, "NDL5"),
198 MT7622_PIN(42, "NDL6"),
199 MT7622_PIN(43, "NDL7"),
200 MT7622_PIN(44, "NRB"),
201 MT7622_PIN(45, "NCLE"),
202 MT7622_PIN(46, "NALE"),
203 MT7622_PIN(47, "NDL0"),
204 MT7622_PIN(48, "NDL1"),
205 MT7622_PIN(49, "NDL2"),
206 MT7622_PIN(50, "NDL3"),
207 MT7622_PIN(51, "MDI_TP_P0"),
208 MT7622_PIN(52, "MDI_TN_P0"),
209 MT7622_PIN(53, "MDI_RP_P0"),
210 MT7622_PIN(54, "MDI_RN_P0"),
211 MT7622_PIN(55, "MDI_TP_P1"),
212 MT7622_PIN(56, "MDI_TN_P1"),
213 MT7622_PIN(57, "MDI_RP_P1"),
214 MT7622_PIN(58, "MDI_RN_P1"),
215 MT7622_PIN(59, "MDI_RP_P2"),
216 MT7622_PIN(60, "MDI_RN_P2"),
217 MT7622_PIN(61, "MDI_TP_P2"),
218 MT7622_PIN(62, "MDI_TN_P2"),
219 MT7622_PIN(63, "MDI_TP_P3"),
220 MT7622_PIN(64, "MDI_TN_P3"),
221 MT7622_PIN(65, "MDI_RP_P3"),
222 MT7622_PIN(66, "MDI_RN_P3"),
223 MT7622_PIN(67, "MDI_RP_P4"),
224 MT7622_PIN(68, "MDI_RN_P4"),
225 MT7622_PIN(69, "MDI_TP_P4"),
226 MT7622_PIN(70, "MDI_TN_P4"),
227 MT7622_PIN(71, "PMIC_SCL"),
228 MT7622_PIN(72, "PMIC_SDA"),
229 MT7622_PIN(73, "SPIC1_CLK"),
230 MT7622_PIN(74, "SPIC1_MOSI"),
231 MT7622_PIN(75, "SPIC1_MISO"),
232 MT7622_PIN(76, "SPIC1_CS"),
233 MT7622_PIN(77, "GPIO_D"),
234 MT7622_PIN(78, "WATCHDOG"),
235 MT7622_PIN(79, "RTS3_N"),
236 MT7622_PIN(80, "CTS3_N"),
237 MT7622_PIN(81, "TXD3"),
238 MT7622_PIN(82, "RXD3"),
239 MT7622_PIN(83, "PERST0_N"),
240 MT7622_PIN(84, "PERST1_N"),
241 MT7622_PIN(85, "WLED_N"),
242 MT7622_PIN(86, "EPHY_LED0_N"),
243 MT7622_PIN(87, "AUXIN0"),
244 MT7622_PIN(88, "AUXIN1"),
245 MT7622_PIN(89, "AUXIN2"),
246 MT7622_PIN(90, "AUXIN3"),
247 MT7622_PIN(91, "TXD4"),
248 MT7622_PIN(92, "RXD4"),
249 MT7622_PIN(93, "RTS4_N"),
250 MT7622_PIN(94, "CTS4_N"),
251 MT7622_PIN(95, "PWM1"),
252 MT7622_PIN(96, "PWM2"),
253 MT7622_PIN(97, "PWM3"),
254 MT7622_PIN(98, "PWM4"),
255 MT7622_PIN(99, "PWM5"),
256 MT7622_PIN(100, "PWM6"),
257 MT7622_PIN(101, "PWM7"),
258 MT7622_PIN(102, "GPIO_E"),
259};
260
261/* List all groups consisting of these pins dedicated to the enablement of
262 * certain hardware block and the corresponding mode for all of the pins. The
263 * hardware probably has multiple combinations of these pinouts.
264 */
265
266/* EMMC */
267static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
268static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
269
270static int mt7622_emmc_rst_pins[] = { 37, };
271static int mt7622_emmc_rst_funcs[] = { 1, };
272
273/* LED for EPHY */
274static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
275static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
276static int mt7622_ephy0_led_pins[] = { 86, };
277static int mt7622_ephy0_led_funcs[] = { 0, };
278static int mt7622_ephy1_led_pins[] = { 91, };
279static int mt7622_ephy1_led_funcs[] = { 2, };
280static int mt7622_ephy2_led_pins[] = { 92, };
281static int mt7622_ephy2_led_funcs[] = { 2, };
282static int mt7622_ephy3_led_pins[] = { 93, };
283static int mt7622_ephy3_led_funcs[] = { 2, };
284static int mt7622_ephy4_led_pins[] = { 94, };
285static int mt7622_ephy4_led_funcs[] = { 2, };
286
287/* Embedded Switch */
288static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
289 62, 63, 64, 65, 66, 67, 68, 69, 70, };
290static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
291 0, 0, 0, 0, 0, 0, 0, 0, 0, };
292static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
293static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
294static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
295 68, 69, 70, };
296static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
297 0, 0, 0, };
298/* RGMII via ESW */
299static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
300 67, 68, 69, 70, };
301static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
302 0, };
303
304/* RGMII via GMAC1 */
305static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
306 67, 68, 69, 70, };
307static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
308 2, };
309
310/* RGMII via GMAC2 */
311static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
312 33, 34, 35, 36, };
313static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
314 0, };
315
316/* I2C */
317static int mt7622_i2c0_pins[] = { 14, 15, };
318static int mt7622_i2c0_funcs[] = { 0, 0, };
319static int mt7622_i2c1_0_pins[] = { 55, 56, };
320static int mt7622_i2c1_0_funcs[] = { 0, 0, };
321static int mt7622_i2c1_1_pins[] = { 73, 74, };
322static int mt7622_i2c1_1_funcs[] = { 3, 3, };
323static int mt7622_i2c1_2_pins[] = { 87, 88, };
324static int mt7622_i2c1_2_funcs[] = { 0, 0, };
325static int mt7622_i2c2_0_pins[] = { 57, 58, };
326static int mt7622_i2c2_0_funcs[] = { 0, 0, };
327static int mt7622_i2c2_1_pins[] = { 75, 76, };
328static int mt7622_i2c2_1_funcs[] = { 3, 3, };
329static int mt7622_i2c2_2_pins[] = { 89, 90, };
330static int mt7622_i2c2_2_funcs[] = { 0, 0, };
331
332/* I2S */
333static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
334static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
335static int mt7622_i2s1_in_data_pins[] = { 1, };
336static int mt7622_i2s1_in_data_funcs[] = { 0, };
337static int mt7622_i2s2_in_data_pins[] = { 16, };
338static int mt7622_i2s2_in_data_funcs[] = { 0, };
339static int mt7622_i2s3_in_data_pins[] = { 17, };
340static int mt7622_i2s3_in_data_funcs[] = { 0, };
341static int mt7622_i2s4_in_data_pins[] = { 18, };
342static int mt7622_i2s4_in_data_funcs[] = { 0, };
343static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
344static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
345static int mt7622_i2s1_out_data_pins[] = { 2, };
346static int mt7622_i2s1_out_data_funcs[] = { 0, };
347static int mt7622_i2s2_out_data_pins[] = { 19, };
348static int mt7622_i2s2_out_data_funcs[] = { 0, };
349static int mt7622_i2s3_out_data_pins[] = { 20, };
350static int mt7622_i2s3_out_data_funcs[] = { 0, };
351static int mt7622_i2s4_out_data_pins[] = { 21, };
352static int mt7622_i2s4_out_data_funcs[] = { 0, };
353
354/* IR */
355static int mt7622_ir_0_tx_pins[] = { 16, };
356static int mt7622_ir_0_tx_funcs[] = { 4, };
357static int mt7622_ir_1_tx_pins[] = { 59, };
358static int mt7622_ir_1_tx_funcs[] = { 5, };
359static int mt7622_ir_2_tx_pins[] = { 99, };
360static int mt7622_ir_2_tx_funcs[] = { 3, };
361static int mt7622_ir_0_rx_pins[] = { 17, };
362static int mt7622_ir_0_rx_funcs[] = { 4, };
363static int mt7622_ir_1_rx_pins[] = { 60, };
364static int mt7622_ir_1_rx_funcs[] = { 5, };
365static int mt7622_ir_2_rx_pins[] = { 100, };
366static int mt7622_ir_2_rx_funcs[] = { 3, };
367
368/* MDIO */
369static int mt7622_mdc_mdio_pins[] = { 23, 24, };
370static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
371
372/* PCIE */
373static int mt7622_pcie0_0_waken_pins[] = { 14, };
374static int mt7622_pcie0_0_waken_funcs[] = { 2, };
375static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
376static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
377static int mt7622_pcie0_1_waken_pins[] = { 79, };
378static int mt7622_pcie0_1_waken_funcs[] = { 4, };
379static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
380static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
381static int mt7622_pcie1_0_waken_pins[] = { 14, };
382static int mt7622_pcie1_0_waken_funcs[] = { 3, };
383static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
384static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
385
386static int mt7622_pcie0_pad_perst_pins[] = { 83, };
387static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
388static int mt7622_pcie1_pad_perst_pins[] = { 84, };
389static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
390
391/* PMIC bus */
392static int mt7622_pmic_bus_pins[] = { 71, 72, };
393static int mt7622_pmic_bus_funcs[] = { 0, 0, };
394
395/* Parallel NAND */
396static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
397 48, 49, 50, };
398static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
399 0, };
400
401/* PWM */
402static int mt7622_pwm_ch1_0_pins[] = { 51, };
403static int mt7622_pwm_ch1_0_funcs[] = { 3, };
404static int mt7622_pwm_ch1_1_pins[] = { 73, };
405static int mt7622_pwm_ch1_1_funcs[] = { 4, };
406static int mt7622_pwm_ch1_2_pins[] = { 95, };
407static int mt7622_pwm_ch1_2_funcs[] = { 0, };
408static int mt7622_pwm_ch2_0_pins[] = { 52, };
409static int mt7622_pwm_ch2_0_funcs[] = { 3, };
410static int mt7622_pwm_ch2_1_pins[] = { 74, };
411static int mt7622_pwm_ch2_1_funcs[] = { 4, };
412static int mt7622_pwm_ch2_2_pins[] = { 96, };
413static int mt7622_pwm_ch2_2_funcs[] = { 0, };
414static int mt7622_pwm_ch3_0_pins[] = { 53, };
415static int mt7622_pwm_ch3_0_funcs[] = { 3, };
416static int mt7622_pwm_ch3_1_pins[] = { 75, };
417static int mt7622_pwm_ch3_1_funcs[] = { 4, };
418static int mt7622_pwm_ch3_2_pins[] = { 97, };
419static int mt7622_pwm_ch3_2_funcs[] = { 0, };
420static int mt7622_pwm_ch4_0_pins[] = { 54, };
421static int mt7622_pwm_ch4_0_funcs[] = { 3, };
422static int mt7622_pwm_ch4_1_pins[] = { 67, };
423static int mt7622_pwm_ch4_1_funcs[] = { 3, };
424static int mt7622_pwm_ch4_2_pins[] = { 76, };
425static int mt7622_pwm_ch4_2_funcs[] = { 4, };
426static int mt7622_pwm_ch4_3_pins[] = { 98, };
427static int mt7622_pwm_ch4_3_funcs[] = { 0, };
428static int mt7622_pwm_ch5_0_pins[] = { 68, };
429static int mt7622_pwm_ch5_0_funcs[] = { 3, };
430static int mt7622_pwm_ch5_1_pins[] = { 77, };
431static int mt7622_pwm_ch5_1_funcs[] = { 4, };
432static int mt7622_pwm_ch5_2_pins[] = { 99, };
433static int mt7622_pwm_ch5_2_funcs[] = { 0, };
434static int mt7622_pwm_ch6_0_pins[] = { 69, };
435static int mt7622_pwm_ch6_0_funcs[] = { 3, };
436static int mt7622_pwm_ch6_1_pins[] = { 78, };
437static int mt7622_pwm_ch6_1_funcs[] = { 4, };
438static int mt7622_pwm_ch6_2_pins[] = { 81, };
439static int mt7622_pwm_ch6_2_funcs[] = { 4, };
440static int mt7622_pwm_ch6_3_pins[] = { 100, };
441static int mt7622_pwm_ch6_3_funcs[] = { 0, };
442static int mt7622_pwm_ch7_0_pins[] = { 70, };
443static int mt7622_pwm_ch7_0_funcs[] = { 3, };
444static int mt7622_pwm_ch7_1_pins[] = { 82, };
445static int mt7622_pwm_ch7_1_funcs[] = { 4, };
446static int mt7622_pwm_ch7_2_pins[] = { 101, };
447static int mt7622_pwm_ch7_2_funcs[] = { 0, };
448
449/* SD */
450static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
451static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
452static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
453static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
454
455/* Serial NAND */
456static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
457static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
458
459/* SPI NOR */
460static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
461static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
462
463/* SPIC */
464static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
465static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
466static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
467static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
468static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
469static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
470static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
471static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
472static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
473static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
474static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
475static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
476
477/* TDM */
478static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
479static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
480static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
481static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
482static int mt7622_tdm_0_out_data_pins[] = { 20, };
483static int mt7622_tdm_0_out_data_funcs[] = { 3, };
484static int mt7622_tdm_0_in_data_pins[] = { 21, };
485static int mt7622_tdm_0_in_data_funcs[] = { 3, };
486static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
487static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
488static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
489static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
490static int mt7622_tdm_1_out_data_pins[] = { 55, };
491static int mt7622_tdm_1_out_data_funcs[] = { 3, };
492static int mt7622_tdm_1_in_data_pins[] = { 56, };
493static int mt7622_tdm_1_in_data_funcs[] = { 3, };
494
495/* UART */
496static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
497static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
498static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
499static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
500static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
501static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
502static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
503static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
504static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
505static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
506static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
507static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
508static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
509static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
510static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
511static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
512static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
513static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
514static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
515static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
516static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
517static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
518static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
519static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
520static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
521static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
522static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
523static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
524static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
525static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
526static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
527static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
528static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
529static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
530static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
531static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
532static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
533static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
534static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
535static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
536
537/* Watchdog */
538static int mt7622_watchdog_pins[] = { 78, };
539static int mt7622_watchdog_funcs[] = { 0, };
540
541/* WLAN LED */
542static int mt7622_wled_pins[] = { 85, };
543static int mt7622_wled_funcs[] = { 0, };
544
545static const struct group_desc mt7622_groups[] = {
546 PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
547 PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
548 PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
549 PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
550 PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
551 PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
552 PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
553 PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
554 PINCTRL_PIN_GROUP("esw", mt7622_esw),
555 PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
556 PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
557 PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
558 PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
559 PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
560 PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
561 PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
562 PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
563 PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
564 PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
565 PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
566 PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
567 PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
568 PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
569 PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
570 PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
571 PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
572 PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
573 PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
574 PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
575 PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
576 PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
577 PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
578 PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
579 PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
580 PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
581 PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
582 PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
583 PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
584 PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
585 PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
586 PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
587 PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
588 PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
589 PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
590 PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
591 PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
592 PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
593 PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
594 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
595 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
596 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
597 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
598 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
599 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
600 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
601 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
602 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
603 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
604 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
605 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
606 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
607 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
608 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
609 PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
610 PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
611 PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
612 PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
613 PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
614 PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
615 PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
616 PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
617 PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
618 PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
619 PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
620 PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
621 PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
622 PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
623 PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
624 PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
625 PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
626 PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
627 PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
628 mt7622_tdm_0_out_mclk_bclk_ws),
629 PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
630 mt7622_tdm_0_in_mclk_bclk_ws),
631 PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
632 PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
633 PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
634 mt7622_tdm_1_out_mclk_bclk_ws),
635 PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
636 mt7622_tdm_1_in_mclk_bclk_ws),
637 PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
638 PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
639 PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
640 PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
641 PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
642 PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
643 PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
644 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
645 PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
646 PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
647 PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
648 PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
649 PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
650 PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
651 PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
652 PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
653 PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
654 PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
655 PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
656 PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
657 PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
658 PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
659 PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
660 PINCTRL_PIN_GROUP("wled", mt7622_wled),
661};
662
663/* Joint those groups owning the same capability in user point of view which
664 * allows that people tend to use through the device tree.
665 */
666static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
667static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
668 "esw_p2_p3_p4", "mdc_mdio",
669 "rgmii_via_gmac1",
670 "rgmii_via_gmac2",
671 "rgmii_via_esw", };
672static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
673 "i2c1_2", "i2c2_0", "i2c2_1",
674 "i2c2_2", };
675static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
676 "i2s_in_mclk_bclk_ws",
677 "i2s1_in_data", "i2s2_in_data",
678 "i2s3_in_data", "i2s4_in_data",
679 "i2s1_out_data", "i2s2_out_data",
680 "i2s3_out_data", "i2s4_out_data", };
681static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
682 "ir_0_rx", "ir_1_rx", "ir_2_rx"};
683static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
684 "ephy1_led", "ephy2_led",
685 "ephy3_led", "ephy4_led",
686 "wled", };
687static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
688static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
689 "pcie0_1_waken", "pcie0_1_clkreq",
690 "pcie1_0_waken", "pcie1_0_clkreq",
691 "pcie0_pad_perst",
692 "pcie1_pad_perst", };
693static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
694static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
695 "pwm_ch1_2", "pwm_ch2_0",
696 "pwm_ch2_1", "pwm_ch2_2",
697 "pwm_ch3_0", "pwm_ch3_1",
698 "pwm_ch3_2", "pwm_ch4_0",
699 "pwm_ch4_1", "pwm_ch4_2",
700 "pwm_ch4_3", "pwm_ch5_0",
701 "pwm_ch5_1", "pwm_ch5_2",
702 "pwm_ch6_0", "pwm_ch6_1",
703 "pwm_ch6_2", "pwm_ch6_3",
704 "pwm_ch7_0", "pwm_ch7_1",
705 "pwm_ch7_2", };
706static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
707static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
708 "spic1_1", "spic2_0",
709 "spic2_0_wp_hold", };
710static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
711 "tdm_0_in_mclk_bclk_ws",
712 "tdm_0_out_data",
713 "tdm_0_in_data",
714 "tdm_1_out_mclk_bclk_ws",
715 "tdm_1_in_mclk_bclk_ws",
716 "tdm_1_out_data",
717 "tdm_1_in_data", };
718
719static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
720 "uart1_0_tx_rx", "uart1_0_rts_cts",
721 "uart1_1_tx_rx", "uart1_1_rts_cts",
722 "uart2_0_tx_rx", "uart2_0_rts_cts",
723 "uart2_1_tx_rx", "uart2_1_rts_cts",
724 "uart2_2_tx_rx", "uart2_2_rts_cts",
725 "uart2_3_tx_rx",
726 "uart3_0_tx_rx",
727 "uart3_1_tx_rx", "uart3_1_rts_cts",
728 "uart4_0_tx_rx",
729 "uart4_1_tx_rx", "uart4_1_rts_cts",
730 "uart4_2_tx_rx",
731 "uart4_2_rts_cts",};
732static const char *mt7622_wdt_groups[] = { "watchdog", };
733
734static const struct function_desc mt7622_functions[] = {
735 {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
736 {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
737 {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
738 {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
739 {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
740 {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
741 {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
742 {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
743 {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
744 {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
745 {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
746 {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
747 {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
748 {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
749 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
750};
751
752static const struct mtk_eint_hw mt7622_eint_hw = {
753 .port_mask = 7,
754 .ports = 7,
755 .ap_num = ARRAY_SIZE(mt7622_pins),
756 .db_cnt = 20,
757};
758
759static const struct mtk_pin_soc mt7622_data = {
760 .reg_cal = mt7622_reg_cals,
761 .pins = mt7622_pins,
762 .npins = ARRAY_SIZE(mt7622_pins),
763 .grps = mt7622_groups,
764 .ngrps = ARRAY_SIZE(mt7622_groups),
765 .funcs = mt7622_functions,
766 .nfuncs = ARRAY_SIZE(mt7622_functions),
767 .eint_hw = &mt7622_eint_hw,
768 .gpio_m = 1,
769 .ies_present = false,
770 .base_names = mtk_default_register_base_names,
771 .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
772 .bias_disable_set = mtk_pinconf_bias_disable_set,
773 .bias_disable_get = mtk_pinconf_bias_disable_get,
774 .bias_set = mtk_pinconf_bias_set,
775 .bias_get = mtk_pinconf_bias_get,
776 .drive_set = mtk_pinconf_drive_set,
777 .drive_get = mtk_pinconf_drive_get,
778};
779
780static const struct of_device_id mt7622_pinctrl_of_match[] = {
781 { .compatible = "mediatek,mt7622-pinctrl", },
782 { }
783};
784
785static int mt7622_pinctrl_probe(struct platform_device *pdev)
786{
787 return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
788}
789
790static struct platform_driver mt7622_pinctrl_driver = {
791 .driver = {
792 .name = "mt7622-pinctrl",
793 .of_match_table = mt7622_pinctrl_of_match,
794 },
795 .probe = mt7622_pinctrl_probe,
796};
797
798static int __init mt7622_pinctrl_init(void)
799{
800 return platform_driver_register(&mt7622_pinctrl_driver);
801}
802arch_initcall(mt7622_pinctrl_init);