tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25#include <linux/slab.h>
26
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
34#include "amd_pcie.h"
35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
62#include "gmc_v8_0.h"
63#include "gmc_v7_0.h"
64#include "gfx_v8_0.h"
65#include "sdma_v2_4.h"
66#include "sdma_v3_0.h"
67#include "dce_v10_0.h"
68#include "dce_v11_0.h"
69#include "iceland_ih.h"
70#include "tonga_ih.h"
71#include "cz_ih.h"
72#include "uvd_v5_0.h"
73#include "uvd_v6_0.h"
74#include "vce_v3_0.h"
75#if defined(CONFIG_DRM_AMD_ACP)
76#include "amdgpu_acp.h"
77#endif
78#include "dce_virtual.h"
79#include "mxgpu_vi.h"
80#include "amdgpu_dm.h"
81
82/*
83 * Indirect registers accessor
84 */
85static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
86{
87 unsigned long flags;
88 u32 r;
89
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
91 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
92 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
93 r = RREG32_NO_KIQ(mmPCIE_DATA);
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
95 return r;
96}
97
98static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
99{
100 unsigned long flags;
101
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
103 WREG32_NO_KIQ(mmPCIE_INDEX, reg);
104 (void)RREG32_NO_KIQ(mmPCIE_INDEX);
105 WREG32_NO_KIQ(mmPCIE_DATA, v);
106 (void)RREG32_NO_KIQ(mmPCIE_DATA);
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
108}
109
110static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 unsigned long flags;
113 u32 r;
114
115 spin_lock_irqsave(&adev->smc_idx_lock, flags);
116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
119 return r;
120}
121
122static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&adev->smc_idx_lock, flags);
127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v));
129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
130}
131
132/* smu_8_0_d.h */
133#define mmMP0PUB_IND_INDEX 0x180
134#define mmMP0PUB_IND_DATA 0x181
135
136static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
137{
138 unsigned long flags;
139 u32 r;
140
141 spin_lock_irqsave(&adev->smc_idx_lock, flags);
142 WREG32(mmMP0PUB_IND_INDEX, (reg));
143 r = RREG32(mmMP0PUB_IND_DATA);
144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
145 return r;
146}
147
148static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&adev->smc_idx_lock, flags);
153 WREG32(mmMP0PUB_IND_INDEX, (reg));
154 WREG32(mmMP0PUB_IND_DATA, (v));
155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
156}
157
158static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
159{
160 unsigned long flags;
161 u32 r;
162
163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
164 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
165 r = RREG32(mmUVD_CTX_DATA);
166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
167 return r;
168}
169
170static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
171{
172 unsigned long flags;
173
174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
175 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
176 WREG32(mmUVD_CTX_DATA, (v));
177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
178}
179
180static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
181{
182 unsigned long flags;
183 u32 r;
184
185 spin_lock_irqsave(&adev->didt_idx_lock, flags);
186 WREG32(mmDIDT_IND_INDEX, (reg));
187 r = RREG32(mmDIDT_IND_DATA);
188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
189 return r;
190}
191
192static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
193{
194 unsigned long flags;
195
196 spin_lock_irqsave(&adev->didt_idx_lock, flags);
197 WREG32(mmDIDT_IND_INDEX, (reg));
198 WREG32(mmDIDT_IND_DATA, (v));
199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
200}
201
202static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
203{
204 unsigned long flags;
205 u32 r;
206
207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
208 WREG32(mmGC_CAC_IND_INDEX, (reg));
209 r = RREG32(mmGC_CAC_IND_DATA);
210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
211 return r;
212}
213
214static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
215{
216 unsigned long flags;
217
218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
219 WREG32(mmGC_CAC_IND_INDEX, (reg));
220 WREG32(mmGC_CAC_IND_DATA, (v));
221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
222}
223
224
225static const u32 tonga_mgcg_cgcg_init[] =
226{
227 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
228 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
229 mmPCIE_DATA, 0x000f0000, 0x00000000,
230 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
231 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
234};
235
236static const u32 fiji_mgcg_cgcg_init[] =
237{
238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
239 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
240 mmPCIE_DATA, 0x000f0000, 0x00000000,
241 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
242 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
243 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
244 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
245};
246
247static const u32 iceland_mgcg_cgcg_init[] =
248{
249 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
250 mmPCIE_DATA, 0x000f0000, 0x00000000,
251 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
252 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
253 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
254};
255
256static const u32 cz_mgcg_cgcg_init[] =
257{
258 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
259 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
260 mmPCIE_DATA, 0x000f0000, 0x00000000,
261 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
262 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
263};
264
265static const u32 stoney_mgcg_cgcg_init[] =
266{
267 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
268 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
269 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
270};
271
272static void vi_init_golden_registers(struct amdgpu_device *adev)
273{
274 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
275 mutex_lock(&adev->grbm_idx_mutex);
276
277 if (amdgpu_sriov_vf(adev)) {
278 xgpu_vi_init_golden_registers(adev);
279 mutex_unlock(&adev->grbm_idx_mutex);
280 return;
281 }
282
283 switch (adev->asic_type) {
284 case CHIP_TOPAZ:
285 amdgpu_device_program_register_sequence(adev,
286 iceland_mgcg_cgcg_init,
287 ARRAY_SIZE(iceland_mgcg_cgcg_init));
288 break;
289 case CHIP_FIJI:
290 amdgpu_device_program_register_sequence(adev,
291 fiji_mgcg_cgcg_init,
292 ARRAY_SIZE(fiji_mgcg_cgcg_init));
293 break;
294 case CHIP_TONGA:
295 amdgpu_device_program_register_sequence(adev,
296 tonga_mgcg_cgcg_init,
297 ARRAY_SIZE(tonga_mgcg_cgcg_init));
298 break;
299 case CHIP_CARRIZO:
300 amdgpu_device_program_register_sequence(adev,
301 cz_mgcg_cgcg_init,
302 ARRAY_SIZE(cz_mgcg_cgcg_init));
303 break;
304 case CHIP_STONEY:
305 amdgpu_device_program_register_sequence(adev,
306 stoney_mgcg_cgcg_init,
307 ARRAY_SIZE(stoney_mgcg_cgcg_init));
308 break;
309 case CHIP_POLARIS10:
310 case CHIP_POLARIS11:
311 case CHIP_POLARIS12:
312 case CHIP_VEGAM:
313 default:
314 break;
315 }
316 mutex_unlock(&adev->grbm_idx_mutex);
317}
318
319/**
320 * vi_get_xclk - get the xclk
321 *
322 * @adev: amdgpu_device pointer
323 *
324 * Returns the reference clock used by the gfx engine
325 * (VI).
326 */
327static u32 vi_get_xclk(struct amdgpu_device *adev)
328{
329 u32 reference_clock = adev->clock.spll.reference_freq;
330 u32 tmp;
331
332 if (adev->flags & AMD_IS_APU)
333 return reference_clock;
334
335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
337 return 1000;
338
339 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
341 return reference_clock / 4;
342
343 return reference_clock;
344}
345
346/**
347 * vi_srbm_select - select specific register instances
348 *
349 * @adev: amdgpu_device pointer
350 * @me: selected ME (micro engine)
351 * @pipe: pipe
352 * @queue: queue
353 * @vmid: VMID
354 *
355 * Switches the currently active registers instances. Some
356 * registers are instanced per VMID, others are instanced per
357 * me/pipe/queue combination.
358 */
359void vi_srbm_select(struct amdgpu_device *adev,
360 u32 me, u32 pipe, u32 queue, u32 vmid)
361{
362 u32 srbm_gfx_cntl = 0;
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
366 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
367 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
368}
369
370static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
371{
372 /* todo */
373}
374
375static bool vi_read_disabled_bios(struct amdgpu_device *adev)
376{
377 u32 bus_cntl;
378 u32 d1vga_control = 0;
379 u32 d2vga_control = 0;
380 u32 vga_render_control = 0;
381 u32 rom_cntl;
382 bool r;
383
384 bus_cntl = RREG32(mmBUS_CNTL);
385 if (adev->mode_info.num_crtc) {
386 d1vga_control = RREG32(mmD1VGA_CONTROL);
387 d2vga_control = RREG32(mmD2VGA_CONTROL);
388 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
389 }
390 rom_cntl = RREG32_SMC(ixROM_CNTL);
391
392 /* enable the rom */
393 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
394 if (adev->mode_info.num_crtc) {
395 /* Disable VGA mode */
396 WREG32(mmD1VGA_CONTROL,
397 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
398 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
399 WREG32(mmD2VGA_CONTROL,
400 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
401 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
402 WREG32(mmVGA_RENDER_CONTROL,
403 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
404 }
405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
406
407 r = amdgpu_read_bios(adev);
408
409 /* restore regs */
410 WREG32(mmBUS_CNTL, bus_cntl);
411 if (adev->mode_info.num_crtc) {
412 WREG32(mmD1VGA_CONTROL, d1vga_control);
413 WREG32(mmD2VGA_CONTROL, d2vga_control);
414 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
415 }
416 WREG32_SMC(ixROM_CNTL, rom_cntl);
417 return r;
418}
419
420static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
421 u8 *bios, u32 length_bytes)
422{
423 u32 *dw_ptr;
424 unsigned long flags;
425 u32 i, length_dw;
426
427 if (bios == NULL)
428 return false;
429 if (length_bytes == 0)
430 return false;
431 /* APU vbios image is part of sbios image */
432 if (adev->flags & AMD_IS_APU)
433 return false;
434
435 dw_ptr = (u32 *)bios;
436 length_dw = ALIGN(length_bytes, 4) / 4;
437 /* take the smc lock since we are using the smc index */
438 spin_lock_irqsave(&adev->smc_idx_lock, flags);
439 /* set rom index to 0 */
440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
441 WREG32(mmSMC_IND_DATA_11, 0);
442 /* set index to data for continous read */
443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
444 for (i = 0; i < length_dw; i++)
445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447
448 return true;
449}
450
451static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
452{
453 uint32_t reg = 0;
454
455 if (adev->asic_type == CHIP_TONGA ||
456 adev->asic_type == CHIP_FIJI) {
457 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
458 /* bit0: 0 means pf and 1 means vf */
459 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
460 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
461 /* bit31: 0 means disable IOV and 1 means enable */
462 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
463 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
464 }
465
466 if (reg == 0) {
467 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
468 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
469 }
470}
471
472static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
473 {mmGRBM_STATUS},
474 {mmGRBM_STATUS2},
475 {mmGRBM_STATUS_SE0},
476 {mmGRBM_STATUS_SE1},
477 {mmGRBM_STATUS_SE2},
478 {mmGRBM_STATUS_SE3},
479 {mmSRBM_STATUS},
480 {mmSRBM_STATUS2},
481 {mmSRBM_STATUS3},
482 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
483 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
484 {mmCP_STAT},
485 {mmCP_STALLED_STAT1},
486 {mmCP_STALLED_STAT2},
487 {mmCP_STALLED_STAT3},
488 {mmCP_CPF_BUSY_STAT},
489 {mmCP_CPF_STALLED_STAT1},
490 {mmCP_CPF_STATUS},
491 {mmCP_CPC_BUSY_STAT},
492 {mmCP_CPC_STALLED_STAT1},
493 {mmCP_CPC_STATUS},
494 {mmGB_ADDR_CONFIG},
495 {mmMC_ARB_RAMCFG},
496 {mmGB_TILE_MODE0},
497 {mmGB_TILE_MODE1},
498 {mmGB_TILE_MODE2},
499 {mmGB_TILE_MODE3},
500 {mmGB_TILE_MODE4},
501 {mmGB_TILE_MODE5},
502 {mmGB_TILE_MODE6},
503 {mmGB_TILE_MODE7},
504 {mmGB_TILE_MODE8},
505 {mmGB_TILE_MODE9},
506 {mmGB_TILE_MODE10},
507 {mmGB_TILE_MODE11},
508 {mmGB_TILE_MODE12},
509 {mmGB_TILE_MODE13},
510 {mmGB_TILE_MODE14},
511 {mmGB_TILE_MODE15},
512 {mmGB_TILE_MODE16},
513 {mmGB_TILE_MODE17},
514 {mmGB_TILE_MODE18},
515 {mmGB_TILE_MODE19},
516 {mmGB_TILE_MODE20},
517 {mmGB_TILE_MODE21},
518 {mmGB_TILE_MODE22},
519 {mmGB_TILE_MODE23},
520 {mmGB_TILE_MODE24},
521 {mmGB_TILE_MODE25},
522 {mmGB_TILE_MODE26},
523 {mmGB_TILE_MODE27},
524 {mmGB_TILE_MODE28},
525 {mmGB_TILE_MODE29},
526 {mmGB_TILE_MODE30},
527 {mmGB_TILE_MODE31},
528 {mmGB_MACROTILE_MODE0},
529 {mmGB_MACROTILE_MODE1},
530 {mmGB_MACROTILE_MODE2},
531 {mmGB_MACROTILE_MODE3},
532 {mmGB_MACROTILE_MODE4},
533 {mmGB_MACROTILE_MODE5},
534 {mmGB_MACROTILE_MODE6},
535 {mmGB_MACROTILE_MODE7},
536 {mmGB_MACROTILE_MODE8},
537 {mmGB_MACROTILE_MODE9},
538 {mmGB_MACROTILE_MODE10},
539 {mmGB_MACROTILE_MODE11},
540 {mmGB_MACROTILE_MODE12},
541 {mmGB_MACROTILE_MODE13},
542 {mmGB_MACROTILE_MODE14},
543 {mmGB_MACROTILE_MODE15},
544 {mmCC_RB_BACKEND_DISABLE, true},
545 {mmGC_USER_RB_BACKEND_DISABLE, true},
546 {mmGB_BACKEND_MAP, false},
547 {mmPA_SC_RASTER_CONFIG, true},
548 {mmPA_SC_RASTER_CONFIG_1, true},
549};
550
551static uint32_t vi_get_register_value(struct amdgpu_device *adev,
552 bool indexed, u32 se_num,
553 u32 sh_num, u32 reg_offset)
554{
555 if (indexed) {
556 uint32_t val;
557 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
558 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
559
560 switch (reg_offset) {
561 case mmCC_RB_BACKEND_DISABLE:
562 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
563 case mmGC_USER_RB_BACKEND_DISABLE:
564 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
565 case mmPA_SC_RASTER_CONFIG:
566 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
567 case mmPA_SC_RASTER_CONFIG_1:
568 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
569 }
570
571 mutex_lock(&adev->grbm_idx_mutex);
572 if (se_num != 0xffffffff || sh_num != 0xffffffff)
573 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
574
575 val = RREG32(reg_offset);
576
577 if (se_num != 0xffffffff || sh_num != 0xffffffff)
578 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
579 mutex_unlock(&adev->grbm_idx_mutex);
580 return val;
581 } else {
582 unsigned idx;
583
584 switch (reg_offset) {
585 case mmGB_ADDR_CONFIG:
586 return adev->gfx.config.gb_addr_config;
587 case mmMC_ARB_RAMCFG:
588 return adev->gfx.config.mc_arb_ramcfg;
589 case mmGB_TILE_MODE0:
590 case mmGB_TILE_MODE1:
591 case mmGB_TILE_MODE2:
592 case mmGB_TILE_MODE3:
593 case mmGB_TILE_MODE4:
594 case mmGB_TILE_MODE5:
595 case mmGB_TILE_MODE6:
596 case mmGB_TILE_MODE7:
597 case mmGB_TILE_MODE8:
598 case mmGB_TILE_MODE9:
599 case mmGB_TILE_MODE10:
600 case mmGB_TILE_MODE11:
601 case mmGB_TILE_MODE12:
602 case mmGB_TILE_MODE13:
603 case mmGB_TILE_MODE14:
604 case mmGB_TILE_MODE15:
605 case mmGB_TILE_MODE16:
606 case mmGB_TILE_MODE17:
607 case mmGB_TILE_MODE18:
608 case mmGB_TILE_MODE19:
609 case mmGB_TILE_MODE20:
610 case mmGB_TILE_MODE21:
611 case mmGB_TILE_MODE22:
612 case mmGB_TILE_MODE23:
613 case mmGB_TILE_MODE24:
614 case mmGB_TILE_MODE25:
615 case mmGB_TILE_MODE26:
616 case mmGB_TILE_MODE27:
617 case mmGB_TILE_MODE28:
618 case mmGB_TILE_MODE29:
619 case mmGB_TILE_MODE30:
620 case mmGB_TILE_MODE31:
621 idx = (reg_offset - mmGB_TILE_MODE0);
622 return adev->gfx.config.tile_mode_array[idx];
623 case mmGB_MACROTILE_MODE0:
624 case mmGB_MACROTILE_MODE1:
625 case mmGB_MACROTILE_MODE2:
626 case mmGB_MACROTILE_MODE3:
627 case mmGB_MACROTILE_MODE4:
628 case mmGB_MACROTILE_MODE5:
629 case mmGB_MACROTILE_MODE6:
630 case mmGB_MACROTILE_MODE7:
631 case mmGB_MACROTILE_MODE8:
632 case mmGB_MACROTILE_MODE9:
633 case mmGB_MACROTILE_MODE10:
634 case mmGB_MACROTILE_MODE11:
635 case mmGB_MACROTILE_MODE12:
636 case mmGB_MACROTILE_MODE13:
637 case mmGB_MACROTILE_MODE14:
638 case mmGB_MACROTILE_MODE15:
639 idx = (reg_offset - mmGB_MACROTILE_MODE0);
640 return adev->gfx.config.macrotile_mode_array[idx];
641 default:
642 return RREG32(reg_offset);
643 }
644 }
645}
646
647static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
648 u32 sh_num, u32 reg_offset, u32 *value)
649{
650 uint32_t i;
651
652 *value = 0;
653 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
654 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
655
656 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
657 continue;
658
659 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
660 reg_offset);
661 return 0;
662 }
663 return -EINVAL;
664}
665
666static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
667{
668 u32 i;
669
670 dev_info(adev->dev, "GPU pci config reset\n");
671
672 /* disable BM */
673 pci_clear_master(adev->pdev);
674 /* reset */
675 amdgpu_device_pci_config_reset(adev);
676
677 udelay(100);
678
679 /* wait for asic to come out of reset */
680 for (i = 0; i < adev->usec_timeout; i++) {
681 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
682 /* enable BM */
683 pci_set_master(adev->pdev);
684 adev->has_hw_reset = true;
685 return 0;
686 }
687 udelay(1);
688 }
689 return -EINVAL;
690}
691
692/**
693 * vi_asic_reset - soft reset GPU
694 *
695 * @adev: amdgpu_device pointer
696 *
697 * Look up which blocks are hung and attempt
698 * to reset them.
699 * Returns 0 for success.
700 */
701static int vi_asic_reset(struct amdgpu_device *adev)
702{
703 int r;
704
705 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
706
707 r = vi_gpu_pci_config_reset(adev);
708
709 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
710
711 return r;
712}
713
714static u32 vi_get_config_memsize(struct amdgpu_device *adev)
715{
716 return RREG32(mmCONFIG_MEMSIZE);
717}
718
719static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
720 u32 cntl_reg, u32 status_reg)
721{
722 int r, i;
723 struct atom_clock_dividers dividers;
724 uint32_t tmp;
725
726 r = amdgpu_atombios_get_clock_dividers(adev,
727 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
728 clock, false, ÷rs);
729 if (r)
730 return r;
731
732 tmp = RREG32_SMC(cntl_reg);
733
734 if (adev->flags & AMD_IS_APU)
735 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
736 else
737 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
738 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
739 tmp |= dividers.post_divider;
740 WREG32_SMC(cntl_reg, tmp);
741
742 for (i = 0; i < 100; i++) {
743 tmp = RREG32_SMC(status_reg);
744 if (adev->flags & AMD_IS_APU) {
745 if (tmp & 0x10000)
746 break;
747 } else {
748 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
749 break;
750 }
751 mdelay(10);
752 }
753 if (i == 100)
754 return -ETIMEDOUT;
755 return 0;
756}
757
758#define ixGNB_CLK1_DFS_CNTL 0xD82200F0
759#define ixGNB_CLK1_STATUS 0xD822010C
760#define ixGNB_CLK2_DFS_CNTL 0xD8220110
761#define ixGNB_CLK2_STATUS 0xD822012C
762#define ixGNB_CLK3_DFS_CNTL 0xD8220130
763#define ixGNB_CLK3_STATUS 0xD822014C
764
765static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
766{
767 int r;
768
769 if (adev->flags & AMD_IS_APU) {
770 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
771 if (r)
772 return r;
773
774 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
775 if (r)
776 return r;
777 } else {
778 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
779 if (r)
780 return r;
781
782 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
783 if (r)
784 return r;
785 }
786
787 return 0;
788}
789
790static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
791{
792 int r, i;
793 struct atom_clock_dividers dividers;
794 u32 tmp;
795 u32 reg_ctrl;
796 u32 reg_status;
797 u32 status_mask;
798 u32 reg_mask;
799
800 if (adev->flags & AMD_IS_APU) {
801 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
802 reg_status = ixGNB_CLK3_STATUS;
803 status_mask = 0x00010000;
804 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
805 } else {
806 reg_ctrl = ixCG_ECLK_CNTL;
807 reg_status = ixCG_ECLK_STATUS;
808 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
809 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
810 }
811
812 r = amdgpu_atombios_get_clock_dividers(adev,
813 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
814 ecclk, false, ÷rs);
815 if (r)
816 return r;
817
818 for (i = 0; i < 100; i++) {
819 if (RREG32_SMC(reg_status) & status_mask)
820 break;
821 mdelay(10);
822 }
823
824 if (i == 100)
825 return -ETIMEDOUT;
826
827 tmp = RREG32_SMC(reg_ctrl);
828 tmp &= ~reg_mask;
829 tmp |= dividers.post_divider;
830 WREG32_SMC(reg_ctrl, tmp);
831
832 for (i = 0; i < 100; i++) {
833 if (RREG32_SMC(reg_status) & status_mask)
834 break;
835 mdelay(10);
836 }
837
838 if (i == 100)
839 return -ETIMEDOUT;
840
841 return 0;
842}
843
844static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
845{
846 if (pci_is_root_bus(adev->pdev->bus))
847 return;
848
849 if (amdgpu_pcie_gen2 == 0)
850 return;
851
852 if (adev->flags & AMD_IS_APU)
853 return;
854
855 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
856 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
857 return;
858
859 /* todo */
860}
861
862static void vi_program_aspm(struct amdgpu_device *adev)
863{
864
865 if (amdgpu_aspm == 0)
866 return;
867
868 /* todo */
869}
870
871static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
872 bool enable)
873{
874 u32 tmp;
875
876 /* not necessary on CZ */
877 if (adev->flags & AMD_IS_APU)
878 return;
879
880 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
881 if (enable)
882 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
883 else
884 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
885
886 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
887}
888
889#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
890#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
891#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
892
893static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
894{
895 if (adev->flags & AMD_IS_APU)
896 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
897 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
898 else
899 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
900 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
901}
902
903static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
904{
905 if (!ring || !ring->funcs->emit_wreg) {
906 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
907 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
908 } else {
909 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
910 }
911}
912
913static void vi_invalidate_hdp(struct amdgpu_device *adev,
914 struct amdgpu_ring *ring)
915{
916 if (!ring || !ring->funcs->emit_wreg) {
917 WREG32(mmHDP_DEBUG0, 1);
918 RREG32(mmHDP_DEBUG0);
919 } else {
920 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
921 }
922}
923
924static bool vi_need_full_reset(struct amdgpu_device *adev)
925{
926 switch (adev->asic_type) {
927 case CHIP_CARRIZO:
928 case CHIP_STONEY:
929 /* CZ has hang issues with full reset at the moment */
930 return false;
931 case CHIP_FIJI:
932 case CHIP_TONGA:
933 /* XXX: soft reset should work on fiji and tonga */
934 return true;
935 case CHIP_POLARIS10:
936 case CHIP_POLARIS11:
937 case CHIP_POLARIS12:
938 case CHIP_TOPAZ:
939 default:
940 /* change this when we support soft reset */
941 return true;
942 }
943}
944
945static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
946 uint64_t *count1)
947{
948 uint32_t perfctr = 0;
949 uint64_t cnt0_of, cnt1_of;
950 int tmp;
951
952 /* This reports 0 on APUs, so return to avoid writing/reading registers
953 * that may or may not be different from their GPU counterparts
954 */
955 if (adev->flags & AMD_IS_APU)
956 return;
957
958 /* Set the 2 events that we wish to watch, defined above */
959 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
960 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
961 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
962
963 /* Write to enable desired perf counters */
964 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
965 /* Zero out and enable the perf counters
966 * Write 0x5:
967 * Bit 0 = Start all counters(1)
968 * Bit 2 = Global counter reset enable(1)
969 */
970 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
971
972 msleep(1000);
973
974 /* Load the shadow and disable the perf counters
975 * Write 0x2:
976 * Bit 0 = Stop counters(0)
977 * Bit 1 = Load the shadow counters(1)
978 */
979 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
980
981 /* Read register values to get any >32bit overflow */
982 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
983 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
984 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
985
986 /* Get the values and add the overflow */
987 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
988 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
989}
990
991static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
992{
993 uint64_t nak_r, nak_g;
994
995 /* Get the number of NAKs received and generated */
996 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
997 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
998
999 /* Add the total number of NAKs, i.e the number of replays */
1000 return (nak_r + nak_g);
1001}
1002
1003static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1004{
1005 u32 clock_cntl, pc;
1006
1007 if (adev->flags & AMD_IS_APU)
1008 return false;
1009
1010 /* check if the SMC is already running */
1011 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
1012 pc = RREG32_SMC(ixSMC_PC_C);
1013 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
1014 (0x20100 <= pc))
1015 return true;
1016
1017 return false;
1018}
1019
1020static const struct amdgpu_asic_funcs vi_asic_funcs =
1021{
1022 .read_disabled_bios = &vi_read_disabled_bios,
1023 .read_bios_from_rom = &vi_read_bios_from_rom,
1024 .read_register = &vi_read_register,
1025 .reset = &vi_asic_reset,
1026 .set_vga_state = &vi_vga_set_state,
1027 .get_xclk = &vi_get_xclk,
1028 .set_uvd_clocks = &vi_set_uvd_clocks,
1029 .set_vce_clocks = &vi_set_vce_clocks,
1030 .get_config_memsize = &vi_get_config_memsize,
1031 .flush_hdp = &vi_flush_hdp,
1032 .invalidate_hdp = &vi_invalidate_hdp,
1033 .need_full_reset = &vi_need_full_reset,
1034 .init_doorbell_index = &legacy_doorbell_index_init,
1035 .get_pcie_usage = &vi_get_pcie_usage,
1036 .need_reset_on_init = &vi_need_reset_on_init,
1037 .get_pcie_replay_count = &vi_get_pcie_replay_count,
1038};
1039
1040#define CZ_REV_BRISTOL(rev) \
1041 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
1042
1043static int vi_common_early_init(void *handle)
1044{
1045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1046
1047 if (adev->flags & AMD_IS_APU) {
1048 adev->smc_rreg = &cz_smc_rreg;
1049 adev->smc_wreg = &cz_smc_wreg;
1050 } else {
1051 adev->smc_rreg = &vi_smc_rreg;
1052 adev->smc_wreg = &vi_smc_wreg;
1053 }
1054 adev->pcie_rreg = &vi_pcie_rreg;
1055 adev->pcie_wreg = &vi_pcie_wreg;
1056 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1057 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1058 adev->didt_rreg = &vi_didt_rreg;
1059 adev->didt_wreg = &vi_didt_wreg;
1060 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1061 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1062
1063 adev->asic_funcs = &vi_asic_funcs;
1064
1065 adev->rev_id = vi_get_rev_id(adev);
1066 adev->external_rev_id = 0xFF;
1067 switch (adev->asic_type) {
1068 case CHIP_TOPAZ:
1069 adev->cg_flags = 0;
1070 adev->pg_flags = 0;
1071 adev->external_rev_id = 0x1;
1072 break;
1073 case CHIP_FIJI:
1074 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1075 AMD_CG_SUPPORT_GFX_MGLS |
1076 AMD_CG_SUPPORT_GFX_RLC_LS |
1077 AMD_CG_SUPPORT_GFX_CP_LS |
1078 AMD_CG_SUPPORT_GFX_CGTS |
1079 AMD_CG_SUPPORT_GFX_CGTS_LS |
1080 AMD_CG_SUPPORT_GFX_CGCG |
1081 AMD_CG_SUPPORT_GFX_CGLS |
1082 AMD_CG_SUPPORT_SDMA_MGCG |
1083 AMD_CG_SUPPORT_SDMA_LS |
1084 AMD_CG_SUPPORT_BIF_LS |
1085 AMD_CG_SUPPORT_HDP_MGCG |
1086 AMD_CG_SUPPORT_HDP_LS |
1087 AMD_CG_SUPPORT_ROM_MGCG |
1088 AMD_CG_SUPPORT_MC_MGCG |
1089 AMD_CG_SUPPORT_MC_LS |
1090 AMD_CG_SUPPORT_UVD_MGCG;
1091 adev->pg_flags = 0;
1092 adev->external_rev_id = adev->rev_id + 0x3c;
1093 break;
1094 case CHIP_TONGA:
1095 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1096 AMD_CG_SUPPORT_GFX_CGCG |
1097 AMD_CG_SUPPORT_GFX_CGLS |
1098 AMD_CG_SUPPORT_SDMA_MGCG |
1099 AMD_CG_SUPPORT_SDMA_LS |
1100 AMD_CG_SUPPORT_BIF_LS |
1101 AMD_CG_SUPPORT_HDP_MGCG |
1102 AMD_CG_SUPPORT_HDP_LS |
1103 AMD_CG_SUPPORT_ROM_MGCG |
1104 AMD_CG_SUPPORT_MC_MGCG |
1105 AMD_CG_SUPPORT_MC_LS |
1106 AMD_CG_SUPPORT_DRM_LS |
1107 AMD_CG_SUPPORT_UVD_MGCG;
1108 adev->pg_flags = 0;
1109 adev->external_rev_id = adev->rev_id + 0x14;
1110 break;
1111 case CHIP_POLARIS11:
1112 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1113 AMD_CG_SUPPORT_GFX_RLC_LS |
1114 AMD_CG_SUPPORT_GFX_CP_LS |
1115 AMD_CG_SUPPORT_GFX_CGCG |
1116 AMD_CG_SUPPORT_GFX_CGLS |
1117 AMD_CG_SUPPORT_GFX_3D_CGCG |
1118 AMD_CG_SUPPORT_GFX_3D_CGLS |
1119 AMD_CG_SUPPORT_SDMA_MGCG |
1120 AMD_CG_SUPPORT_SDMA_LS |
1121 AMD_CG_SUPPORT_BIF_MGCG |
1122 AMD_CG_SUPPORT_BIF_LS |
1123 AMD_CG_SUPPORT_HDP_MGCG |
1124 AMD_CG_SUPPORT_HDP_LS |
1125 AMD_CG_SUPPORT_ROM_MGCG |
1126 AMD_CG_SUPPORT_MC_MGCG |
1127 AMD_CG_SUPPORT_MC_LS |
1128 AMD_CG_SUPPORT_DRM_LS |
1129 AMD_CG_SUPPORT_UVD_MGCG |
1130 AMD_CG_SUPPORT_VCE_MGCG;
1131 adev->pg_flags = 0;
1132 adev->external_rev_id = adev->rev_id + 0x5A;
1133 break;
1134 case CHIP_POLARIS10:
1135 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1136 AMD_CG_SUPPORT_GFX_RLC_LS |
1137 AMD_CG_SUPPORT_GFX_CP_LS |
1138 AMD_CG_SUPPORT_GFX_CGCG |
1139 AMD_CG_SUPPORT_GFX_CGLS |
1140 AMD_CG_SUPPORT_GFX_3D_CGCG |
1141 AMD_CG_SUPPORT_GFX_3D_CGLS |
1142 AMD_CG_SUPPORT_SDMA_MGCG |
1143 AMD_CG_SUPPORT_SDMA_LS |
1144 AMD_CG_SUPPORT_BIF_MGCG |
1145 AMD_CG_SUPPORT_BIF_LS |
1146 AMD_CG_SUPPORT_HDP_MGCG |
1147 AMD_CG_SUPPORT_HDP_LS |
1148 AMD_CG_SUPPORT_ROM_MGCG |
1149 AMD_CG_SUPPORT_MC_MGCG |
1150 AMD_CG_SUPPORT_MC_LS |
1151 AMD_CG_SUPPORT_DRM_LS |
1152 AMD_CG_SUPPORT_UVD_MGCG |
1153 AMD_CG_SUPPORT_VCE_MGCG;
1154 adev->pg_flags = 0;
1155 adev->external_rev_id = adev->rev_id + 0x50;
1156 break;
1157 case CHIP_POLARIS12:
1158 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1159 AMD_CG_SUPPORT_GFX_RLC_LS |
1160 AMD_CG_SUPPORT_GFX_CP_LS |
1161 AMD_CG_SUPPORT_GFX_CGCG |
1162 AMD_CG_SUPPORT_GFX_CGLS |
1163 AMD_CG_SUPPORT_GFX_3D_CGCG |
1164 AMD_CG_SUPPORT_GFX_3D_CGLS |
1165 AMD_CG_SUPPORT_SDMA_MGCG |
1166 AMD_CG_SUPPORT_SDMA_LS |
1167 AMD_CG_SUPPORT_BIF_MGCG |
1168 AMD_CG_SUPPORT_BIF_LS |
1169 AMD_CG_SUPPORT_HDP_MGCG |
1170 AMD_CG_SUPPORT_HDP_LS |
1171 AMD_CG_SUPPORT_ROM_MGCG |
1172 AMD_CG_SUPPORT_MC_MGCG |
1173 AMD_CG_SUPPORT_MC_LS |
1174 AMD_CG_SUPPORT_DRM_LS |
1175 AMD_CG_SUPPORT_UVD_MGCG |
1176 AMD_CG_SUPPORT_VCE_MGCG;
1177 adev->pg_flags = 0;
1178 adev->external_rev_id = adev->rev_id + 0x64;
1179 break;
1180 case CHIP_VEGAM:
1181 adev->cg_flags = 0;
1182 /*AMD_CG_SUPPORT_GFX_MGCG |
1183 AMD_CG_SUPPORT_GFX_RLC_LS |
1184 AMD_CG_SUPPORT_GFX_CP_LS |
1185 AMD_CG_SUPPORT_GFX_CGCG |
1186 AMD_CG_SUPPORT_GFX_CGLS |
1187 AMD_CG_SUPPORT_GFX_3D_CGCG |
1188 AMD_CG_SUPPORT_GFX_3D_CGLS |
1189 AMD_CG_SUPPORT_SDMA_MGCG |
1190 AMD_CG_SUPPORT_SDMA_LS |
1191 AMD_CG_SUPPORT_BIF_MGCG |
1192 AMD_CG_SUPPORT_BIF_LS |
1193 AMD_CG_SUPPORT_HDP_MGCG |
1194 AMD_CG_SUPPORT_HDP_LS |
1195 AMD_CG_SUPPORT_ROM_MGCG |
1196 AMD_CG_SUPPORT_MC_MGCG |
1197 AMD_CG_SUPPORT_MC_LS |
1198 AMD_CG_SUPPORT_DRM_LS |
1199 AMD_CG_SUPPORT_UVD_MGCG |
1200 AMD_CG_SUPPORT_VCE_MGCG;*/
1201 adev->pg_flags = 0;
1202 adev->external_rev_id = adev->rev_id + 0x6E;
1203 break;
1204 case CHIP_CARRIZO:
1205 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1206 AMD_CG_SUPPORT_GFX_MGCG |
1207 AMD_CG_SUPPORT_GFX_MGLS |
1208 AMD_CG_SUPPORT_GFX_RLC_LS |
1209 AMD_CG_SUPPORT_GFX_CP_LS |
1210 AMD_CG_SUPPORT_GFX_CGTS |
1211 AMD_CG_SUPPORT_GFX_CGTS_LS |
1212 AMD_CG_SUPPORT_GFX_CGCG |
1213 AMD_CG_SUPPORT_GFX_CGLS |
1214 AMD_CG_SUPPORT_BIF_LS |
1215 AMD_CG_SUPPORT_HDP_MGCG |
1216 AMD_CG_SUPPORT_HDP_LS |
1217 AMD_CG_SUPPORT_SDMA_MGCG |
1218 AMD_CG_SUPPORT_SDMA_LS |
1219 AMD_CG_SUPPORT_VCE_MGCG;
1220 /* rev0 hardware requires workarounds to support PG */
1221 adev->pg_flags = 0;
1222 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1223 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1224 AMD_PG_SUPPORT_GFX_PIPELINE |
1225 AMD_PG_SUPPORT_CP |
1226 AMD_PG_SUPPORT_UVD |
1227 AMD_PG_SUPPORT_VCE;
1228 }
1229 adev->external_rev_id = adev->rev_id + 0x1;
1230 break;
1231 case CHIP_STONEY:
1232 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1233 AMD_CG_SUPPORT_GFX_MGCG |
1234 AMD_CG_SUPPORT_GFX_MGLS |
1235 AMD_CG_SUPPORT_GFX_RLC_LS |
1236 AMD_CG_SUPPORT_GFX_CP_LS |
1237 AMD_CG_SUPPORT_GFX_CGTS |
1238 AMD_CG_SUPPORT_GFX_CGTS_LS |
1239 AMD_CG_SUPPORT_GFX_CGLS |
1240 AMD_CG_SUPPORT_BIF_LS |
1241 AMD_CG_SUPPORT_HDP_MGCG |
1242 AMD_CG_SUPPORT_HDP_LS |
1243 AMD_CG_SUPPORT_SDMA_MGCG |
1244 AMD_CG_SUPPORT_SDMA_LS |
1245 AMD_CG_SUPPORT_VCE_MGCG;
1246 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1247 AMD_PG_SUPPORT_GFX_SMG |
1248 AMD_PG_SUPPORT_GFX_PIPELINE |
1249 AMD_PG_SUPPORT_CP |
1250 AMD_PG_SUPPORT_UVD |
1251 AMD_PG_SUPPORT_VCE;
1252 adev->external_rev_id = adev->rev_id + 0x61;
1253 break;
1254 default:
1255 /* FIXME: not supported yet */
1256 return -EINVAL;
1257 }
1258
1259 if (amdgpu_sriov_vf(adev)) {
1260 amdgpu_virt_init_setting(adev);
1261 xgpu_vi_mailbox_set_irq_funcs(adev);
1262 }
1263
1264 return 0;
1265}
1266
1267static int vi_common_late_init(void *handle)
1268{
1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270
1271 if (amdgpu_sriov_vf(adev))
1272 xgpu_vi_mailbox_get_irq(adev);
1273
1274 return 0;
1275}
1276
1277static int vi_common_sw_init(void *handle)
1278{
1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281 if (amdgpu_sriov_vf(adev))
1282 xgpu_vi_mailbox_add_irq_id(adev);
1283
1284 return 0;
1285}
1286
1287static int vi_common_sw_fini(void *handle)
1288{
1289 return 0;
1290}
1291
1292static int vi_common_hw_init(void *handle)
1293{
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295
1296 /* move the golden regs per IP block */
1297 vi_init_golden_registers(adev);
1298 /* enable pcie gen2/3 link */
1299 vi_pcie_gen3_enable(adev);
1300 /* enable aspm */
1301 vi_program_aspm(adev);
1302 /* enable the doorbell aperture */
1303 vi_enable_doorbell_aperture(adev, true);
1304
1305 return 0;
1306}
1307
1308static int vi_common_hw_fini(void *handle)
1309{
1310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1311
1312 /* enable the doorbell aperture */
1313 vi_enable_doorbell_aperture(adev, false);
1314
1315 if (amdgpu_sriov_vf(adev))
1316 xgpu_vi_mailbox_put_irq(adev);
1317
1318 return 0;
1319}
1320
1321static int vi_common_suspend(void *handle)
1322{
1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324
1325 return vi_common_hw_fini(adev);
1326}
1327
1328static int vi_common_resume(void *handle)
1329{
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331
1332 return vi_common_hw_init(adev);
1333}
1334
1335static bool vi_common_is_idle(void *handle)
1336{
1337 return true;
1338}
1339
1340static int vi_common_wait_for_idle(void *handle)
1341{
1342 return 0;
1343}
1344
1345static int vi_common_soft_reset(void *handle)
1346{
1347 return 0;
1348}
1349
1350static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1351 bool enable)
1352{
1353 uint32_t temp, data;
1354
1355 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1356
1357 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1358 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1359 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1360 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1361 else
1362 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1363 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1364 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1365
1366 if (temp != data)
1367 WREG32_PCIE(ixPCIE_CNTL2, data);
1368}
1369
1370static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1371 bool enable)
1372{
1373 uint32_t temp, data;
1374
1375 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1376
1377 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1378 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1379 else
1380 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1381
1382 if (temp != data)
1383 WREG32(mmHDP_HOST_PATH_CNTL, data);
1384}
1385
1386static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1387 bool enable)
1388{
1389 uint32_t temp, data;
1390
1391 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1392
1393 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1394 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1395 else
1396 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1397
1398 if (temp != data)
1399 WREG32(mmHDP_MEM_POWER_LS, data);
1400}
1401
1402static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1403 bool enable)
1404{
1405 uint32_t temp, data;
1406
1407 temp = data = RREG32(0x157a);
1408
1409 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1410 data |= 1;
1411 else
1412 data &= ~1;
1413
1414 if (temp != data)
1415 WREG32(0x157a, data);
1416}
1417
1418
1419static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1420 bool enable)
1421{
1422 uint32_t temp, data;
1423
1424 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1425
1426 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1427 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1428 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1429 else
1430 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1431 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1432
1433 if (temp != data)
1434 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1435}
1436
1437static int vi_common_set_clockgating_state_by_smu(void *handle,
1438 enum amd_clockgating_state state)
1439{
1440 uint32_t msg_id, pp_state = 0;
1441 uint32_t pp_support_state = 0;
1442 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1443
1444 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1445 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1446 pp_support_state = PP_STATE_SUPPORT_LS;
1447 pp_state = PP_STATE_LS;
1448 }
1449 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1450 pp_support_state |= PP_STATE_SUPPORT_CG;
1451 pp_state |= PP_STATE_CG;
1452 }
1453 if (state == AMD_CG_STATE_UNGATE)
1454 pp_state = 0;
1455 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1456 PP_BLOCK_SYS_MC,
1457 pp_support_state,
1458 pp_state);
1459 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1460 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1461 }
1462
1463 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1464 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1465 pp_support_state = PP_STATE_SUPPORT_LS;
1466 pp_state = PP_STATE_LS;
1467 }
1468 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1469 pp_support_state |= PP_STATE_SUPPORT_CG;
1470 pp_state |= PP_STATE_CG;
1471 }
1472 if (state == AMD_CG_STATE_UNGATE)
1473 pp_state = 0;
1474 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1475 PP_BLOCK_SYS_SDMA,
1476 pp_support_state,
1477 pp_state);
1478 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1479 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1480 }
1481
1482 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1483 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1484 pp_support_state = PP_STATE_SUPPORT_LS;
1485 pp_state = PP_STATE_LS;
1486 }
1487 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1488 pp_support_state |= PP_STATE_SUPPORT_CG;
1489 pp_state |= PP_STATE_CG;
1490 }
1491 if (state == AMD_CG_STATE_UNGATE)
1492 pp_state = 0;
1493 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1494 PP_BLOCK_SYS_HDP,
1495 pp_support_state,
1496 pp_state);
1497 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1498 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1499 }
1500
1501
1502 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1503 if (state == AMD_CG_STATE_UNGATE)
1504 pp_state = 0;
1505 else
1506 pp_state = PP_STATE_LS;
1507
1508 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1509 PP_BLOCK_SYS_BIF,
1510 PP_STATE_SUPPORT_LS,
1511 pp_state);
1512 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1513 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1514 }
1515 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1516 if (state == AMD_CG_STATE_UNGATE)
1517 pp_state = 0;
1518 else
1519 pp_state = PP_STATE_CG;
1520
1521 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1522 PP_BLOCK_SYS_BIF,
1523 PP_STATE_SUPPORT_CG,
1524 pp_state);
1525 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1526 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1527 }
1528
1529 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1530
1531 if (state == AMD_CG_STATE_UNGATE)
1532 pp_state = 0;
1533 else
1534 pp_state = PP_STATE_LS;
1535
1536 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1537 PP_BLOCK_SYS_DRM,
1538 PP_STATE_SUPPORT_LS,
1539 pp_state);
1540 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1541 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1542 }
1543
1544 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1545
1546 if (state == AMD_CG_STATE_UNGATE)
1547 pp_state = 0;
1548 else
1549 pp_state = PP_STATE_CG;
1550
1551 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1552 PP_BLOCK_SYS_ROM,
1553 PP_STATE_SUPPORT_CG,
1554 pp_state);
1555 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
1556 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1557 }
1558 return 0;
1559}
1560
1561static int vi_common_set_clockgating_state(void *handle,
1562 enum amd_clockgating_state state)
1563{
1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1565
1566 if (amdgpu_sriov_vf(adev))
1567 return 0;
1568
1569 switch (adev->asic_type) {
1570 case CHIP_FIJI:
1571 vi_update_bif_medium_grain_light_sleep(adev,
1572 state == AMD_CG_STATE_GATE);
1573 vi_update_hdp_medium_grain_clock_gating(adev,
1574 state == AMD_CG_STATE_GATE);
1575 vi_update_hdp_light_sleep(adev,
1576 state == AMD_CG_STATE_GATE);
1577 vi_update_rom_medium_grain_clock_gating(adev,
1578 state == AMD_CG_STATE_GATE);
1579 break;
1580 case CHIP_CARRIZO:
1581 case CHIP_STONEY:
1582 vi_update_bif_medium_grain_light_sleep(adev,
1583 state == AMD_CG_STATE_GATE);
1584 vi_update_hdp_medium_grain_clock_gating(adev,
1585 state == AMD_CG_STATE_GATE);
1586 vi_update_hdp_light_sleep(adev,
1587 state == AMD_CG_STATE_GATE);
1588 vi_update_drm_light_sleep(adev,
1589 state == AMD_CG_STATE_GATE);
1590 break;
1591 case CHIP_TONGA:
1592 case CHIP_POLARIS10:
1593 case CHIP_POLARIS11:
1594 case CHIP_POLARIS12:
1595 case CHIP_VEGAM:
1596 vi_common_set_clockgating_state_by_smu(adev, state);
1597 default:
1598 break;
1599 }
1600 return 0;
1601}
1602
1603static int vi_common_set_powergating_state(void *handle,
1604 enum amd_powergating_state state)
1605{
1606 return 0;
1607}
1608
1609static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1610{
1611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1612 int data;
1613
1614 if (amdgpu_sriov_vf(adev))
1615 *flags = 0;
1616
1617 /* AMD_CG_SUPPORT_BIF_LS */
1618 data = RREG32_PCIE(ixPCIE_CNTL2);
1619 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1620 *flags |= AMD_CG_SUPPORT_BIF_LS;
1621
1622 /* AMD_CG_SUPPORT_HDP_LS */
1623 data = RREG32(mmHDP_MEM_POWER_LS);
1624 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1625 *flags |= AMD_CG_SUPPORT_HDP_LS;
1626
1627 /* AMD_CG_SUPPORT_HDP_MGCG */
1628 data = RREG32(mmHDP_HOST_PATH_CNTL);
1629 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1630 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1631
1632 /* AMD_CG_SUPPORT_ROM_MGCG */
1633 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1634 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1635 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1636}
1637
1638static const struct amd_ip_funcs vi_common_ip_funcs = {
1639 .name = "vi_common",
1640 .early_init = vi_common_early_init,
1641 .late_init = vi_common_late_init,
1642 .sw_init = vi_common_sw_init,
1643 .sw_fini = vi_common_sw_fini,
1644 .hw_init = vi_common_hw_init,
1645 .hw_fini = vi_common_hw_fini,
1646 .suspend = vi_common_suspend,
1647 .resume = vi_common_resume,
1648 .is_idle = vi_common_is_idle,
1649 .wait_for_idle = vi_common_wait_for_idle,
1650 .soft_reset = vi_common_soft_reset,
1651 .set_clockgating_state = vi_common_set_clockgating_state,
1652 .set_powergating_state = vi_common_set_powergating_state,
1653 .get_clockgating_state = vi_common_get_clockgating_state,
1654};
1655
1656static const struct amdgpu_ip_block_version vi_common_ip_block =
1657{
1658 .type = AMD_IP_BLOCK_TYPE_COMMON,
1659 .major = 1,
1660 .minor = 0,
1661 .rev = 0,
1662 .funcs = &vi_common_ip_funcs,
1663};
1664
1665int vi_set_ip_blocks(struct amdgpu_device *adev)
1666{
1667 /* in early init stage, vbios code won't work */
1668 vi_detect_hw_virtualization(adev);
1669
1670 if (amdgpu_sriov_vf(adev))
1671 adev->virt.ops = &xgpu_vi_virt_ops;
1672
1673 switch (adev->asic_type) {
1674 case CHIP_TOPAZ:
1675 /* topaz has no DCE, UVD, VCE */
1676 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1677 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
1678 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
1679 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1680 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
1681 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1682 if (adev->enable_virtual_display)
1683 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1684 break;
1685 case CHIP_FIJI:
1686 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1687 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
1688 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1689 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1690 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1691 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1692 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1693 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1694#if defined(CONFIG_DRM_AMD_DC)
1695 else if (amdgpu_device_has_dc_support(adev))
1696 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1697#endif
1698 else
1699 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
1700 if (!amdgpu_sriov_vf(adev)) {
1701 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1702 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1703 }
1704 break;
1705 case CHIP_TONGA:
1706 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1707 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1708 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1709 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1710 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1711 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1712 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1713 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1714#if defined(CONFIG_DRM_AMD_DC)
1715 else if (amdgpu_device_has_dc_support(adev))
1716 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1717#endif
1718 else
1719 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
1720 if (!amdgpu_sriov_vf(adev)) {
1721 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
1722 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
1723 }
1724 break;
1725 case CHIP_POLARIS10:
1726 case CHIP_POLARIS11:
1727 case CHIP_POLARIS12:
1728 case CHIP_VEGAM:
1729 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1730 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
1731 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
1732 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1733 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
1734 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1735 if (adev->enable_virtual_display)
1736 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1737#if defined(CONFIG_DRM_AMD_DC)
1738 else if (amdgpu_device_has_dc_support(adev))
1739 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1740#endif
1741 else
1742 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
1743 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
1744 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1745 break;
1746 case CHIP_CARRIZO:
1747 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1748 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1749 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1750 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
1751 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1752 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1753 if (adev->enable_virtual_display)
1754 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1755#if defined(CONFIG_DRM_AMD_DC)
1756 else if (amdgpu_device_has_dc_support(adev))
1757 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1758#endif
1759 else
1760 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1761 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
1762 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
1763#if defined(CONFIG_DRM_AMD_ACP)
1764 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1765#endif
1766 break;
1767 case CHIP_STONEY:
1768 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
1769 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
1770 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
1771 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
1772 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
1773 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1774 if (adev->enable_virtual_display)
1775 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1776#if defined(CONFIG_DRM_AMD_DC)
1777 else if (amdgpu_device_has_dc_support(adev))
1778 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1779#endif
1780 else
1781 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
1782 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
1783 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
1784#if defined(CONFIG_DRM_AMD_ACP)
1785 amdgpu_device_ip_block_add(adev, &acp_ip_block);
1786#endif
1787 break;
1788 default:
1789 /* FIXME: not supported yet */
1790 return -EINVAL;
1791 }
1792
1793 return 0;
1794}
1795
1796void legacy_doorbell_index_init(struct amdgpu_device *adev)
1797{
1798 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
1799 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
1800 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
1801 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
1802 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
1803 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
1804 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
1805 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
1806 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
1807 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
1808 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
1809 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
1810 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
1811 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
1812}