tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_4.h"
26
27#include "nbio/nbio_7_4_offset.h"
28#include "nbio/nbio_7_4_sh_mask.h"
29#include "nbio/nbio_7_4_0_smn.h"
30#include <uapi/linux/kfd_ioctl.h>
31
32#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
33
34static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
35{
36 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
37 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
38 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
39 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
40}
41
42static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
43{
44 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
45
46 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
47 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
48
49 return tmp;
50}
51
52static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
53{
54 if (enable)
55 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
56 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
57 else
58 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
59}
60
61static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev,
62 struct amdgpu_ring *ring)
63{
64 if (!ring || !ring->funcs->emit_wreg)
65 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
66 else
67 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
68}
69
70static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
71{
72 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
73}
74
75static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
76 bool use_doorbell, int doorbell_index, int doorbell_size)
77{
78 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
79 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
80
81 u32 doorbell_range = RREG32(reg);
82
83 if (use_doorbell) {
84 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
85 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
86 } else
87 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
88
89 WREG32(reg, doorbell_range);
90}
91
92static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
93 bool enable)
94{
95 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
96}
97
98static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
99 bool enable)
100{
101 u32 tmp = 0;
102
103 if (enable) {
104 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
105 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
106 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
107
108 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
109 lower_32_bits(adev->doorbell.base));
110 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
111 upper_32_bits(adev->doorbell.base));
112 }
113
114 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
115}
116
117static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
118 bool use_doorbell, int doorbell_index)
119{
120 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
121
122 if (use_doorbell) {
123 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
124 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
125 } else
126 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
127
128 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
129}
130
131
132static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
133 bool enable)
134{
135 //TODO: Add support for v7.4
136}
137
138static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
139 bool enable)
140{
141 uint32_t def, data;
142
143 def = data = RREG32_PCIE(smnPCIE_CNTL2);
144 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
145 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
146 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
147 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
148 } else {
149 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
150 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
151 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
152 }
153
154 if (def != data)
155 WREG32_PCIE(smnPCIE_CNTL2, data);
156}
157
158static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
159 u32 *flags)
160{
161 int data;
162
163 /* AMD_CG_SUPPORT_BIF_MGCG */
164 data = RREG32_PCIE(smnCPM_CONTROL);
165 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
166 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
167
168 /* AMD_CG_SUPPORT_BIF_LS */
169 data = RREG32_PCIE(smnPCIE_CNTL2);
170 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
171 *flags |= AMD_CG_SUPPORT_BIF_LS;
172}
173
174static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
175{
176 u32 interrupt_cntl;
177
178 /* setup interrupt control */
179 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
180 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
181 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
182 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
183 */
184 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
185 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
186 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
187 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
188}
189
190static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
191{
192 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
193}
194
195static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
196{
197 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
198}
199
200static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
201{
202 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
203}
204
205static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
206{
207 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
208}
209
210static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
211 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
212 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
213 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
214 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
215 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
216 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
217 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
218 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
219 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
220 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
221 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
222 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
223};
224
225static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
226{
227 uint32_t reg;
228
229 reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
230 if (reg & 1)
231 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
232
233 if (reg & 0x80000000)
234 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
235
236 if (!reg) {
237 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
238 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
239 }
240}
241
242static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
243{
244 uint32_t def, data;
245
246 def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
247 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
248
249 if (def != data)
250 WREG32_PCIE(smnPCIE_CI_CNTL, data);
251}
252
253const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
254 .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg,
255 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
256 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
257 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
258 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
259 .get_rev_id = nbio_v7_4_get_rev_id,
260 .mc_access_enable = nbio_v7_4_mc_access_enable,
261 .hdp_flush = nbio_v7_4_hdp_flush,
262 .get_memsize = nbio_v7_4_get_memsize,
263 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
264 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
265 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
266 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
267 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
268 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
269 .get_clockgating_state = nbio_v7_4_get_clockgating_state,
270 .ih_control = nbio_v7_4_ih_control,
271 .init_registers = nbio_v7_4_init_registers,
272 .detect_hw_virt = nbio_v7_4_detect_hw_virt,
273 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
274};