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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AM33XX Power Management Routines
4 *
5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Vaibhav Bedia, Dave Gerlach
7 */
8
9#include <linux/clk.h>
10#include <linux/cpu.h>
11#include <linux/err.h>
12#include <linux/genalloc.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/nvmem-consumer.h>
18#include <linux/of.h>
19#include <linux/platform_data/pm33xx.h>
20#include <linux/platform_device.h>
21#include <linux/rtc.h>
22#include <linux/rtc/rtc-omap.h>
23#include <linux/sizes.h>
24#include <linux/sram.h>
25#include <linux/suspend.h>
26#include <linux/ti-emif-sram.h>
27#include <linux/wkup_m3_ipc.h>
28
29#include <asm/proc-fns.h>
30#include <asm/suspend.h>
31#include <asm/system_misc.h>
32
33#define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
34 (unsigned long)pm_sram->do_wfi)
35
36#define RTC_SCRATCH_RESUME_REG 0
37#define RTC_SCRATCH_MAGIC_REG 1
38#define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
39#define GIC_INT_SET_PENDING_BASE 0x200
40#define AM43XX_GIC_DIST_BASE 0x48241000
41
42static u32 rtc_magic_val;
43
44static int (*am33xx_do_wfi_sram)(unsigned long unused);
45static phys_addr_t am33xx_do_wfi_sram_phys;
46
47static struct gen_pool *sram_pool, *sram_pool_data;
48static unsigned long ocmcram_location, ocmcram_location_data;
49
50static struct rtc_device *omap_rtc;
51static void __iomem *gic_dist_base;
52
53static struct am33xx_pm_platform_data *pm_ops;
54static struct am33xx_pm_sram_addr *pm_sram;
55
56static struct device *pm33xx_dev;
57static struct wkup_m3_ipc *m3_ipc;
58
59#ifdef CONFIG_SUSPEND
60static int rtc_only_idle;
61static int retrigger_irq;
62static unsigned long suspend_wfi_flags;
63
64static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
65 .src = "Unknown",
66};
67
68static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
69 .irq_nr = 108, .src = "RTC Alarm",
70};
71
72static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
73 .irq_nr = 0, .src = "Ext wakeup",
74};
75#endif
76
77static u32 sram_suspend_address(unsigned long addr)
78{
79 return ((unsigned long)am33xx_do_wfi_sram +
80 AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
81}
82
83static int am33xx_push_sram_idle(void)
84{
85 struct am33xx_pm_ro_sram_data ro_sram_data;
86 int ret;
87 u32 table_addr, ro_data_addr;
88 void *copy_addr;
89
90 ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
91 ro_sram_data.amx3_pm_sram_data_phys =
92 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
93 ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
94
95 /* Save physical address to calculate resume offset during pm init */
96 am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
97 ocmcram_location);
98
99 am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
100 pm_sram->do_wfi,
101 *pm_sram->do_wfi_sz);
102 if (!am33xx_do_wfi_sram) {
103 dev_err(pm33xx_dev,
104 "PM: %s: am33xx_do_wfi copy to sram failed\n",
105 __func__);
106 return -ENODEV;
107 }
108
109 table_addr =
110 sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
111 ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
112 if (ret) {
113 dev_dbg(pm33xx_dev,
114 "PM: %s: EMIF function copy failed\n", __func__);
115 return -EPROBE_DEFER;
116 }
117
118 ro_data_addr =
119 sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
120 copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
121 &ro_sram_data,
122 sizeof(ro_sram_data));
123 if (!copy_addr) {
124 dev_err(pm33xx_dev,
125 "PM: %s: ro_sram_data copy to sram failed\n",
126 __func__);
127 return -ENODEV;
128 }
129
130 return 0;
131}
132
133static int __init am43xx_map_gic(void)
134{
135 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
136
137 if (!gic_dist_base)
138 return -ENOMEM;
139
140 return 0;
141}
142
143#ifdef CONFIG_SUSPEND
144struct wkup_m3_wakeup_src rtc_wake_src(void)
145{
146 u32 i;
147
148 i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40;
149
150 if (i) {
151 retrigger_irq = rtc_alarm_wakeup.irq_nr;
152 return rtc_alarm_wakeup;
153 }
154
155 retrigger_irq = rtc_ext_wakeup.irq_nr;
156
157 return rtc_ext_wakeup;
158}
159
160int am33xx_rtc_only_idle(unsigned long wfi_flags)
161{
162 omap_rtc_power_off_program(&omap_rtc->dev);
163 am33xx_do_wfi_sram(wfi_flags);
164 return 0;
165}
166
167static int am33xx_pm_suspend(suspend_state_t suspend_state)
168{
169 int i, ret = 0;
170
171 if (suspend_state == PM_SUSPEND_MEM &&
172 pm_ops->check_off_mode_enable()) {
173 pm_ops->prepare_rtc_suspend();
174 pm_ops->save_context();
175 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
176 clk_save_context();
177 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
178 suspend_wfi_flags);
179
180 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
181 dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
182
183 if (!ret) {
184 clk_restore_context();
185 pm_ops->restore_context();
186 m3_ipc->ops->set_rtc_only(m3_ipc);
187 am33xx_push_sram_idle();
188 }
189 } else {
190 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
191 suspend_wfi_flags);
192 }
193
194 if (ret) {
195 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
196 } else {
197 i = m3_ipc->ops->request_pm_status(m3_ipc);
198
199 switch (i) {
200 case 0:
201 dev_info(pm33xx_dev,
202 "PM: Successfully put all powerdomains to target state\n");
203 break;
204 case 1:
205 dev_err(pm33xx_dev,
206 "PM: Could not transition all powerdomains to target state\n");
207 ret = -1;
208 break;
209 default:
210 dev_err(pm33xx_dev,
211 "PM: CM3 returned unknown result = %d\n", i);
212 ret = -1;
213 }
214
215 /* print the wakeup reason */
216 if (rtc_only_idle) {
217 wakeup_src = rtc_wake_src();
218 pr_info("PM: Wakeup source %s\n", wakeup_src.src);
219 } else {
220 pr_info("PM: Wakeup source %s\n",
221 m3_ipc->ops->request_wake_src(m3_ipc));
222 }
223 }
224
225 if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
226 pm_ops->prepare_rtc_resume();
227
228 return ret;
229}
230
231static int am33xx_pm_enter(suspend_state_t suspend_state)
232{
233 int ret = 0;
234
235 switch (suspend_state) {
236 case PM_SUSPEND_MEM:
237 case PM_SUSPEND_STANDBY:
238 ret = am33xx_pm_suspend(suspend_state);
239 break;
240 default:
241 ret = -EINVAL;
242 }
243
244 return ret;
245}
246
247static int am33xx_pm_begin(suspend_state_t state)
248{
249 int ret = -EINVAL;
250 struct nvmem_device *nvmem;
251
252 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
253 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
254 "omap_rtc_scratch0");
255 if (nvmem)
256 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
257 (void *)&rtc_magic_val);
258 rtc_only_idle = 1;
259 } else {
260 rtc_only_idle = 0;
261 }
262
263 switch (state) {
264 case PM_SUSPEND_MEM:
265 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
266 break;
267 case PM_SUSPEND_STANDBY:
268 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
269 break;
270 }
271
272 return ret;
273}
274
275static void am33xx_pm_end(void)
276{
277 u32 val = 0;
278 struct nvmem_device *nvmem;
279
280 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
281 m3_ipc->ops->finish_low_power(m3_ipc);
282 if (rtc_only_idle) {
283 if (retrigger_irq)
284 /*
285 * 32 bits of Interrupt Set-Pending correspond to 32
286 * 32 interrupts. Compute the bit offset of the
287 * Interrupt and set that particular bit
288 * Compute the register offset by dividing interrupt
289 * number by 32 and mutiplying by 4
290 */
291 writel_relaxed(1 << (retrigger_irq & 31),
292 gic_dist_base + GIC_INT_SET_PENDING_BASE
293 + retrigger_irq / 32 * 4);
294 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
295 (void *)&val);
296 }
297
298 rtc_only_idle = 0;
299}
300
301static int am33xx_pm_valid(suspend_state_t state)
302{
303 switch (state) {
304 case PM_SUSPEND_STANDBY:
305 case PM_SUSPEND_MEM:
306 return 1;
307 default:
308 return 0;
309 }
310}
311
312static const struct platform_suspend_ops am33xx_pm_ops = {
313 .begin = am33xx_pm_begin,
314 .end = am33xx_pm_end,
315 .enter = am33xx_pm_enter,
316 .valid = am33xx_pm_valid,
317};
318#endif /* CONFIG_SUSPEND */
319
320static void am33xx_pm_set_ipc_ops(void)
321{
322 u32 resume_address;
323 int temp;
324
325 temp = ti_emif_get_mem_type();
326 if (temp < 0) {
327 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
328 return;
329 }
330 m3_ipc->ops->set_mem_type(m3_ipc, temp);
331
332 /* Physical resume address to be used by ROM code */
333 resume_address = am33xx_do_wfi_sram_phys +
334 *pm_sram->resume_offset + 0x4;
335
336 m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
337}
338
339static void am33xx_pm_free_sram(void)
340{
341 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
342 gen_pool_free(sram_pool_data, ocmcram_location_data,
343 sizeof(struct am33xx_pm_ro_sram_data));
344}
345
346/*
347 * Push the minimal suspend-resume code to SRAM
348 */
349static int am33xx_pm_alloc_sram(void)
350{
351 struct device_node *np;
352 int ret = 0;
353
354 np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
355 if (!np) {
356 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
357 if (!np) {
358 dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
359 __func__);
360 return -ENODEV;
361 }
362 }
363
364 sram_pool = of_gen_pool_get(np, "pm-sram", 0);
365 if (!sram_pool) {
366 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
367 __func__);
368 ret = -ENODEV;
369 goto mpu_put_node;
370 }
371
372 sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
373 if (!sram_pool_data) {
374 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
375 __func__);
376 ret = -ENODEV;
377 goto mpu_put_node;
378 }
379
380 ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
381 if (!ocmcram_location) {
382 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
383 __func__);
384 ret = -ENOMEM;
385 goto mpu_put_node;
386 }
387
388 ocmcram_location_data = gen_pool_alloc(sram_pool_data,
389 sizeof(struct emif_regs_amx3));
390 if (!ocmcram_location_data) {
391 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
392 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
393 ret = -ENOMEM;
394 }
395
396mpu_put_node:
397 of_node_put(np);
398 return ret;
399}
400
401static int am33xx_pm_rtc_setup(void)
402{
403 struct device_node *np;
404 unsigned long val = 0;
405 struct nvmem_device *nvmem;
406
407 np = of_find_node_by_name(NULL, "rtc");
408
409 if (of_device_is_available(np)) {
410 omap_rtc = rtc_class_open("rtc0");
411 if (!omap_rtc) {
412 pr_warn("PM: rtc0 not available");
413 return -EPROBE_DEFER;
414 }
415
416 nvmem = devm_nvmem_device_get(&omap_rtc->dev,
417 "omap_rtc_scratch0");
418 if (nvmem) {
419 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
420 4, (void *)&rtc_magic_val);
421 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
422 pr_warn("PM: bootloader does not support rtc-only!\n");
423
424 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
425 4, (void *)&val);
426 val = pm_sram->resume_address;
427 nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
428 4, (void *)&val);
429 }
430 } else {
431 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
432 }
433
434 return 0;
435}
436
437static int am33xx_pm_probe(struct platform_device *pdev)
438{
439 struct device *dev = &pdev->dev;
440 int ret;
441
442 if (!of_machine_is_compatible("ti,am33xx") &&
443 !of_machine_is_compatible("ti,am43"))
444 return -ENODEV;
445
446 pm_ops = dev->platform_data;
447 if (!pm_ops) {
448 dev_err(dev, "PM: Cannot get core PM ops!\n");
449 return -ENODEV;
450 }
451
452 ret = am43xx_map_gic();
453 if (ret) {
454 pr_err("PM: Could not ioremap GIC base\n");
455 return ret;
456 }
457
458 pm_sram = pm_ops->get_sram_addrs();
459 if (!pm_sram) {
460 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
461 return -ENODEV;
462 }
463
464 m3_ipc = wkup_m3_ipc_get();
465 if (!m3_ipc) {
466 pr_err("PM: Cannot get wkup_m3_ipc handle\n");
467 return -EPROBE_DEFER;
468 }
469
470 pm33xx_dev = dev;
471
472 ret = am33xx_pm_alloc_sram();
473 if (ret)
474 return ret;
475
476 ret = am33xx_pm_rtc_setup();
477 if (ret)
478 goto err_free_sram;
479
480 ret = am33xx_push_sram_idle();
481 if (ret)
482 goto err_free_sram;
483
484 am33xx_pm_set_ipc_ops();
485
486#ifdef CONFIG_SUSPEND
487 suspend_set_ops(&am33xx_pm_ops);
488
489 /*
490 * For a system suspend we must flush the caches, we want
491 * the DDR in self-refresh, we want to save the context
492 * of the EMIF, and we want the wkup_m3 to handle low-power
493 * transition.
494 */
495 suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
496 suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
497 suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
498 suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
499#endif /* CONFIG_SUSPEND */
500
501 ret = pm_ops->init();
502 if (ret) {
503 dev_err(dev, "Unable to call core pm init!\n");
504 ret = -ENODEV;
505 goto err_put_wkup_m3_ipc;
506 }
507
508 return 0;
509
510err_put_wkup_m3_ipc:
511 wkup_m3_ipc_put(m3_ipc);
512err_free_sram:
513 am33xx_pm_free_sram();
514 pm33xx_dev = NULL;
515 return ret;
516}
517
518static int am33xx_pm_remove(struct platform_device *pdev)
519{
520 suspend_set_ops(NULL);
521 wkup_m3_ipc_put(m3_ipc);
522 am33xx_pm_free_sram();
523 return 0;
524}
525
526static struct platform_driver am33xx_pm_driver = {
527 .driver = {
528 .name = "pm33xx",
529 },
530 .probe = am33xx_pm_probe,
531 .remove = am33xx_pm_remove,
532};
533module_platform_driver(am33xx_pm_driver);
534
535MODULE_ALIAS("platform:pm33xx");
536MODULE_LICENSE("GPL v2");
537MODULE_DESCRIPTION("am33xx power management driver");