tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28
29struct amd_vce_state {
30 /* vce clocks */
31 u32 evclk;
32 u32 ecclk;
33 /* gpu clocks */
34 u32 sclk;
35 u32 mclk;
36 u8 clk_idx;
37 u8 pstate;
38};
39
40
41enum amd_dpm_forced_level {
42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
51};
52
53enum amd_pm_state_type {
54 /* not used for dpm */
55 POWER_STATE_TYPE_DEFAULT,
56 POWER_STATE_TYPE_POWERSAVE,
57 /* user selectable states */
58 POWER_STATE_TYPE_BATTERY,
59 POWER_STATE_TYPE_BALANCED,
60 POWER_STATE_TYPE_PERFORMANCE,
61 /* internal states */
62 POWER_STATE_TYPE_INTERNAL_UVD,
63 POWER_STATE_TYPE_INTERNAL_UVD_SD,
64 POWER_STATE_TYPE_INTERNAL_UVD_HD,
65 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
66 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
67 POWER_STATE_TYPE_INTERNAL_BOOT,
68 POWER_STATE_TYPE_INTERNAL_THERMAL,
69 POWER_STATE_TYPE_INTERNAL_ACPI,
70 POWER_STATE_TYPE_INTERNAL_ULV,
71 POWER_STATE_TYPE_INTERNAL_3DPERF,
72};
73
74#define AMD_MAX_VCE_LEVELS 6
75
76enum amd_vce_level {
77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
83};
84
85enum amd_fan_ctrl_mode {
86 AMD_FAN_CTRL_NONE = 0,
87 AMD_FAN_CTRL_MANUAL = 1,
88 AMD_FAN_CTRL_AUTO = 2,
89};
90
91enum pp_clock_type {
92 PP_SCLK,
93 PP_MCLK,
94 PP_PCIE,
95 PP_SOCCLK,
96 PP_FCLK,
97 PP_DCEFCLK,
98 OD_SCLK,
99 OD_MCLK,
100 OD_VDDC_CURVE,
101 OD_RANGE,
102};
103
104enum amd_pp_sensors {
105 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
106 AMDGPU_PP_SENSOR_VDDNB,
107 AMDGPU_PP_SENSOR_VDDGFX,
108 AMDGPU_PP_SENSOR_UVD_VCLK,
109 AMDGPU_PP_SENSOR_UVD_DCLK,
110 AMDGPU_PP_SENSOR_VCE_ECCLK,
111 AMDGPU_PP_SENSOR_GPU_LOAD,
112 AMDGPU_PP_SENSOR_MEM_LOAD,
113 AMDGPU_PP_SENSOR_GFX_MCLK,
114 AMDGPU_PP_SENSOR_GPU_TEMP,
115 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
116 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
117 AMDGPU_PP_SENSOR_MEM_TEMP,
118 AMDGPU_PP_SENSOR_VCE_POWER,
119 AMDGPU_PP_SENSOR_UVD_POWER,
120 AMDGPU_PP_SENSOR_GPU_POWER,
121 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
122 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
123 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
124 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
125 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
126 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
127};
128
129enum amd_pp_task {
130 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
131 AMD_PP_TASK_ENABLE_USER_STATE,
132 AMD_PP_TASK_READJUST_POWER_STATE,
133 AMD_PP_TASK_COMPLETE_INIT,
134 AMD_PP_TASK_MAX
135};
136
137enum PP_SMC_POWER_PROFILE {
138 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
139 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
140 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
141 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
142 PP_SMC_POWER_PROFILE_VR = 0x4,
143 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
144 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
145};
146
147enum {
148 PP_GROUP_UNKNOWN = 0,
149 PP_GROUP_GFX = 1,
150 PP_GROUP_SYS,
151 PP_GROUP_MAX
152};
153
154enum PP_OD_DPM_TABLE_COMMAND {
155 PP_OD_EDIT_SCLK_VDDC_TABLE,
156 PP_OD_EDIT_MCLK_VDDC_TABLE,
157 PP_OD_EDIT_VDDC_CURVE,
158 PP_OD_RESTORE_DEFAULT_TABLE,
159 PP_OD_COMMIT_DPM_TABLE
160};
161
162struct pp_states_info {
163 uint32_t nums;
164 uint32_t states[16];
165};
166
167enum PP_HWMON_TEMP {
168 PP_TEMP_EDGE = 0,
169 PP_TEMP_JUNCTION,
170 PP_TEMP_MEM,
171 PP_TEMP_MAX
172};
173
174#define PP_GROUP_MASK 0xF0000000
175#define PP_GROUP_SHIFT 28
176
177#define PP_BLOCK_MASK 0x0FFFFF00
178#define PP_BLOCK_SHIFT 8
179
180#define PP_BLOCK_GFX_CG 0x01
181#define PP_BLOCK_GFX_MG 0x02
182#define PP_BLOCK_GFX_3D 0x04
183#define PP_BLOCK_GFX_RLC 0x08
184#define PP_BLOCK_GFX_CP 0x10
185#define PP_BLOCK_SYS_BIF 0x01
186#define PP_BLOCK_SYS_MC 0x02
187#define PP_BLOCK_SYS_ROM 0x04
188#define PP_BLOCK_SYS_DRM 0x08
189#define PP_BLOCK_SYS_HDP 0x10
190#define PP_BLOCK_SYS_SDMA 0x20
191
192#define PP_STATE_MASK 0x0000000F
193#define PP_STATE_SHIFT 0
194#define PP_STATE_SUPPORT_MASK 0x000000F0
195#define PP_STATE_SUPPORT_SHIFT 0
196
197#define PP_STATE_CG 0x01
198#define PP_STATE_LS 0x02
199#define PP_STATE_DS 0x04
200#define PP_STATE_SD 0x08
201#define PP_STATE_SUPPORT_CG 0x10
202#define PP_STATE_SUPPORT_LS 0x20
203#define PP_STATE_SUPPORT_DS 0x40
204#define PP_STATE_SUPPORT_SD 0x80
205
206#define PP_CG_MSG_ID(group, block, support, state) \
207 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
208 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
209
210struct seq_file;
211enum amd_pp_clock_type;
212struct amd_pp_simple_clock_info;
213struct amd_pp_display_configuration;
214struct amd_pp_clock_info;
215struct pp_display_clock_request;
216struct pp_clock_levels_with_voltage;
217struct pp_clock_levels_with_latency;
218struct amd_pp_clocks;
219
220struct amd_pm_funcs {
221/* export for dpm on ci and si */
222 int (*pre_set_power_state)(void *handle);
223 int (*set_power_state)(void *handle);
224 void (*post_set_power_state)(void *handle);
225 void (*display_configuration_changed)(void *handle);
226 void (*print_power_state)(void *handle, void *ps);
227 bool (*vblank_too_short)(void *handle);
228 void (*enable_bapm)(void *handle, bool enable);
229 int (*check_state_equal)(void *handle,
230 void *cps,
231 void *rps,
232 bool *equal);
233/* export for sysfs */
234 void (*set_fan_control_mode)(void *handle, u32 mode);
235 u32 (*get_fan_control_mode)(void *handle);
236 int (*set_fan_speed_percent)(void *handle, u32 speed);
237 int (*get_fan_speed_percent)(void *handle, u32 *speed);
238 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
239 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
240 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
241 int (*get_sclk_od)(void *handle);
242 int (*set_sclk_od)(void *handle, uint32_t value);
243 int (*get_mclk_od)(void *handle);
244 int (*set_mclk_od)(void *handle, uint32_t value);
245 int (*read_sensor)(void *handle, int idx, void *value, int *size);
246 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
247 enum amd_pm_state_type (*get_current_power_state)(void *handle);
248 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
249 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
250 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
251 int (*get_pp_table)(void *handle, char **table);
252 int (*set_pp_table)(void *handle, const char *buf, size_t size);
253 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
254 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
255/* export to amdgpu */
256 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
257 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
258 enum amd_pm_state_type *user_state);
259 int (*load_firmware)(void *handle);
260 int (*wait_for_fw_loading_complete)(void *handle);
261 int (*set_powergating_by_smu)(void *handle,
262 uint32_t block_type, bool gate);
263 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
264 int (*set_power_limit)(void *handle, uint32_t n);
265 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
266 int (*get_power_profile_mode)(void *handle, char *buf);
267 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
268 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
269/* export to DC */
270 u32 (*get_sclk)(void *handle, bool low);
271 u32 (*get_mclk)(void *handle, bool low);
272 int (*display_configuration_change)(void *handle,
273 const struct amd_pp_display_configuration *input);
274 int (*get_display_power_level)(void *handle,
275 struct amd_pp_simple_clock_info *output);
276 int (*get_current_clocks)(void *handle,
277 struct amd_pp_clock_info *clocks);
278 int (*get_clock_by_type)(void *handle,
279 enum amd_pp_clock_type type,
280 struct amd_pp_clocks *clocks);
281 int (*get_clock_by_type_with_latency)(void *handle,
282 enum amd_pp_clock_type type,
283 struct pp_clock_levels_with_latency *clocks);
284 int (*get_clock_by_type_with_voltage)(void *handle,
285 enum amd_pp_clock_type type,
286 struct pp_clock_levels_with_voltage *clocks);
287 int (*set_watermarks_for_clocks_ranges)(void *handle,
288 void *clock_ranges);
289 int (*display_clock_voltage_request)(void *handle,
290 struct pp_display_clock_request *clock);
291 int (*get_display_mode_validation_clocks)(void *handle,
292 struct amd_pp_simple_clock_info *clocks);
293 int (*notify_smu_enable_pwe)(void *handle);
294 int (*enable_mgpu_fan_boost)(void *handle);
295 int (*set_active_display_count)(void *handle, uint32_t count);
296 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
297 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
298 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
299 int (*get_asic_baco_capability)(void *handle, bool *cap);
300 int (*get_asic_baco_state)(void *handle, int *state);
301 int (*set_asic_baco_state)(void *handle, int state);
302 int (*get_ppfeature_status)(void *handle, char *buf);
303 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
304};
305
306#endif