tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * shmob_drm_regs.h -- SH Mobile DRM registers
4 *
5 * Copyright (C) 2012 Renesas Electronics Corporation
6 *
7 * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#ifndef __SHMOB_DRM_REGS_H__
11#define __SHMOB_DRM_REGS_H__
12
13#include <linux/io.h>
14
15/* Register definitions */
16#define LDDCKPAT1R 0x400
17#define LDDCKPAT2R 0x404
18#define LDDCKR 0x410
19#define LDDCKR_ICKSEL_BUS (0 << 16)
20#define LDDCKR_ICKSEL_MIPI (1 << 16)
21#define LDDCKR_ICKSEL_HDMI (2 << 16)
22#define LDDCKR_ICKSEL_EXT (3 << 16)
23#define LDDCKR_ICKSEL_MASK (7 << 16)
24#define LDDCKR_MOSEL (1 << 6)
25#define LDDCKSTPR 0x414
26#define LDDCKSTPR_DCKSTS (1 << 16)
27#define LDDCKSTPR_DCKSTP (1 << 0)
28#define LDMT1R 0x418
29#define LDMT1R_VPOL (1 << 28)
30#define LDMT1R_HPOL (1 << 27)
31#define LDMT1R_DWPOL (1 << 26)
32#define LDMT1R_DIPOL (1 << 25)
33#define LDMT1R_DAPOL (1 << 24)
34#define LDMT1R_HSCNT (1 << 17)
35#define LDMT1R_DWCNT (1 << 16)
36#define LDMT1R_IFM (1 << 12)
37#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
38#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
39#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
40#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
41#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
42#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
43#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
44#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
45#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
46#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
47#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
48#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
49#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
50#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
51#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
52#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
53#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
54#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
55#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
56#define LDMT1R_MIFTYP_MASK (0xf << 0)
57#define LDMT2R 0x41c
58#define LDMT2R_CSUP_MASK (7 << 26)
59#define LDMT2R_CSUP_SHIFT 26
60#define LDMT2R_RSV (1 << 25)
61#define LDMT2R_VSEL (1 << 24)
62#define LDMT2R_WCSC_MASK (0xff << 16)
63#define LDMT2R_WCSC_SHIFT 16
64#define LDMT2R_WCEC_MASK (0xff << 8)
65#define LDMT2R_WCEC_SHIFT 8
66#define LDMT2R_WCLW_MASK (0xff << 0)
67#define LDMT2R_WCLW_SHIFT 0
68#define LDMT3R 0x420
69#define LDMT3R_RDLC_MASK (0x3f << 24)
70#define LDMT3R_RDLC_SHIFT 24
71#define LDMT3R_RCSC_MASK (0xff << 16)
72#define LDMT3R_RCSC_SHIFT 16
73#define LDMT3R_RCEC_MASK (0xff << 8)
74#define LDMT3R_RCEC_SHIFT 8
75#define LDMT3R_RCLW_MASK (0xff << 0)
76#define LDMT3R_RCLW_SHIFT 0
77#define LDDFR 0x424
78#define LDDFR_CF1 (1 << 18)
79#define LDDFR_CF0 (1 << 17)
80#define LDDFR_CC (1 << 16)
81#define LDDFR_YF_420 (0 << 8)
82#define LDDFR_YF_422 (1 << 8)
83#define LDDFR_YF_444 (2 << 8)
84#define LDDFR_YF_MASK (3 << 8)
85#define LDDFR_PKF_ARGB32 (0x00 << 0)
86#define LDDFR_PKF_RGB16 (0x03 << 0)
87#define LDDFR_PKF_RGB24 (0x0b << 0)
88#define LDDFR_PKF_MASK (0x1f << 0)
89#define LDSM1R 0x428
90#define LDSM1R_OS (1 << 0)
91#define LDSM2R 0x42c
92#define LDSM2R_OSTRG (1 << 0)
93#define LDSA1R 0x430
94#define LDSA2R 0x434
95#define LDMLSR 0x438
96#define LDWBFR 0x43c
97#define LDWBCNTR 0x440
98#define LDWBAR 0x444
99#define LDHCNR 0x448
100#define LDHSYNR 0x44c
101#define LDVLNR 0x450
102#define LDVSYNR 0x454
103#define LDHPDR 0x458
104#define LDVPDR 0x45c
105#define LDPMR 0x460
106#define LDPMR_LPS (3 << 0)
107#define LDINTR 0x468
108#define LDINTR_FE (1 << 10)
109#define LDINTR_VSE (1 << 9)
110#define LDINTR_VEE (1 << 8)
111#define LDINTR_FS (1 << 2)
112#define LDINTR_VSS (1 << 1)
113#define LDINTR_VES (1 << 0)
114#define LDINTR_STATUS_MASK (0xff << 0)
115#define LDSR 0x46c
116#define LDSR_MSS (1 << 10)
117#define LDSR_MRS (1 << 8)
118#define LDSR_AS (1 << 1)
119#define LDCNT1R 0x470
120#define LDCNT1R_DE (1 << 0)
121#define LDCNT2R 0x474
122#define LDCNT2R_BR (1 << 8)
123#define LDCNT2R_MD (1 << 3)
124#define LDCNT2R_SE (1 << 2)
125#define LDCNT2R_ME (1 << 1)
126#define LDCNT2R_DO (1 << 0)
127#define LDRCNTR 0x478
128#define LDRCNTR_SRS (1 << 17)
129#define LDRCNTR_SRC (1 << 16)
130#define LDRCNTR_MRS (1 << 1)
131#define LDRCNTR_MRC (1 << 0)
132#define LDDDSR 0x47c
133#define LDDDSR_LS (1 << 2)
134#define LDDDSR_WS (1 << 1)
135#define LDDDSR_BS (1 << 0)
136#define LDHAJR 0x4a0
137
138#define LDDWD0R 0x800
139#define LDDWDxR_WDACT (1 << 28)
140#define LDDWDxR_RSW (1 << 24)
141#define LDDRDR 0x840
142#define LDDRDR_RSR (1 << 24)
143#define LDDRDR_DRD_MASK (0x3ffff << 0)
144#define LDDWAR 0x900
145#define LDDWAR_WA (1 << 0)
146#define LDDRAR 0x904
147#define LDDRAR_RA (1 << 0)
148
149#define LDBCR 0xb00
150#define LDBCR_UPC(n) (1 << ((n) + 16))
151#define LDBCR_UPF(n) (1 << ((n) + 8))
152#define LDBCR_UPD(n) (1 << ((n) + 0))
153#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
154#define LDBBSIFR_EN (1 << 31)
155#define LDBBSIFR_VS (1 << 29)
156#define LDBBSIFR_BRSEL (1 << 28)
157#define LDBBSIFR_MX (1 << 27)
158#define LDBBSIFR_MY (1 << 26)
159#define LDBBSIFR_CV3 (3 << 24)
160#define LDBBSIFR_CV2 (2 << 24)
161#define LDBBSIFR_CV1 (1 << 24)
162#define LDBBSIFR_CV0 (0 << 24)
163#define LDBBSIFR_CV_MASK (3 << 24)
164#define LDBBSIFR_LAY_MASK (0xff << 16)
165#define LDBBSIFR_LAY_SHIFT 16
166#define LDBBSIFR_ROP3_MASK (0xff << 16)
167#define LDBBSIFR_ROP3_SHIFT 16
168#define LDBBSIFR_AL_PL8 (3 << 14)
169#define LDBBSIFR_AL_PL1 (2 << 14)
170#define LDBBSIFR_AL_PK (1 << 14)
171#define LDBBSIFR_AL_1 (0 << 14)
172#define LDBBSIFR_AL_MASK (3 << 14)
173#define LDBBSIFR_SWPL (1 << 10)
174#define LDBBSIFR_SWPW (1 << 9)
175#define LDBBSIFR_SWPB (1 << 8)
176#define LDBBSIFR_RY (1 << 7)
177#define LDBBSIFR_CHRR_420 (2 << 0)
178#define LDBBSIFR_CHRR_422 (1 << 0)
179#define LDBBSIFR_CHRR_444 (0 << 0)
180#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
181#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
182#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
183#define LDBBSIFR_RPKF_MASK (0x1f << 0)
184#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
185#define LDBBSSZR_BVSS_MASK (0xfff << 16)
186#define LDBBSSZR_BVSS_SHIFT 16
187#define LDBBSSZR_BHSS_MASK (0xfff << 0)
188#define LDBBSSZR_BHSS_SHIFT 0
189#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
190#define LDBBLOCR_CVLC_MASK (0xfff << 16)
191#define LDBBLOCR_CVLC_SHIFT 16
192#define LDBBLOCR_CHLC_MASK (0xfff << 0)
193#define LDBBLOCR_CHLC_SHIFT 0
194#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
195#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
196#define LDBBSMWR_BSMWA_SHIFT 16
197#define LDBBSMWR_BSMW_MASK (0xffff << 0)
198#define LDBBSMWR_BSMW_SHIFT 0
199#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
200#define LDBBSAYR_FG1A_MASK (0xff << 24)
201#define LDBBSAYR_FG1A_SHIFT 24
202#define LDBBSAYR_FG1R_MASK (0xff << 16)
203#define LDBBSAYR_FG1R_SHIFT 16
204#define LDBBSAYR_FG1G_MASK (0xff << 8)
205#define LDBBSAYR_FG1G_SHIFT 8
206#define LDBBSAYR_FG1B_MASK (0xff << 0)
207#define LDBBSAYR_FG1B_SHIFT 0
208#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
209#define LDBBSACR_FG2A_MASK (0xff << 24)
210#define LDBBSACR_FG2A_SHIFT 24
211#define LDBBSACR_FG2R_MASK (0xff << 16)
212#define LDBBSACR_FG2R_SHIFT 16
213#define LDBBSACR_FG2G_MASK (0xff << 8)
214#define LDBBSACR_FG2G_SHIFT 8
215#define LDBBSACR_FG2B_MASK (0xff << 0)
216#define LDBBSACR_FG2B_SHIFT 0
217#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
218#define LDBBSAAR_AP_MASK (0xff << 24)
219#define LDBBSAAR_AP_SHIFT 24
220#define LDBBSAAR_R_MASK (0xff << 16)
221#define LDBBSAAR_R_SHIFT 16
222#define LDBBSAAR_GY_MASK (0xff << 8)
223#define LDBBSAAR_GY_SHIFT 8
224#define LDBBSAAR_B_MASK (0xff << 0)
225#define LDBBSAAR_B_SHIFT 0
226#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
227#define LDBBPPCR_AP_MASK (0xff << 24)
228#define LDBBPPCR_AP_SHIFT 24
229#define LDBBPPCR_R_MASK (0xff << 16)
230#define LDBBPPCR_R_SHIFT 16
231#define LDBBPPCR_GY_MASK (0xff << 8)
232#define LDBBPPCR_GY_SHIFT 8
233#define LDBBPPCR_B_MASK (0xff << 0)
234#define LDBBPPCR_B_SHIFT 0
235#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
236#define LDBBBGCL_BGA_MASK (0xff << 24)
237#define LDBBBGCL_BGA_SHIFT 24
238#define LDBBBGCL_BGR_MASK (0xff << 16)
239#define LDBBBGCL_BGR_SHIFT 16
240#define LDBBBGCL_BGG_MASK (0xff << 8)
241#define LDBBBGCL_BGG_SHIFT 8
242#define LDBBBGCL_BGB_MASK (0xff << 0)
243#define LDBBBGCL_BGB_SHIFT 0
244
245#define LCDC_SIDE_B_OFFSET 0x1000
246#define LCDC_MIRROR_OFFSET 0x2000
247
248static inline bool lcdc_is_banked(u32 reg)
249{
250 switch (reg) {
251 case LDMT1R:
252 case LDMT2R:
253 case LDMT3R:
254 case LDDFR:
255 case LDSM1R:
256 case LDSA1R:
257 case LDSA2R:
258 case LDMLSR:
259 case LDWBFR:
260 case LDWBCNTR:
261 case LDWBAR:
262 case LDHCNR:
263 case LDHSYNR:
264 case LDVLNR:
265 case LDVSYNR:
266 case LDHPDR:
267 case LDVPDR:
268 case LDHAJR:
269 return true;
270 default:
271 return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3);
272 }
273}
274
275static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg,
276 u32 data)
277{
278 iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET);
279}
280
281static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data)
282{
283 iowrite32(data, sdev->mmio + reg);
284 if (lcdc_is_banked(reg))
285 iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET);
286}
287
288static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg)
289{
290 return ioread32(sdev->mmio + reg);
291}
292
293static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg,
294 u32 mask, u32 until)
295{
296 unsigned long timeout = jiffies + msecs_to_jiffies(5);
297
298 while ((lcdc_read(sdev, reg) & mask) != until) {
299 if (time_after(jiffies, timeout))
300 return -ETIMEDOUT;
301 cpu_relax();
302 }
303
304 return 0;
305}
306
307#endif /* __SHMOB_DRM_REGS_H__ */