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at v5.3-rc4 30 lines 747 B view raw
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7/* Video Clock */ 8 9#ifndef __MESON_VCLK_H 10#define __MESON_VCLK_H 11 12enum { 13 MESON_VCLK_TARGET_CVBS = 0, 14 MESON_VCLK_TARGET_HDMI = 1, 15 MESON_VCLK_TARGET_DMT = 2, 16}; 17 18/* 27MHz is the CVBS Pixel Clock */ 19#define MESON_VCLK_CVBS 27000 20 21enum drm_mode_status 22meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); 23enum drm_mode_status 24meson_vclk_vic_supported_freq(unsigned int freq); 25 26void meson_vclk_setup(struct meson_drm *priv, unsigned int target, 27 unsigned int vclk_freq, unsigned int venc_freq, 28 unsigned int dac_freq, bool hdmi_use_enci); 29 30#endif /* __MESON_VCLK_H */