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1* Clock Block on Freescale QorIQ Platforms
2
3Freescale QorIQ chips take primary clocking input from the external
4SYSCLK signal. The SYSCLK input (frequency) is multiplied using
5multiple phase locked loops (PLL) to create a variety of frequencies
6which can then be passed to a variety of internal logic, including
7cores and peripheral IP blocks.
8Please refer to the Reference Manual for details.
9
10All references to "1.0" and "2.0" refer to the QorIQ chassis version to
11which the chip complies.
12
13Chassis Version Example Chips
14--------------- -------------
151.0 p4080, p5020, p5040
162.0 t4240, b4860
17
181. Clock Block Binding
19
20Required properties:
21- compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
23 compatible string.
24
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t1023-clockgen"
32 * "fsl,t1024-clockgen"
33 * "fsl,t1040-clockgen"
34 * "fsl,t1042-clockgen"
35 * "fsl,t2080-clockgen"
36 * "fsl,t2081-clockgen"
37 * "fsl,t4240-clockgen"
38 * "fsl,b4420-clockgen"
39 * "fsl,b4860-clockgen"
40 * "fsl,ls1012a-clockgen"
41 * "fsl,ls1021a-clockgen"
42 * "fsl,ls1028a-clockgen"
43 * "fsl,ls1043a-clockgen"
44 * "fsl,ls1046a-clockgen"
45 * "fsl,ls1088a-clockgen"
46 * "fsl,ls2080a-clockgen"
47 Chassis-version clock strings include:
48 * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
49 * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
50- reg: Describes the address of the device's resources within the
51 address space defined by its parent bus, and resource zero
52 represents the clock register set
53
54Optional properties:
55- ranges: Allows valid translation between child's address space and
56 parent's. Must be present if the device has sub-nodes.
57- #address-cells: Specifies the number of cells used to represent
58 physical base addresses. Must be present if the device has
59 sub-nodes and set to 1 if present
60- #size-cells: Specifies the number of cells used to represent
61 the size of an address. Must be present if the device has
62 sub-nodes and set to 1 if present
63- clock-frequency: Input system clock frequency (SYSCLK)
64- clocks: If clock-frequency is not specified, sysclk may be provided
65 as an input clock. Either clock-frequency or clocks must be
66 provided.
67 A second input clock, called "coreclk", may be provided if
68 core PLLs are based on a different input clock from the
69 platform PLL.
70- clock-names: Required if a coreclk is present. Valid names are
71 "sysclk" and "coreclk".
72
732. Clock Provider
74
75The clockgen node should act as a clock provider, though in older device
76trees the children of the clockgen node are the clock providers.
77
78When the clockgen node is a clock provider, #clock-cells = <2>.
79The first cell of the clock specifier is the clock type, and the
80second cell is the clock index for the specified type.
81
82 Type# Name Index Cell
83 0 sysclk must be 0
84 1 cmux index (n in CLKCnCSR)
85 2 hwaccel index (n in CLKCGnHWACSR)
86 3 fman 0 for fm1, 1 for fm2
87 4 platform pll n=pll/(n+1). For example, when n=1,
88 that means output_freq=PLL_freq/2.
89 5 coreclk must be 0
90
913. Example
92
93 clockgen: global-utilities@e1000 {
94 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
95 clock-frequency = <133333333>;
96 reg = <0xe1000 0x1000>;
97 #clock-cells = <2>;
98 };
99
100 fman@400000 {
101 ...
102 clocks = <&clockgen 3 0>;
103 ...
104 };
105}
1064. Legacy Child Nodes
107
108NOTE: These nodes are deprecated. Kernels should continue to support
109device trees with these nodes, but new device trees should not use them.
110
111Most of the bindings are from the common clock binding[1].
112 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
113
114Required properties:
115- compatible : Should include one of the following:
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
118 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
119 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
120 * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
121 It takes parent's clock-frequency as its clock.
122 * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
123 It takes parent's clock-frequency as its clock.
124 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
125 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
126- #clock-cells: From common clock binding. The number of cells in a
127 clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
130 clock-specifier cell may take the following values:
131 * 0 - equal to the PLL frequency
132 * 1 - equal to the PLL frequency divided by 2
133 * 2 - equal to the PLL frequency divided by 4
134
135Recommended properties:
136- clocks: Should be the phandle of input parent clock
137- clock-names: From common clock binding, indicates the clock name
138- clock-output-names: From common clock binding, indicates the names of
139 output clocks
140- reg: Should be the offset and length of clock block base address.
141 The length should be 4.
142
143Legacy Example:
144/ {
145 clockgen: global-utilities@e1000 {
146 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
147 ranges = <0x0 0xe1000 0x1000>;
148 clock-frequency = <133333333>;
149 reg = <0xe1000 0x1000>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152
153 sysclk: sysclk {
154 #clock-cells = <0>;
155 compatible = "fsl,qoriq-sysclk-1.0";
156 clock-output-names = "sysclk";
157 };
158
159 pll0: pll0@800 {
160 #clock-cells = <1>;
161 reg = <0x800 0x4>;
162 compatible = "fsl,qoriq-core-pll-1.0";
163 clocks = <&sysclk>;
164 clock-output-names = "pll0", "pll0-div2";
165 };
166
167 pll1: pll1@820 {
168 #clock-cells = <1>;
169 reg = <0x820 0x4>;
170 compatible = "fsl,qoriq-core-pll-1.0";
171 clocks = <&sysclk>;
172 clock-output-names = "pll1", "pll1-div2";
173 };
174
175 mux0: mux0@0 {
176 #clock-cells = <0>;
177 reg = <0x0 0x4>;
178 compatible = "fsl,qoriq-core-mux-1.0";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
181 clock-output-names = "cmux0";
182 };
183
184 mux1: mux1@20 {
185 #clock-cells = <0>;
186 reg = <0x20 0x4>;
187 compatible = "fsl,qoriq-core-mux-1.0";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
190 clock-output-names = "cmux1";
191 };
192
193 platform-pll: platform-pll@c00 {
194 #clock-cells = <1>;
195 reg = <0xc00 0x4>;
196 compatible = "fsl,qoriq-platform-pll-1.0";
197 clocks = <&sysclk>;
198 clock-output-names = "platform-pll", "platform-pll-div2";
199 };
200 };
201};
202
203Example for legacy clock consumer:
204
205/ {
206 cpu0: PowerPC,e5500@0 {
207 ...
208 clocks = <&mux0>;
209 ...
210 };
211};