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at v5.3-rc1 63 lines 1.8 kB view raw
1* Freescale Quad Serial Peripheral Interface(QuadSPI) 2 3Required properties: 4 - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi", 5 "fsl,imx7d-qspi", "fsl,imx6ul-qspi", 6 "fsl,ls1021a-qspi" 7 or 8 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi", 9 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" 10 - reg : the first contains the register location and length, 11 the second contains the memory mapping address and length 12 - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" 13 - interrupts : Should contain the interrupt for the device 14 - clocks : The clocks needed by the QuadSPI controller 15 - clock-names : Should contain the name of the clocks: "qspi_en" and "qspi". 16 17Required SPI slave node properties: 18 - reg: There are two buses (A and B) with two chip selects each. 19 This encodes to which bus and CS the flash is connected: 20 <0>: Bus A, CS 0 21 <1>: Bus A, CS 1 22 <2>: Bus B, CS 0 23 <3>: Bus B, CS 1 24 25Example: 26 27qspi0: quadspi@40044000 { 28 compatible = "fsl,vf610-qspi"; 29 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>; 30 reg-names = "QuadSPI", "QuadSPI-memory"; 31 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&clks VF610_CLK_QSPI0_EN>, 33 <&clks VF610_CLK_QSPI0>; 34 clock-names = "qspi_en", "qspi"; 35 36 flash0: s25fl128s@0 { 37 .... 38 }; 39}; 40 41Example showing the usage of two SPI NOR devices on bus A: 42 43&qspi2 { 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_qspi2>; 46 status = "okay"; 47 48 flash0: n25q256a@0 { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 compatible = "micron,n25q256a", "jedec,spi-nor"; 52 spi-max-frequency = <29000000>; 53 reg = <0>; 54 }; 55 56 flash1: n25q256a@1 { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 compatible = "micron,n25q256a", "jedec,spi-nor"; 60 spi-max-frequency = <29000000>; 61 reg = <1>; 62 }; 63};