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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <sound/hda_codec.h>
15#include <sound/hdaudio_ext.h>
16#include "shim.h"
17
18/* PCI registers */
19#define PCI_TCSEL 0x44
20#define PCI_PGCTL PCI_TCSEL
21#define PCI_CGCTL 0x48
22
23/* PCI_PGCTL bits */
24#define PCI_PGCTL_ADSPPGD BIT(2)
25#define PCI_PGCTL_LSRMD_MASK BIT(4)
26
27/* PCI_CGCTL bits */
28#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
29#define PCI_CGCTL_ADSPDCGE BIT(1)
30
31/* Legacy HDA registers and bits used - widths are variable */
32#define SOF_HDA_GCAP 0x0
33#define SOF_HDA_GCTL 0x8
34/* accept unsol. response enable */
35#define SOF_HDA_GCTL_UNSOL BIT(8)
36#define SOF_HDA_LLCH 0x14
37#define SOF_HDA_INTCTL 0x20
38#define SOF_HDA_INTSTS 0x24
39#define SOF_HDA_WAKESTS 0x0E
40#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
41#define SOF_HDA_RIRBSTS 0x5d
42#define SOF_HDA_VS_EM2_L1SEN BIT(13)
43
44/* SOF_HDA_GCTL register bist */
45#define SOF_HDA_GCTL_RESET BIT(0)
46
47/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
48#define SOF_HDA_INT_GLOBAL_EN BIT(31)
49#define SOF_HDA_INT_CTRL_EN BIT(30)
50#define SOF_HDA_INT_ALL_STREAM 0xff
51
52#define SOF_HDA_MAX_CAPS 10
53#define SOF_HDA_CAP_ID_OFF 16
54#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
55 SOF_HDA_CAP_ID_OFF)
56#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
57
58#define SOF_HDA_GTS_CAP_ID 0x1
59#define SOF_HDA_ML_CAP_ID 0x2
60
61#define SOF_HDA_PP_CAP_ID 0x3
62#define SOF_HDA_REG_PP_PPCH 0x10
63#define SOF_HDA_REG_PP_PPCTL 0x04
64#define SOF_HDA_PPCTL_PIE BIT(31)
65#define SOF_HDA_PPCTL_GPROCEN BIT(30)
66
67/* DPIB entry size: 8 Bytes = 2 DWords */
68#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
69
70#define SOF_HDA_SPIB_CAP_ID 0x4
71#define SOF_HDA_DRSM_CAP_ID 0x5
72
73#define SOF_HDA_SPIB_BASE 0x08
74#define SOF_HDA_SPIB_INTERVAL 0x08
75#define SOF_HDA_SPIB_SPIB 0x00
76#define SOF_HDA_SPIB_MAXFIFO 0x04
77
78#define SOF_HDA_PPHC_BASE 0x10
79#define SOF_HDA_PPHC_INTERVAL 0x10
80
81#define SOF_HDA_PPLC_BASE 0x10
82#define SOF_HDA_PPLC_MULTI 0x10
83#define SOF_HDA_PPLC_INTERVAL 0x10
84
85#define SOF_HDA_DRSM_BASE 0x08
86#define SOF_HDA_DRSM_INTERVAL 0x08
87
88/* Descriptor error interrupt */
89#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
90
91/* FIFO error interrupt */
92#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
93
94/* Buffer completion interrupt */
95#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
96
97#define SOF_HDA_CL_DMA_SD_INT_MASK \
98 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
99 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
100 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
101#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
102
103/* Intel HD Audio Code Loader DMA Registers */
104#define SOF_HDA_ADSP_LOADER_BASE 0x80
105#define SOF_HDA_ADSP_DPLBASE 0x70
106#define SOF_HDA_ADSP_DPUBASE 0x74
107#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
108
109/* Stream Registers */
110#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
111#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
112#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
113#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
114#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
115#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
116#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
117#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
118#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
119#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
120#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
121#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
122
123/* CL: Software Position Based FIFO Capability Registers */
124#define SOF_DSP_REG_CL_SPBFIFO \
125 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
126#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
127#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
128#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
129#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
130
131/* Stream Number */
132#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
133#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
134 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
135 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
136
137#define HDA_DSP_HDA_BAR 0
138#define HDA_DSP_PP_BAR 1
139#define HDA_DSP_SPIB_BAR 2
140#define HDA_DSP_DRSM_BAR 3
141#define HDA_DSP_BAR 4
142
143#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
144
145#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
146
147#define HDA_DSP_PANIC_OFFSET(x) \
148 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
149
150/* SRAM window 0 FW "registers" */
151#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
152#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
153/* FW and ROM share offset 4 */
154#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
155#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
156#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
157
158#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
159
160#define HDA_DSP_STREAM_RESET_TIMEOUT 300
161#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
162
163#define HDA_DSP_SPIB_ENABLE 1
164#define HDA_DSP_SPIB_DISABLE 0
165
166#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
167
168#define HDA_DSP_STACK_DUMP_SIZE 32
169
170/* ROM status/error values */
171#define HDA_DSP_ROM_STS_MASK 0xf
172#define HDA_DSP_ROM_INIT 0x1
173#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
174#define HDA_DSP_ROM_FW_FW_LOADED 0x4
175#define HDA_DSP_ROM_FW_ENTERED 0x5
176#define HDA_DSP_ROM_RFW_START 0xf
177#define HDA_DSP_ROM_CSE_ERROR 40
178#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
179#define HDA_DSP_ROM_IMR_TO_SMALL 42
180#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
181#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
182#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
183#define HDA_DSP_ROM_L2_CACHE_ERROR 46
184#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
185#define HDA_DSP_ROM_API_PTR_INVALID 50
186#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
187#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
188#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
189#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
190#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
191#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
192#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
193#define HDA_DSP_IPC_PURGE_FW 0x01004000
194
195/* various timeout values */
196#define HDA_DSP_PU_TIMEOUT 50
197#define HDA_DSP_PD_TIMEOUT 50
198#define HDA_DSP_RESET_TIMEOUT_US 50000
199#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
200#define HDA_DSP_INIT_TIMEOUT_US 500000
201#define HDA_DSP_CTRL_RESET_TIMEOUT 100
202#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
203#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
204
205#define HDA_DSP_ADSPIC_IPC 1
206#define HDA_DSP_ADSPIS_IPC 1
207
208/* Intel HD Audio General DSP Registers */
209#define HDA_DSP_GEN_BASE 0x0
210#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
211#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
212#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
213#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
214#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
215
216/* Intel HD Audio Inter-Processor Communication Registers */
217#define HDA_DSP_IPC_BASE 0x40
218#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
219#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
220#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
221#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
222#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
223
224/* HIPCI */
225#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
226#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
227
228/* HIPCIE */
229#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
230#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
231
232/* HIPCCTL */
233#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
234#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
235
236/* HIPCT */
237#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
238#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
239
240/* HIPCTE */
241#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
242
243#define HDA_DSP_ADSPIC_CL_DMA 0x2
244#define HDA_DSP_ADSPIS_CL_DMA 0x2
245
246/* Delay before scheduling D0i3 entry */
247#define BXT_D0I3_DELAY 5000
248
249#define FW_CL_STREAM_NUMBER 0x1
250
251/* ADSPCS - Audio DSP Control & Status */
252
253/*
254 * Core Reset - asserted high
255 * CRST Mask for a given core mask pattern, cm
256 */
257#define HDA_DSP_ADSPCS_CRST_SHIFT 0
258#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
259
260/*
261 * Core run/stall - when set to '1' core is stalled
262 * CSTALL Mask for a given core mask pattern, cm
263 */
264#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
265#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
266
267/*
268 * Set Power Active - when set to '1' turn cores on
269 * SPA Mask for a given core mask pattern, cm
270 */
271#define HDA_DSP_ADSPCS_SPA_SHIFT 16
272#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
273
274/*
275 * Current Power Active - power status of cores, set by hardware
276 * CPA Mask for a given core mask pattern, cm
277 */
278#define HDA_DSP_ADSPCS_CPA_SHIFT 24
279#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
280
281/* Mask for a given core index, c = 0.. number of supported cores - 1 */
282#define HDA_DSP_CORE_MASK(c) BIT(c)
283
284/*
285 * Mask for a given number of cores
286 * nc = number of supported cores
287 */
288#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
289
290/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
291#define CNL_DSP_IPC_BASE 0xc0
292#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
293#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
294#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
295#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
296#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
297#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
298
299/* HIPCI */
300#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
301#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
302
303/* HIPCIE */
304#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
305#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
306
307/* HIPCCTL */
308#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
309#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
310
311/* HIPCT */
312#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
313#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
314
315/* HIPCTDA */
316#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
317#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
318
319/* HIPCTDD */
320#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
321
322/* BDL */
323#define HDA_DSP_BDL_SIZE 4096
324#define HDA_DSP_MAX_BDL_ENTRIES \
325 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
326
327/* Number of DAIs */
328#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
329#define SOF_SKL_NUM_DAIS 14
330#else
331#define SOF_SKL_NUM_DAIS 8
332#endif
333
334/* Intel HD Audio SRAM Window 0*/
335#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
336
337/* Firmware status window */
338#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
339#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
340
341/* Host Device Memory Space */
342#define APL_SSP_BASE_OFFSET 0x2000
343#define CNL_SSP_BASE_OFFSET 0x10000
344
345/* Host Device Memory Size of a Single SSP */
346#define SSP_DEV_MEM_SIZE 0x1000
347
348/* SSP Count of the Platform */
349#define APL_SSP_COUNT 6
350#define CNL_SSP_COUNT 3
351
352/* SSP Registers */
353#define SSP_SSC1_OFFSET 0x4
354#define SSP_SET_SCLK_SLAVE BIT(25)
355#define SSP_SET_SFRM_SLAVE BIT(24)
356#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
357
358#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
359
360struct sof_intel_dsp_bdl {
361 __le32 addr_l;
362 __le32 addr_h;
363 __le32 size;
364 __le32 ioc;
365} __attribute((packed));
366
367#define SOF_HDA_PLAYBACK_STREAMS 16
368#define SOF_HDA_CAPTURE_STREAMS 16
369#define SOF_HDA_PLAYBACK 0
370#define SOF_HDA_CAPTURE 1
371
372/* represents DSP HDA controller frontend - i.e. host facing control */
373struct sof_intel_hda_dev {
374
375 struct hda_bus hbus;
376
377 /* hw config */
378 const struct sof_intel_dsp_desc *desc;
379
380 /* trace */
381 struct hdac_ext_stream *dtrace_stream;
382
383 /* if position update IPC needed */
384 u32 no_ipc_position;
385
386 /* the maximum number of streams (playback + capture) supported */
387 u32 stream_max;
388
389 int irq;
390
391 /* DMIC device */
392 struct platform_device *dmic_dev;
393};
394
395static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
396{
397 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
398
399 return &hda->hbus.core;
400}
401
402static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
403{
404 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
405
406 return &hda->hbus;
407}
408
409struct sof_intel_hda_stream {
410 struct hdac_ext_stream hda_stream;
411 struct sof_intel_stream stream;
412 int hw_params_upon_resume; /* set up hw_params upon resume */
413};
414
415#define bus_to_sof_hda(bus) \
416 container_of(bus, struct sof_intel_hda_dev, hbus.core)
417
418#define SOF_STREAM_SD_OFFSET(s) \
419 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
420 + SOF_HDA_ADSP_LOADER_BASE)
421
422/*
423 * DSP Core services.
424 */
425int hda_dsp_probe(struct snd_sof_dev *sdev);
426int hda_dsp_remove(struct snd_sof_dev *sdev);
427int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
428 unsigned int core_mask);
429int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
430 unsigned int core_mask);
431int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
432int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
433int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
434int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
435int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
436bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
437 unsigned int core_mask);
438int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
439 unsigned int core_mask);
440void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
441void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
442
443int hda_dsp_suspend(struct snd_sof_dev *sdev, int state);
444int hda_dsp_resume(struct snd_sof_dev *sdev);
445int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state);
446int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
447void hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
448void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
449void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
450void hda_ipc_dump(struct snd_sof_dev *sdev);
451
452/*
453 * DSP PCM Operations.
454 */
455int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
456 struct snd_pcm_substream *substream);
457int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
458 struct snd_pcm_substream *substream);
459int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
460 struct snd_pcm_substream *substream,
461 struct snd_pcm_hw_params *params,
462 struct sof_ipc_stream_params *ipc_params);
463int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
464 struct snd_pcm_substream *substream, int cmd);
465snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
466 struct snd_pcm_substream *substream);
467
468/*
469 * DSP Stream Operations.
470 */
471
472int hda_dsp_stream_init(struct snd_sof_dev *sdev);
473void hda_dsp_stream_free(struct snd_sof_dev *sdev);
474int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
475 struct hdac_ext_stream *stream,
476 struct snd_dma_buffer *dmab,
477 struct snd_pcm_hw_params *params);
478int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
479 struct hdac_ext_stream *stream, int cmd);
480irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
481irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
482int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
483 struct snd_dma_buffer *dmab,
484 struct hdac_stream *stream);
485
486struct hdac_ext_stream *
487 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
488int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
489int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
490 struct hdac_ext_stream *stream,
491 int enable, u32 size);
492
493void hda_ipc_msg_data(struct snd_sof_dev *sdev,
494 struct snd_pcm_substream *substream,
495 void *p, size_t sz);
496int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
497 struct snd_pcm_substream *substream,
498 const struct sof_ipc_pcm_params_reply *reply);
499
500/*
501 * DSP IPC Operations.
502 */
503int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
504 struct snd_sof_ipc_msg *msg);
505void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
506int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
507irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
508irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
509int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
510
511/*
512 * DSP Code loader.
513 */
514int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
515int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
516
517/* pre and post fw run ops */
518int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
519int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
520
521/*
522 * HDA Controller Operations.
523 */
524int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
525void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
526void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
527int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
528void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
529int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
530int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
531
532/*
533 * HDA bus operations.
534 */
535void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev,
536 const struct hdac_ext_bus_ops *ext_ops);
537
538#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
539/*
540 * HDA Codec operations.
541 */
542int hda_codec_probe_bus(struct snd_sof_dev *sdev);
543
544#endif /* CONFIG_SND_SOC_SOF_HDA */
545
546#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
547
548void hda_codec_i915_get(struct snd_sof_dev *sdev);
549void hda_codec_i915_put(struct snd_sof_dev *sdev);
550int hda_codec_i915_init(struct snd_sof_dev *sdev);
551int hda_codec_i915_exit(struct snd_sof_dev *sdev);
552
553#else
554
555static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { }
556static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { }
557static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
558static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
559
560#endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
561
562/*
563 * Trace Control.
564 */
565int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
566int hda_dsp_trace_release(struct snd_sof_dev *sdev);
567int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
568
569/* common dai driver */
570extern struct snd_soc_dai_driver skl_dai[];
571
572/*
573 * Platform Specific HW abstraction Ops.
574 */
575extern const struct snd_sof_dsp_ops sof_apl_ops;
576extern const struct snd_sof_dsp_ops sof_cnl_ops;
577extern const struct snd_sof_dsp_ops sof_skl_ops;
578
579extern const struct sof_intel_dsp_desc apl_chip_info;
580extern const struct sof_intel_dsp_desc cnl_chip_info;
581extern const struct sof_intel_dsp_desc skl_chip_info;
582
583#endif