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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * linux/mdio.h: definitions for MDIO (clause 45) transceivers
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef _UAPI__LINUX_MDIO_H__
12#define _UAPI__LINUX_MDIO_H__
13
14#include <linux/types.h>
15#include <linux/mii.h>
16
17/* MDIO Manageable Devices (MMDs). */
18#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment/
19 * Physical Medium Dependent */
20#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
21#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
22#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
23#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
24#define MDIO_MMD_TC 6 /* Transmission Convergence */
25#define MDIO_MMD_AN 7 /* Auto-Negotiation */
26#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
27#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
28#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
29
30/* Generic MDIO registers. */
31#define MDIO_CTRL1 MII_BMCR
32#define MDIO_STAT1 MII_BMSR
33#define MDIO_DEVID1 MII_PHYSID1
34#define MDIO_DEVID2 MII_PHYSID2
35#define MDIO_SPEED 4 /* Speed ability */
36#define MDIO_DEVS1 5 /* Devices in package */
37#define MDIO_DEVS2 6
38#define MDIO_CTRL2 7 /* 10G control 2 */
39#define MDIO_STAT2 8 /* 10G status 2 */
40#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
43#define MDIO_PKGID1 14 /* Package identifier */
44#define MDIO_PKGID2 15
45#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
46#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
47#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
48#define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
49#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
50#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
51#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
52#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
53
54/* Media-dependent registers. */
55#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
56#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
57#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
58 * Lanes B-D are numbered 134-136. */
59#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
60#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
61#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
62#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
63#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
64#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
65
66/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
67#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
68#define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
69#define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
70#define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
71#define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
72#define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
73
74/* Control register 1. */
75/* Enable extended speed selection */
76#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
77/* All speed selection bits */
78#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
79#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
80#define MDIO_CTRL1_LPOWER BMCR_PDOWN
81#define MDIO_CTRL1_RESET BMCR_RESET
82#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
83#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
84#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
85#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
86#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
87#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
88#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
89#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
90#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
91
92/* 10 Gb/s */
93#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
94/* 10PASS-TS/2BASE-TL */
95#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
96/* 2.5 Gb/s */
97#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
98/* 5 Gb/s */
99#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
100
101/* Status register 1. */
102#define MDIO_STAT1_LPOWERABLE 0x0002 /* Low-power ability */
103#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
104#define MDIO_STAT1_FAULT 0x0080 /* Fault */
105#define MDIO_AN_STAT1_LPABLE 0x0001 /* Link partner AN ability */
106#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
107#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
108#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
109#define MDIO_AN_STAT1_PAGE 0x0040 /* Page received */
110#define MDIO_AN_STAT1_XNP 0x0080 /* Extended next page status */
111
112/* Speed register. */
113#define MDIO_SPEED_10G 0x0001 /* 10G capable */
114#define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
115#define MDIO_PMA_SPEED_10P 0x0004 /* 10PASS-TS capable */
116#define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */
117#define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */
118#define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */
119#define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
120
121/* Device present registers. */
122#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
123#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0)
124#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
125#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
126#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
127#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
128#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
129#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
130#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
131#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
132#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
133#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
134
135/* Control register 2. */
136#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
137#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
138#define MDIO_PMA_CTRL2_10GBEW 0x0001 /* 10GBASE-EW type */
139#define MDIO_PMA_CTRL2_10GBLW 0x0002 /* 10GBASE-LW type */
140#define MDIO_PMA_CTRL2_10GBSW 0x0003 /* 10GBASE-SW type */
141#define MDIO_PMA_CTRL2_10GBLX4 0x0004 /* 10GBASE-LX4 type */
142#define MDIO_PMA_CTRL2_10GBER 0x0005 /* 10GBASE-ER type */
143#define MDIO_PMA_CTRL2_10GBLR 0x0006 /* 10GBASE-LR type */
144#define MDIO_PMA_CTRL2_10GBSR 0x0007 /* 10GBASE-SR type */
145#define MDIO_PMA_CTRL2_10GBLRM 0x0008 /* 10GBASE-LRM type */
146#define MDIO_PMA_CTRL2_10GBT 0x0009 /* 10GBASE-T type */
147#define MDIO_PMA_CTRL2_10GBKX4 0x000a /* 10GBASE-KX4 type */
148#define MDIO_PMA_CTRL2_10GBKR 0x000b /* 10GBASE-KR type */
149#define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
150#define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
151#define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
152#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
153#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
154#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
155#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
156#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
157#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
158#define MDIO_PCS_CTRL2_10GBW 0x0002 /* 10GBASE-W type */
159#define MDIO_PCS_CTRL2_10GBT 0x0003 /* 10GBASE-T type */
160
161/* Status register 2. */
162#define MDIO_STAT2_RXFAULT 0x0400 /* Receive fault */
163#define MDIO_STAT2_TXFAULT 0x0800 /* Transmit fault */
164#define MDIO_STAT2_DEVPRST 0xc000 /* Device present */
165#define MDIO_STAT2_DEVPRST_VAL 0x8000 /* Device present value */
166#define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
167#define MDIO_PMA_STAT2_10GBEW 0x0002 /* 10GBASE-EW ability */
168#define MDIO_PMA_STAT2_10GBLW 0x0004 /* 10GBASE-LW ability */
169#define MDIO_PMA_STAT2_10GBSW 0x0008 /* 10GBASE-SW ability */
170#define MDIO_PMA_STAT2_10GBLX4 0x0010 /* 10GBASE-LX4 ability */
171#define MDIO_PMA_STAT2_10GBER 0x0020 /* 10GBASE-ER ability */
172#define MDIO_PMA_STAT2_10GBLR 0x0040 /* 10GBASE-LR ability */
173#define MDIO_PMA_STAT2_10GBSR 0x0080 /* 10GBASE-SR ability */
174#define MDIO_PMD_STAT2_TXDISAB 0x0100 /* PMD TX disable ability */
175#define MDIO_PMA_STAT2_EXTABLE 0x0200 /* Extended abilities */
176#define MDIO_PMA_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
177#define MDIO_PMA_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
178#define MDIO_PCS_STAT2_10GBR 0x0001 /* 10GBASE-R capable */
179#define MDIO_PCS_STAT2_10GBX 0x0002 /* 10GBASE-X capable */
180#define MDIO_PCS_STAT2_10GBW 0x0004 /* 10GBASE-W capable */
181#define MDIO_PCS_STAT2_RXFLTABLE 0x1000 /* Receive fault ability */
182#define MDIO_PCS_STAT2_TXFLTABLE 0x2000 /* Transmit fault ability */
183
184/* Transmit disable register. */
185#define MDIO_PMD_TXDIS_GLOBAL 0x0001 /* Global PMD TX disable */
186#define MDIO_PMD_TXDIS_0 0x0002 /* PMD TX disable 0 */
187#define MDIO_PMD_TXDIS_1 0x0004 /* PMD TX disable 1 */
188#define MDIO_PMD_TXDIS_2 0x0008 /* PMD TX disable 2 */
189#define MDIO_PMD_TXDIS_3 0x0010 /* PMD TX disable 3 */
190
191/* Receive signal detect register. */
192#define MDIO_PMD_RXDET_GLOBAL 0x0001 /* Global PMD RX signal detect */
193#define MDIO_PMD_RXDET_0 0x0002 /* PMD RX signal detect 0 */
194#define MDIO_PMD_RXDET_1 0x0004 /* PMD RX signal detect 1 */
195#define MDIO_PMD_RXDET_2 0x0008 /* PMD RX signal detect 2 */
196#define MDIO_PMD_RXDET_3 0x0010 /* PMD RX signal detect 3 */
197
198/* Extended abilities register. */
199#define MDIO_PMA_EXTABLE_10GCX4 0x0001 /* 10GBASE-CX4 ability */
200#define MDIO_PMA_EXTABLE_10GBLRM 0x0002 /* 10GBASE-LRM ability */
201#define MDIO_PMA_EXTABLE_10GBT 0x0004 /* 10GBASE-T ability */
202#define MDIO_PMA_EXTABLE_10GBKX4 0x0008 /* 10GBASE-KX4 ability */
203#define MDIO_PMA_EXTABLE_10GBKR 0x0010 /* 10GBASE-KR ability */
204#define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
205#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
206#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
207#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
208#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
209
210/* PHY XGXS lane state register. */
211#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
212#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
213#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
214#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
215#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
216
217/* PMA 10GBASE-T pair swap & polarity */
218#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 /* Pair A/B uncrossed */
219#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 /* Pair C/D uncrossed */
220#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 /* Pair A polarity reversed */
221#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 /* Pair B polarity reversed */
222#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 /* Pair C polarity reversed */
223#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 /* Pair D polarity reversed */
224
225/* PMA 10GBASE-T TX power register. */
226#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 /* Short-reach mode */
227
228/* PMA 10GBASE-T SNR registers. */
229/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
230#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
231#define MDIO_PMA_10GBT_SNR_MAX 127
232
233/* PMA 10GBASE-R FEC ability register. */
234#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
235#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
236
237/* PCS 10GBASE-R/-T status register 1. */
238#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 /* Block lock attained */
239
240/* PCS 10GBASE-R/-T status register 2. */
241#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
242#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
243
244/* AN 10GBASE-T control register. */
245#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 /* Advertise 2.5GBASE-T */
246#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 /* Advertise 5GBASE-T */
247#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 /* Advertise 10GBASE-T */
248
249/* AN 10GBASE-T status register. */
250#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 /* LP is 2.5GBT capable */
251#define MDIO_AN_10GBT_STAT_LP5G 0x0040 /* LP is 5GBT capable */
252#define MDIO_AN_10GBT_STAT_LPTRR 0x0200 /* LP training reset req. */
253#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 /* LP loop timing ability */
254#define MDIO_AN_10GBT_STAT_LP10G 0x0800 /* LP is 10GBT capable */
255#define MDIO_AN_10GBT_STAT_REMOK 0x1000 /* Remote OK */
256#define MDIO_AN_10GBT_STAT_LOCOK 0x2000 /* Local OK */
257#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
258#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
259
260/* EEE Supported/Advertisement/LP Advertisement registers.
261 *
262 * EEE capability Register (3.20), Advertisement (7.60) and
263 * Link partner ability (7.61) registers have and can use the same identical
264 * bit masks.
265 */
266#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
267#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
268/* Note: the two defines above can be potentially used by the user-land
269 * and cannot remove them now.
270 * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
271 * using the previous ones (that can be considered obsolete).
272 */
273#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX /* 100TX EEE cap */
274#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T /* 1000T EEE cap */
275#define MDIO_EEE_10GT 0x0008 /* 10GT EEE cap */
276#define MDIO_EEE_1000KX 0x0010 /* 1000KX EEE cap */
277#define MDIO_EEE_10GKX4 0x0020 /* 10G KX4 EEE cap */
278#define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE cap */
279
280/* 2.5G/5G Extended abilities register. */
281#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 /* 2.5GBASET ability */
282#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 /* 5GBASET ability */
283
284/* LASI RX_ALARM control/status registers. */
285#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
286#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */
287#define MDIO_PMA_LASI_RX_PMALFLT 0x0010 /* PMA/PMD RX local fault */
288#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 /* RX optical power fault */
289#define MDIO_PMA_LASI_RX_WISLFLT 0x0200 /* WIS local fault */
290
291/* LASI TX_ALARM control/status registers. */
292#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 /* PHY XS TX local fault */
293#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 /* PCS TX local fault */
294#define MDIO_PMA_LASI_TX_PMALFLT 0x0010 /* PMA/PMD TX local fault */
295#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 /* Laser output power fault */
296#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 /* Laser temperature fault */
297#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 /* Laser bias current fault */
298
299/* LASI control/status registers. */
300#define MDIO_PMA_LASI_LSALARM 0x0001 /* LS_ALARM enable/status */
301#define MDIO_PMA_LASI_TXALARM 0x0002 /* TX_ALARM enable/status */
302#define MDIO_PMA_LASI_RXALARM 0x0004 /* RX_ALARM enable/status */
303
304/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
305
306#define MDIO_PHY_ID_C45 0x8000
307#define MDIO_PHY_ID_PRTAD 0x03e0
308#define MDIO_PHY_ID_DEVAD 0x001f
309#define MDIO_PHY_ID_C45_MASK \
310 (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
311
312static inline __u16 mdio_phy_id_c45(int prtad, int devad)
313{
314 return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
315}
316
317#endif /* _UAPI__LINUX_MDIO_H__ */