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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16
17#define MTL_MAX_RX_QUEUES 8
18#define MTL_MAX_TX_QUEUES 8
19#define STMMAC_CH_MAX 8
20
21#define STMMAC_RX_COE_NONE 0
22#define STMMAC_RX_COE_TYPE1 1
23#define STMMAC_RX_COE_TYPE2 2
24
25/* Define the macros for CSR clock range parameters to be passed by
26 * platform code.
27 * This could also be configured at run time using CPU freq framework. */
28
29/* MDC Clock Selection define*/
30#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
31#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
32#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
33#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
34#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
35#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
36
37/* MTL algorithms identifiers */
38#define MTL_TX_ALGORITHM_WRR 0x0
39#define MTL_TX_ALGORITHM_WFQ 0x1
40#define MTL_TX_ALGORITHM_DWRR 0x2
41#define MTL_TX_ALGORITHM_SP 0x3
42#define MTL_RX_ALGORITHM_SP 0x4
43#define MTL_RX_ALGORITHM_WSP 0x5
44
45/* RX/TX Queue Mode */
46#define MTL_QUEUE_AVB 0x0
47#define MTL_QUEUE_DCB 0x1
48
49/* The MDC clock could be set higher than the IEEE 802.3
50 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
51 * of value different than the above defined values. The resultant MDIO
52 * clock frequency of 12.5 MHz is applicable for the interfacing chips
53 * supporting higher MDC clocks.
54 * The MDC clock selection macros need to be defined for MDC clock rate
55 * of 12.5 MHz, corresponding to the following selection.
56 */
57#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
58#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
59#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
60#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
61#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
62#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
63#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
64#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
65
66/* AXI DMA Burst length supported */
67#define DMA_AXI_BLEN_4 (1 << 1)
68#define DMA_AXI_BLEN_8 (1 << 2)
69#define DMA_AXI_BLEN_16 (1 << 3)
70#define DMA_AXI_BLEN_32 (1 << 4)
71#define DMA_AXI_BLEN_64 (1 << 5)
72#define DMA_AXI_BLEN_128 (1 << 6)
73#define DMA_AXI_BLEN_256 (1 << 7)
74#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
75 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
76 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
77
78/* Platfrom data for platform device structure's platform_data field */
79
80struct stmmac_mdio_bus_data {
81 int (*phy_reset)(void *priv);
82 unsigned int phy_mask;
83 int *irqs;
84 int probed_phy_irq;
85#ifdef CONFIG_OF
86 int reset_gpio, active_low;
87 u32 delays[3];
88#endif
89};
90
91struct stmmac_dma_cfg {
92 int pbl;
93 int txpbl;
94 int rxpbl;
95 bool pblx8;
96 int fixed_burst;
97 int mixed_burst;
98 bool aal;
99};
100
101#define AXI_BLEN 7
102struct stmmac_axi {
103 bool axi_lpi_en;
104 bool axi_xit_frm;
105 u32 axi_wr_osr_lmt;
106 u32 axi_rd_osr_lmt;
107 bool axi_kbbe;
108 u32 axi_blen[AXI_BLEN];
109 bool axi_fb;
110 bool axi_mb;
111 bool axi_rb;
112};
113
114struct stmmac_rxq_cfg {
115 u8 mode_to_use;
116 u32 chan;
117 u8 pkt_route;
118 bool use_prio;
119 u32 prio;
120};
121
122struct stmmac_txq_cfg {
123 u32 weight;
124 u8 mode_to_use;
125 /* Credit Base Shaper parameters */
126 u32 send_slope;
127 u32 idle_slope;
128 u32 high_credit;
129 u32 low_credit;
130 bool use_prio;
131 u32 prio;
132};
133
134struct plat_stmmacenet_data {
135 int bus_id;
136 int phy_addr;
137 int interface;
138 struct stmmac_mdio_bus_data *mdio_bus_data;
139 struct device_node *phy_node;
140 struct device_node *mdio_node;
141 struct stmmac_dma_cfg *dma_cfg;
142 int clk_csr;
143 int has_gmac;
144 int enh_desc;
145 int tx_coe;
146 int rx_coe;
147 int bugged_jumbo;
148 int pmt;
149 int force_sf_dma_mode;
150 int force_thresh_dma_mode;
151 int riwt_off;
152 int max_speed;
153 int maxmtu;
154 int multicast_filter_bins;
155 int unicast_filter_entries;
156 int tx_fifo_size;
157 int rx_fifo_size;
158 u32 rx_queues_to_use;
159 u32 tx_queues_to_use;
160 u8 rx_sched_algorithm;
161 u8 tx_sched_algorithm;
162 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
163 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
164 void (*fix_mac_speed)(void *priv, unsigned int speed);
165 int (*init)(struct platform_device *pdev, void *priv);
166 void (*exit)(struct platform_device *pdev, void *priv);
167 struct mac_device_info *(*setup)(void *priv);
168 void *bsp_priv;
169 struct clk *stmmac_clk;
170 struct clk *pclk;
171 struct clk *clk_ptp_ref;
172 unsigned int clk_ptp_rate;
173 unsigned int clk_ref_rate;
174 struct reset_control *stmmac_rst;
175 struct stmmac_axi *axi;
176 int has_gmac4;
177 bool has_sun8i;
178 bool tso_en;
179 int mac_port_sel_speed;
180 bool en_tx_lpi_clockgating;
181 int has_xgmac;
182};
183#endif