tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 *
6 */
7
8#include <dt-bindings/clock/imx6sll-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include "imx6sll-pinfunc.h"
12
13/ {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 mmc0 = &usdhc1;
28 mmc1 = &usdhc2;
29 mmc2 = &usdhc3;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 spi0 = &ecspi1;
36 spi1 = &ecspi2;
37 spi3 = &ecspi3;
38 spi4 = &ecspi4;
39 usbphy0 = &usbphy1;
40 usbphy1 = &usbphy2;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 compatible = "arm,cortex-a9";
49 device_type = "cpu";
50 reg = <0>;
51 next-level-cache = <&L2>;
52 operating-points = <
53 /* kHz uV */
54 996000 1275000
55 792000 1175000
56 396000 1075000
57 198000 975000
58 >;
59 fsl,soc-operating-points = <
60 /* ARM kHz SOC-PU uV */
61 996000 1175000
62 792000 1175000
63 396000 1175000
64 198000 1175000
65 >;
66 clock-latency = <61036>; /* two CLK32 periods */
67 #cooling-cells = <2>;
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
74 "pll1_sw", "pll1_sys";
75 };
76 };
77
78 intc: interrupt-controller@a01000 {
79 compatible = "arm,cortex-a9-gic";
80 #interrupt-cells = <3>;
81 interrupt-controller;
82 reg = <0x00a01000 0x1000>,
83 <0x00a00100 0x100>;
84 interrupt-parent = <&intc>;
85 };
86
87 ckil: clock-ckil {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <32768>;
91 clock-output-names = "ckil";
92 };
93
94 osc: clock-osc-24m {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <24000000>;
98 clock-output-names = "osc";
99 };
100
101 ipp_di0: clock-ipp-di0 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <0>;
105 clock-output-names = "ipp_di0";
106 };
107
108 ipp_di1: clock-ipp-di1 {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <0>;
112 clock-output-names = "ipp_di1";
113 };
114
115 tempmon: temperature-sensor {
116 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
117 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
118 interrupt-parent = <&gpc>;
119 fsl,tempmon = <&anatop>;
120 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
121 nvmem-cell-names = "calib", "temp_grade";
122 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
123 };
124
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 interrupt-parent = <&gpc>;
130 ranges;
131
132 ocram: sram@900000 {
133 compatible = "mmio-sram";
134 reg = <0x00900000 0x20000>;
135 };
136
137 L2: l2-cache@a02000 {
138 compatible = "arm,pl310-cache";
139 reg = <0x00a02000 0x1000>;
140 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
141 cache-unified;
142 cache-level = <2>;
143 arm,tag-latency = <4 2 3>;
144 arm,data-latency = <4 2 3>;
145 };
146
147 aips1: aips-bus@2000000 {
148 compatible = "fsl,aips-bus", "simple-bus";
149 #address-cells = <1>;
150 #size-cells = <1>;
151 reg = <0x02000000 0x100000>;
152 ranges;
153
154 spba: spba-bus@2000000 {
155 compatible = "fsl,spba-bus", "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 reg = <0x02000000 0x40000>;
159 ranges;
160
161 spdif: spdif@2004000 {
162 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
163 reg = <0x02004000 0x4000>;
164 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
165 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
166 dma-names = "rx", "tx";
167 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
168 <&clks IMX6SLL_CLK_OSC>,
169 <&clks IMX6SLL_CLK_SPDIF>,
170 <&clks IMX6SLL_CLK_DUMMY>,
171 <&clks IMX6SLL_CLK_DUMMY>,
172 <&clks IMX6SLL_CLK_DUMMY>,
173 <&clks IMX6SLL_CLK_IPG>,
174 <&clks IMX6SLL_CLK_DUMMY>,
175 <&clks IMX6SLL_CLK_DUMMY>,
176 <&clks IMX6SLL_CLK_SPBA>;
177 clock-names = "core", "rxtx0",
178 "rxtx1", "rxtx2",
179 "rxtx3", "rxtx4",
180 "rxtx5", "rxtx6",
181 "rxtx7", "dma";
182 status = "disabled";
183 };
184
185 ecspi1: spi@2008000 {
186 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02008000 0x4000>;
188 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
189 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
190 dma-names = "rx", "tx";
191 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
192 <&clks IMX6SLL_CLK_ECSPI1>;
193 clock-names = "ipg", "per";
194 status = "disabled";
195 };
196
197 ecspi2: spi@200c000 {
198 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
199 reg = <0x0200c000 0x4000>;
200 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
201 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
202 dma-names = "rx", "tx";
203 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
204 <&clks IMX6SLL_CLK_ECSPI2>;
205 clock-names = "ipg", "per";
206 status = "disabled";
207 };
208
209 ecspi3: spi@2010000 {
210 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
211 reg = <0x02010000 0x4000>;
212 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
213 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
214 dma-names = "rx", "tx";
215 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
216 <&clks IMX6SLL_CLK_ECSPI3>;
217 clock-names = "ipg", "per";
218 status = "disabled";
219 };
220
221 ecspi4: spi@2014000 {
222 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
223 reg = <0x02014000 0x4000>;
224 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
225 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
226 dma-names = "rx", "tx";
227 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
228 <&clks IMX6SLL_CLK_ECSPI4>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232
233 uart4: serial@2018000 {
234 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
235 "fsl,imx21-uart";
236 reg = <0x02018000 0x4000>;
237 interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
238 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
239 dma-names = "rx", "tx";
240 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
241 <&clks IMX6SLL_CLK_UART4_SERIAL>;
242 clock-names = "ipg", "per";
243 status = "disabled";
244 };
245
246 uart1: serial@2020000 {
247 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
248 "fsl,imx21-uart";
249 reg = <0x02020000 0x4000>;
250 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
251 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
252 dma-names = "rx", "tx";
253 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
254 <&clks IMX6SLL_CLK_UART1_SERIAL>;
255 clock-names = "ipg", "per";
256 status = "disabled";
257 };
258
259 uart2: serial@2024000 {
260 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
261 "fsl,imx21-uart";
262 reg = <0x02024000 0x4000>;
263 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
264 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
265 dma-names = "rx", "tx";
266 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
267 <&clks IMX6SLL_CLK_UART2_SERIAL>;
268 clock-names = "ipg", "per";
269 status = "disabled";
270 };
271
272 ssi1: ssi-controller@2028000 {
273 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
274 reg = <0x02028000 0x4000>;
275 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
276 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
277 dma-names = "rx", "tx";
278 fsl,fifo-depth = <15>;
279 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
280 <&clks IMX6SLL_CLK_SSI1>;
281 clock-names = "ipg", "baud";
282 status = "disabled";
283 };
284
285 ssi2: ssi-controller@202c000 {
286 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
287 reg = <0x0202c000 0x4000>;
288 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
289 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
290 dma-names = "rx", "tx";
291 fsl,fifo-depth = <15>;
292 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
293 <&clks IMX6SLL_CLK_SSI2>;
294 clock-names = "ipg", "baud";
295 status = "disabled";
296 };
297
298 ssi3: ssi-controller@2030000 {
299 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
300 reg = <0x02030000 0x4000>;
301 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
302 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
303 dma-names = "rx", "tx";
304 fsl,fifo-depth = <15>;
305 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
306 <&clks IMX6SLL_CLK_SSI3>;
307 clock-names = "ipg", "baud";
308 status = "disabled";
309 };
310
311 uart3: serial@2034000 {
312 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
313 "fsl,imx21-uart";
314 reg = <0x02034000 0x4000>;
315 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
316 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
317 dma-name = "rx", "tx";
318 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
319 <&clks IMX6SLL_CLK_UART3_SERIAL>;
320 clock-names = "ipg", "per";
321 status = "disabled";
322 };
323 };
324
325 pwm1: pwm@2080000 {
326 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
327 reg = <0x02080000 0x4000>;
328 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks IMX6SLL_CLK_PWM1>,
330 <&clks IMX6SLL_CLK_PWM1>;
331 clock-names = "ipg", "per";
332 #pwm-cells = <2>;
333 };
334
335 pwm2: pwm@2084000 {
336 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
337 reg = <0x02084000 0x4000>;
338 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&clks IMX6SLL_CLK_PWM2>,
340 <&clks IMX6SLL_CLK_PWM2>;
341 clock-names = "ipg", "per";
342 #pwm-cells = <2>;
343 };
344
345 pwm3: pwm@2088000 {
346 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
347 reg = <0x02088000 0x4000>;
348 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks IMX6SLL_CLK_PWM3>,
350 <&clks IMX6SLL_CLK_PWM3>;
351 clock-names = "ipg", "per";
352 #pwm-cells = <2>;
353 };
354
355 pwm4: pwm@208c000 {
356 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
357 reg = <0x0208c000 0x4000>;
358 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clks IMX6SLL_CLK_PWM4>,
360 <&clks IMX6SLL_CLK_PWM4>;
361 clock-names = "ipg", "per";
362 #pwm-cells = <2>;
363 };
364
365 gpt1: timer@2098000 {
366 compatible = "fsl,imx6sl-gpt";
367 reg = <0x02098000 0x4000>;
368 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
370 <&clks IMX6SLL_CLK_GPT_SERIAL>;
371 clock-names = "ipg", "per";
372 };
373
374 gpio1: gpio@209c000 {
375 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
376 reg = <0x0209c000 0x4000>;
377 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clks IMX6SLL_CLK_GPIO1>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
385 };
386
387 gpio2: gpio@20a0000 {
388 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
389 reg = <0x020a0000 0x4000>;
390 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clks IMX6SLL_CLK_GPIO2>;
393 gpio-controller;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 gpio-ranges = <&iomuxc 0 50 32>;
398 };
399
400 gpio3: gpio@20a4000 {
401 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
402 reg = <0x020a4000 0x4000>;
403 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6SLL_CLK_GPIO3>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
411 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
412 <&iomuxc 21 6 11>;
413 };
414
415 gpio4: gpio@20a8000 {
416 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
417 reg = <0x020a8000 0x4000>;
418 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SLL_CLK_GPIO4>;
421 gpio-controller;
422 #gpio-cells = <2>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
426 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
427 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
428 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
429 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
430 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
431 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
432 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
433 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
434 };
435
436 gpio5: gpio@20ac000 {
437 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
438 reg = <0x020ac000 0x4000>;
439 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX6SLL_CLK_GPIO5>;
442 gpio-controller;
443 #gpio-cells = <2>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
446 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
447 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
448 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
449 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
450 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
451 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
452 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
453 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
454 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
455 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
456 <&iomuxc 21 137 1>;
457 };
458
459 gpio6: gpio@20b0000 {
460 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
461 reg = <0x020b0000 0x4000>;
462 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clks IMX6SLL_CLK_GPIO6>;
465 gpio-controller;
466 #gpio-cells = <2>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 };
470
471 kpp: keypad@20b8000 {
472 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
473 reg = <0x020b8000 0x4000>;
474 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX6SLL_CLK_KPP>;
476 status = "disabled";
477 };
478
479 wdog1: watchdog@20bc000 {
480 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
481 reg = <0x020bc000 0x4000>;
482 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX6SLL_CLK_WDOG1>;
484 };
485
486 wdog2: watchdog@20c0000 {
487 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
488 reg = <0x020c0000 0x4000>;
489 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&clks IMX6SLL_CLK_WDOG2>;
491 status = "disabled";
492 };
493
494 clks: clock-controller@20c4000 {
495 compatible = "fsl,imx6sll-ccm";
496 reg = <0x020c4000 0x4000>;
497 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
499 #clock-cells = <1>;
500 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
501 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
502
503 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
504 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
505 };
506
507 anatop: anatop@20c8000 {
508 compatible = "fsl,imx6sll-anatop",
509 "fsl,imx6q-anatop",
510 "syscon", "simple-bus";
511 reg = <0x020c8000 0x4000>;
512 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517
518 reg_3p0: regulator-3p0@20c8120 {
519 compatible = "fsl,anatop-regulator";
520 reg = <0x20c8120>;
521 regulator-name = "vdd3p0";
522 regulator-min-microvolt = <2625000>;
523 regulator-max-microvolt = <3400000>;
524 anatop-reg-offset = <0x120>;
525 anatop-vol-bit-shift = <8>;
526 anatop-vol-bit-width = <5>;
527 anatop-min-bit-val = <0>;
528 anatop-min-voltage = <2625000>;
529 anatop-max-voltage = <3400000>;
530 anatop-enable-bit = <0>;
531 };
532 };
533
534 usbphy1: usb-phy@20c9000 {
535 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
536 "fsl,imx23-usbphy";
537 reg = <0x020c9000 0x1000>;
538 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
540 phy-3p0-supply = <®_3p0>;
541 fsl,anatop = <&anatop>;
542 };
543
544 usbphy2: usb-phy@20ca000 {
545 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
546 "fsl,imx23-usbphy";
547 reg = <0x020ca000 0x1000>;
548 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
550 phy-reg_3p0-supply = <®_3p0>;
551 fsl,anatop = <&anatop>;
552 };
553
554 snvs: snvs@20cc000 {
555 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
556 reg = <0x020cc000 0x4000>;
557
558 snvs_rtc: snvs-rtc-lp {
559 compatible = "fsl,sec-v4.0-mon-rtc-lp";
560 regmap = <&snvs>;
561 offset = <0x34>;
562 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
564 };
565
566 snvs_poweroff: snvs-poweroff {
567 compatible = "syscon-poweroff";
568 regmap = <&snvs>;
569 offset = <0x38>;
570 mask = <0x61>;
571 };
572
573 snvs_pwrkey: snvs-powerkey {
574 compatible = "fsl,sec-v4.0-pwrkey";
575 regmap = <&snvs>;
576 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
577 linux,keycode = <KEY_POWER>;
578 wakeup-source;
579 };
580 };
581
582 src: reset-controller@20d8000 {
583 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
584 reg = <0x020d8000 0x4000>;
585 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
587 #reset-cells = <1>;
588 };
589
590 gpc: interrupt-controller@20dc000 {
591 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
592 reg = <0x020dc000 0x4000>;
593 interrupt-controller;
594 #interrupt-cells = <3>;
595 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-parent = <&intc>;
597 };
598
599 iomuxc: pinctrl@20e0000 {
600 compatible = "fsl,imx6sll-iomuxc";
601 reg = <0x020e0000 0x4000>;
602 };
603
604 gpr: iomuxc-gpr@20e4000 {
605 compatible = "fsl,imx6sll-iomuxc-gpr",
606 "fsl,imx6q-iomuxc-gpr", "syscon";
607 reg = <0x020e4000 0x4000>;
608 };
609
610 csi: csi@20e8000 {
611 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
612 reg = <0x020e8000 0x4000>;
613 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clks IMX6SLL_CLK_DUMMY>,
615 <&clks IMX6SLL_CLK_CSI>,
616 <&clks IMX6SLL_CLK_DUMMY>;
617 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
618 status = "disabled";
619 };
620
621 sdma: dma-controller@20ec000 {
622 compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
623 reg = <0x020ec000 0x4000>;
624 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks IMX6SLL_CLK_IPG>,
626 <&clks IMX6SLL_CLK_SDMA>;
627 clock-names = "ipg", "ahb";
628 #dma-cells = <3>;
629 iram = <&ocram>;
630 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
631 };
632
633 lcdif: lcd-controller@20f8000 {
634 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
635 reg = <0x020f8000 0x4000>;
636 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
638 <&clks IMX6SLL_CLK_LCDIF_APB>,
639 <&clks IMX6SLL_CLK_DUMMY>;
640 clock-names = "pix", "axi", "disp_axi";
641 status = "disabled";
642 };
643
644 dcp: dcp@20fc000 {
645 compatible = "fsl,imx28-dcp";
646 reg = <0x020fc000 0x4000>;
647 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clks IMX6SLL_CLK_DCP>;
651 clock-names = "dcp";
652 };
653 };
654
655 aips2: aips-bus@2100000 {
656 compatible = "fsl,aips-bus", "simple-bus";
657 #address-cells = <1>;
658 #size-cells = <1>;
659 reg = <0x02100000 0x100000>;
660 ranges;
661
662 usbotg1: usb@2184000 {
663 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
664 "fsl,imx27-usb";
665 reg = <0x02184000 0x200>;
666 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&clks IMX6SLL_CLK_USBOH3>;
668 fsl,usbphy = <&usbphy1>;
669 fsl,usbmisc = <&usbmisc 0>;
670 fsl,anatop = <&anatop>;
671 ahb-burst-config = <0x0>;
672 tx-burst-size-dword = <0x10>;
673 rx-burst-size-dword = <0x10>;
674 status = "disabled";
675 };
676
677 usbotg2: usb@2184200 {
678 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
679 "fsl,imx27-usb";
680 reg = <0x02184200 0x200>;
681 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clks IMX6SLL_CLK_USBOH3>;
683 fsl,usbphy = <&usbphy2>;
684 fsl,usbmisc = <&usbmisc 1>;
685 ahb-burst-config = <0x0>;
686 tx-burst-size-dword = <0x10>;
687 rx-burst-size-dword = <0x10>;
688 status = "disabled";
689 };
690
691 usbmisc: usbmisc@2184800 {
692 #index-cells = <1>;
693 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
694 "fsl,imx6q-usbmisc";
695 reg = <0x02184800 0x200>;
696 };
697
698 usdhc1: mmc@2190000 {
699 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
700 reg = <0x02190000 0x4000>;
701 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&clks IMX6SLL_CLK_USDHC1>,
703 <&clks IMX6SLL_CLK_USDHC1>,
704 <&clks IMX6SLL_CLK_USDHC1>;
705 clock-names = "ipg", "ahb", "per";
706 bus-width = <4>;
707 fsl,tuning-step = <2>;
708 fsl,tuning-start-tap = <20>;
709 status = "disabled";
710 };
711
712 usdhc2: mmc@2194000 {
713 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
714 reg = <0x02194000 0x4000>;
715 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&clks IMX6SLL_CLK_USDHC2>,
717 <&clks IMX6SLL_CLK_USDHC2>,
718 <&clks IMX6SLL_CLK_USDHC2>;
719 clock-names = "ipg", "ahb", "per";
720 bus-width = <4>;
721 fsl,tuning-step = <2>;
722 fsl,tuning-start-tap = <20>;
723 status = "disabled";
724 };
725
726 usdhc3: mmc@2198000 {
727 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
728 reg = <0x02198000 0x4000>;
729 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clks IMX6SLL_CLK_USDHC3>,
731 <&clks IMX6SLL_CLK_USDHC3>,
732 <&clks IMX6SLL_CLK_USDHC3>;
733 clock-names = "ipg", "ahb", "per";
734 bus-width = <4>;
735 fsl,tuning-step = <2>;
736 fsl,tuning-start-tap = <20>;
737 status = "disabled";
738 };
739
740 i2c1: i2c@21a0000 {
741 #address-cells = <1>;
742 #size-cells = <0>;
743 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
744 reg = <0x021a0000 0x4000>;
745 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX6SLL_CLK_I2C1>;
747 status = "disabled";
748 };
749
750 i2c2: i2c@21a4000 {
751 #address-cells = <1>;
752 #size-cells = <0>;
753 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
754 reg = <0x021a4000 0x4000>;
755 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX6SLL_CLK_I2C2>;
757 status = "disabled";
758 };
759
760 i2c3: i2c@21a8000 {
761 #address-cells = <1>;
762 #size-cells = <0>;
763 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
764 reg = <0x021a8000 0x4000>;
765 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clks IMX6SLL_CLK_I2C3>;
767 status = "disabled";
768 };
769
770 mmdc: memory-controller@21b0000 {
771 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
772 reg = <0x021b0000 0x4000>;
773 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
774 };
775
776 ocotp: ocotp-ctrl@21bc000 {
777 #address-cells = <1>;
778 #size-cells = <1>;
779 compatible = "fsl,imx6sll-ocotp", "syscon";
780 reg = <0x021bc000 0x4000>;
781 clocks = <&clks IMX6SLL_CLK_OCOTP>;
782
783 tempmon_calib: calib@38 {
784 reg = <0x38 4>;
785 };
786
787 tempmon_temp_grade: temp-grade@20 {
788 reg = <0x20 4>;
789 };
790 };
791
792 audmux: audmux@21d8000 {
793 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
794 reg = <0x021d8000 0x4000>;
795 status = "disabled";
796 };
797
798 uart5: serial@21f4000 {
799 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
800 "fsl,imx21-uart";
801 reg = <0x021f4000 0x4000>;
802 interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
803 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
804 dma-names = "rx", "tx";
805 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
806 <&clks IMX6SLL_CLK_UART5_SERIAL>;
807 clock-names = "ipg", "per";
808 status = "disabled";
809 };
810 };
811 };
812};