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Linux kernel mirror (for testing)
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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __AMDGPU_DM_H__
27#define __AMDGPU_DM_H__
28
29#include <drm/drmP.h>
30#include <drm/drm_atomic.h>
31
32/*
33 * This file contains the definition for amdgpu_display_manager
34 * and its API for amdgpu driver's use.
35 * This component provides all the display related functionality
36 * and this is the only component that calls DAL API.
37 * The API contained here intended for amdgpu driver use.
38 * The API that is called directly from KMS framework is located
39 * in amdgpu_dm_kms.h file
40 */
41
42#define AMDGPU_DM_MAX_DISPLAY_INDEX 31
43/*
44#include "include/amdgpu_dal_power_if.h"
45#include "amdgpu_dm_irq.h"
46*/
47
48#include "irq_types.h"
49#include "signal_types.h"
50
51/* Forward declarations */
52struct amdgpu_device;
53struct drm_device;
54struct amdgpu_dm_irq_handler_data;
55struct dc;
56
57struct common_irq_params {
58 struct amdgpu_device *adev;
59 enum dc_irq_source irq_src;
60};
61
62/**
63 * struct irq_list_head - Linked-list for low context IRQ handlers.
64 *
65 * @head: The list_head within &struct handler_data
66 * @work: A work_struct containing the deferred handler work
67 */
68struct irq_list_head {
69 struct list_head head;
70 /* In case this interrupt needs post-processing, 'work' will be queued*/
71 struct work_struct work;
72};
73
74/**
75 * struct dm_compressor_info - Buffer info used by frame buffer compression
76 * @cpu_addr: MMIO cpu addr
77 * @bo_ptr: Pointer to the buffer object
78 * @gpu_addr: MMIO gpu addr
79 */
80struct dm_comressor_info {
81 void *cpu_addr;
82 struct amdgpu_bo *bo_ptr;
83 uint64_t gpu_addr;
84};
85
86/**
87 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI
88 * @min_input_signal: minimum possible input in range 0-255
89 * @max_input_signal: maximum possible input in range 0-255
90 * @caps_valid: true if these values are from the ACPI interface
91 */
92struct amdgpu_dm_backlight_caps {
93 int min_input_signal;
94 int max_input_signal;
95 bool caps_valid;
96};
97
98/**
99 * struct amdgpu_display_manager - Central amdgpu display manager device
100 *
101 * @dc: Display Core control structure
102 * @adev: AMDGPU base driver structure
103 * @ddev: DRM base driver structure
104 * @display_indexes_num: Max number of display streams supported
105 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
106 * @backlight_dev: Backlight control device
107 * @cached_state: Caches device atomic state for suspend/resume
108 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
109 */
110struct amdgpu_display_manager {
111
112 struct dc *dc;
113
114 /**
115 * @cgs_device:
116 *
117 * The Common Graphics Services device. It provides an interface for
118 * accessing registers.
119 */
120 struct cgs_device *cgs_device;
121
122 struct amdgpu_device *adev;
123 struct drm_device *ddev;
124 u16 display_indexes_num;
125
126 /**
127 * @atomic_obj
128 *
129 * In combination with &dm_atomic_state it helps manage
130 * global atomic state that doesn't map cleanly into existing
131 * drm resources, like &dc_context.
132 */
133 struct drm_private_obj atomic_obj;
134
135 /**
136 * @dc_lock:
137 *
138 * Guards access to DC functions that can issue register write
139 * sequences.
140 */
141 struct mutex dc_lock;
142
143 /**
144 * @irq_handler_list_low_tab:
145 *
146 * Low priority IRQ handler table.
147 *
148 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
149 * source. Low priority IRQ handlers are deferred to a workqueue to be
150 * processed. Hence, they can sleep.
151 *
152 * Note that handlers are called in the same order as they were
153 * registered (FIFO).
154 */
155 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
156
157 /**
158 * @irq_handler_list_high_tab:
159 *
160 * High priority IRQ handler table.
161 *
162 * It is a n*m table, same as &irq_handler_list_low_tab. However,
163 * handlers in this table are not deferred and are called immediately.
164 */
165 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
166
167 /**
168 * @pflip_params:
169 *
170 * Page flip IRQ parameters, passed to registered handlers when
171 * triggered.
172 */
173 struct common_irq_params
174 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
175
176 /**
177 * @vblank_params:
178 *
179 * Vertical blanking IRQ parameters, passed to registered handlers when
180 * triggered.
181 */
182 struct common_irq_params
183 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
184
185 /**
186 * @vupdate_params:
187 *
188 * Vertical update IRQ parameters, passed to registered handlers when
189 * triggered.
190 */
191 struct common_irq_params
192 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
193
194 spinlock_t irq_handler_list_table_lock;
195
196 struct backlight_device *backlight_dev;
197
198 const struct dc_link *backlight_link;
199 struct amdgpu_dm_backlight_caps backlight_caps;
200
201 struct mod_freesync *freesync_module;
202
203 struct drm_atomic_state *cached_state;
204
205 struct dm_comressor_info compressor;
206
207 const struct firmware *fw_dmcu;
208 uint32_t dmcu_fw_version;
209};
210
211struct amdgpu_dm_connector {
212
213 struct drm_connector base;
214 uint32_t connector_id;
215
216 /* we need to mind the EDID between detect
217 and get modes due to analog/digital/tvencoder */
218 struct edid *edid;
219
220 /* shared with amdgpu */
221 struct amdgpu_hpd hpd;
222
223 /* number of modes generated from EDID at 'dc_sink' */
224 int num_modes;
225
226 /* The 'old' sink - before an HPD.
227 * The 'current' sink is in dc_link->sink. */
228 struct dc_sink *dc_sink;
229 struct dc_link *dc_link;
230 struct dc_sink *dc_em_sink;
231
232 /* DM only */
233 struct drm_dp_mst_topology_mgr mst_mgr;
234 struct amdgpu_dm_dp_aux dm_dp_aux;
235 struct drm_dp_mst_port *port;
236 struct amdgpu_dm_connector *mst_port;
237 struct amdgpu_encoder *mst_encoder;
238
239 /* TODO see if we can merge with ddc_bus or make a dm_connector */
240 struct amdgpu_i2c_adapter *i2c;
241
242 /* Monitor range limits */
243 int min_vfreq ;
244 int max_vfreq ;
245 int pixel_clock_mhz;
246
247 struct mutex hpd_lock;
248
249 bool fake_enable;
250#ifdef CONFIG_DEBUG_FS
251 uint32_t debugfs_dpcd_address;
252 uint32_t debugfs_dpcd_size;
253#endif
254};
255
256#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
257
258extern const struct amdgpu_ip_block_version dm_ip_block;
259
260struct amdgpu_framebuffer;
261struct amdgpu_display_manager;
262struct dc_validation_set;
263struct dc_plane_state;
264
265struct dm_plane_state {
266 struct drm_plane_state base;
267 struct dc_plane_state *dc_state;
268};
269
270struct dm_crtc_state {
271 struct drm_crtc_state base;
272 struct dc_stream_state *stream;
273
274 int active_planes;
275 bool interrupts_enabled;
276
277 int crc_skip_count;
278 bool crc_enabled;
279
280 bool freesync_timing_changed;
281 bool freesync_vrr_info_changed;
282
283 bool vrr_supported;
284 struct mod_freesync_config freesync_config;
285 struct mod_vrr_params vrr_params;
286 struct dc_info_packet vrr_infopacket;
287
288 int abm_level;
289};
290
291#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
292
293struct dm_atomic_state {
294 struct drm_private_state base;
295
296 struct dc_state *context;
297};
298
299#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
300
301struct dm_connector_state {
302 struct drm_connector_state base;
303
304 enum amdgpu_rmx_type scaling;
305 uint8_t underscan_vborder;
306 uint8_t underscan_hborder;
307 uint8_t max_bpc;
308 bool underscan_enable;
309 bool freesync_capable;
310 uint8_t abm_level;
311};
312
313#define to_dm_connector_state(x)\
314 container_of((x), struct dm_connector_state, base)
315
316void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
317struct drm_connector_state *
318amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
319int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
320 struct drm_connector_state *state,
321 struct drm_property *property,
322 uint64_t val);
323
324int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
325 const struct drm_connector_state *state,
326 struct drm_property *property,
327 uint64_t *val);
328
329int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
330
331void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
332 struct amdgpu_dm_connector *aconnector,
333 int connector_type,
334 struct dc_link *link,
335 int link_index);
336
337enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
338 struct drm_display_mode *mode);
339
340void dm_restore_drm_connector_state(struct drm_device *dev,
341 struct drm_connector *connector);
342
343void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
344 struct edid *edid);
345
346/* amdgpu_dm_crc.c */
347#ifdef CONFIG_DEBUG_FS
348int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
349int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
350 const char *src_name,
351 size_t *values_cnt);
352void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
353#else
354#define amdgpu_dm_crtc_set_crc_source NULL
355#define amdgpu_dm_crtc_verify_crc_source NULL
356#define amdgpu_dm_crtc_handle_crc_irq(x)
357#endif
358
359#define MAX_COLOR_LUT_ENTRIES 4096
360/* Legacy gamm LUT users such as X doesn't like large LUT sizes */
361#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
362
363void amdgpu_dm_init_color_mod(void);
364int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
365 struct dc_plane_state *dc_plane_state);
366void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
367int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
368
369extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
370
371#endif /* __AMDGPU_DM_H__ */