Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4#
5
6config ARC
7 def_bool y
8 select ARC_TIMERS
9 select ARCH_HAS_DMA_COHERENT_TO_PFN
10 select ARCH_HAS_PTE_SPECIAL
11 select ARCH_HAS_SETUP_DMA_OPS
12 select ARCH_HAS_SYNC_DMA_FOR_CPU
13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
14 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
15 select ARCH_32BIT_OFF_T
16 select BUILDTIME_EXTABLE_SORT
17 select CLONE_BACKWARDS
18 select COMMON_CLK
19 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
20 select GENERIC_CLOCKEVENTS
21 select GENERIC_FIND_FIRST_BIT
22 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
23 select GENERIC_IRQ_SHOW
24 select GENERIC_PCI_IOMAP
25 select GENERIC_PENDING_IRQ if SMP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select HAVE_ARCH_KGDB
29 select HAVE_ARCH_TRACEHOOK
30 select HAVE_DEBUG_STACKOVERFLOW
31 select HAVE_FUTEX_CMPXCHG if FUTEX
32 select HAVE_IOREMAP_PROT
33 select HAVE_KERNEL_GZIP
34 select HAVE_KERNEL_LZMA
35 select HAVE_KPROBES
36 select HAVE_KRETPROBES
37 select HAVE_MOD_ARCH_SPECIFIC
38 select HAVE_OPROFILE
39 select HAVE_PERF_EVENTS
40 select HANDLE_DOMAIN_IRQ
41 select IRQ_DOMAIN
42 select MODULES_USE_ELF_RELA
43 select OF
44 select OF_EARLY_FLATTREE
45 select PCI_SYSCALL if PCI
46 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
47
48config ARCH_HAS_CACHE_LINE_SIZE
49 def_bool y
50
51config TRACE_IRQFLAGS_SUPPORT
52 def_bool y
53
54config LOCKDEP_SUPPORT
55 def_bool y
56
57config SCHED_OMIT_FRAME_POINTER
58 def_bool y
59
60config GENERIC_CSUM
61 def_bool y
62
63config ARCH_DISCONTIGMEM_ENABLE
64 def_bool n
65
66config ARCH_FLATMEM_ENABLE
67 def_bool y
68
69config MMU
70 def_bool y
71
72config NO_IOPORT_MAP
73 def_bool y
74
75config GENERIC_CALIBRATE_DELAY
76 def_bool y
77
78config GENERIC_HWEIGHT
79 def_bool y
80
81config STACKTRACE_SUPPORT
82 def_bool y
83 select STACKTRACE
84
85config HAVE_ARCH_TRANSPARENT_HUGEPAGE
86 def_bool y
87 depends on ARC_MMU_V4
88
89menu "ARC Architecture Configuration"
90
91menu "ARC Platform/SoC/Board"
92
93source "arch/arc/plat-tb10x/Kconfig"
94source "arch/arc/plat-axs10x/Kconfig"
95#New platform adds here
96source "arch/arc/plat-eznps/Kconfig"
97source "arch/arc/plat-hsdk/Kconfig"
98
99endmenu
100
101choice
102 prompt "ARC Instruction Set"
103 default ISA_ARCV2
104
105config ISA_ARCOMPACT
106 bool "ARCompact ISA"
107 select CPU_NO_EFFICIENT_FFS
108 help
109 The original ARC ISA of ARC600/700 cores
110
111config ISA_ARCV2
112 bool "ARC ISA v2"
113 select ARC_TIMERS_64BIT
114 help
115 ISA for the Next Generation ARC-HS cores
116
117endchoice
118
119menu "ARC CPU Configuration"
120
121choice
122 prompt "ARC Core"
123 default ARC_CPU_770 if ISA_ARCOMPACT
124 default ARC_CPU_HS if ISA_ARCV2
125
126if ISA_ARCOMPACT
127
128config ARC_CPU_750D
129 bool "ARC750D"
130 select ARC_CANT_LLSC
131 help
132 Support for ARC750 core
133
134config ARC_CPU_770
135 bool "ARC770"
136 select ARC_HAS_SWAPE
137 help
138 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
139 This core has a bunch of cool new features:
140 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
141 Shared Address Spaces (for sharing TLB entries in MMU)
142 -Caches: New Prog Model, Region Flush
143 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
144
145endif #ISA_ARCOMPACT
146
147config ARC_CPU_HS
148 bool "ARC-HS"
149 depends on ISA_ARCV2
150 help
151 Support for ARC HS38x Cores based on ARCv2 ISA
152 The notable features are:
153 - SMP configurations of upto 4 core with coherency
154 - Optional L2 Cache and IO-Coherency
155 - Revised Interrupt Architecture (multiple priorites, reg banks,
156 auto stack switch, auto regfile save/restore)
157 - MMUv4 (PIPT dcache, Huge Pages)
158 - Instructions for
159 * 64bit load/store: LDD, STD
160 * Hardware assisted divide/remainder: DIV, REM
161 * Function prologue/epilogue: ENTER_S, LEAVE_S
162 * IRQ enable/disable: CLRI, SETI
163 * pop count: FFS, FLS
164 * SETcc, BMSKN, XBFU...
165
166endchoice
167
168config CPU_BIG_ENDIAN
169 bool "Enable Big Endian Mode"
170 help
171 Build kernel for Big Endian Mode of ARC CPU
172
173config SMP
174 bool "Symmetric Multi-Processing"
175 select ARC_MCIP if ISA_ARCV2
176 help
177 This enables support for systems with more than one CPU.
178
179if SMP
180
181config NR_CPUS
182 int "Maximum number of CPUs (2-4096)"
183 range 2 4096
184 default "4"
185
186config ARC_SMP_HALT_ON_RESET
187 bool "Enable Halt-on-reset boot mode"
188 help
189 In SMP configuration cores can be configured as Halt-on-reset
190 or they could all start at same time. For Halt-on-reset, non
191 masters are parked until Master kicks them so they can start of
192 at designated entry point. For other case, all jump to common
193 entry point and spin wait for Master's signal.
194
195endif #SMP
196
197config ARC_MCIP
198 bool "ARConnect Multicore IP (MCIP) Support "
199 depends on ISA_ARCV2
200 default y if SMP
201 help
202 This IP block enables SMP in ARC-HS38 cores.
203 It provides for cross-core interrupts, multi-core debug
204 hardware semaphores, shared memory,....
205
206menuconfig ARC_CACHE
207 bool "Enable Cache Support"
208 default y
209
210if ARC_CACHE
211
212config ARC_CACHE_LINE_SHIFT
213 int "Cache Line Length (as power of 2)"
214 range 5 7
215 default "6"
216 help
217 Starting with ARC700 4.9, Cache line length is configurable,
218 This option specifies "N", with Line-len = 2 power N
219 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
220 Linux only supports same line lengths for I and D caches.
221
222config ARC_HAS_ICACHE
223 bool "Use Instruction Cache"
224 default y
225
226config ARC_HAS_DCACHE
227 bool "Use Data Cache"
228 default y
229
230config ARC_CACHE_PAGES
231 bool "Per Page Cache Control"
232 default y
233 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
234 help
235 This can be used to over-ride the global I/D Cache Enable on a
236 per-page basis (but only for pages accessed via MMU such as
237 Kernel Virtual address or User Virtual Address)
238 TLB entries have a per-page Cache Enable Bit.
239 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
240 Global DISABLE + Per Page ENABLE won't work
241
242config ARC_CACHE_VIPT_ALIASING
243 bool "Support VIPT Aliasing D$"
244 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
245
246endif #ARC_CACHE
247
248config ARC_HAS_ICCM
249 bool "Use ICCM"
250 help
251 Single Cycle RAMS to store Fast Path Code
252
253config ARC_ICCM_SZ
254 int "ICCM Size in KB"
255 default "64"
256 depends on ARC_HAS_ICCM
257
258config ARC_HAS_DCCM
259 bool "Use DCCM"
260 help
261 Single Cycle RAMS to store Fast Path Data
262
263config ARC_DCCM_SZ
264 int "DCCM Size in KB"
265 default "64"
266 depends on ARC_HAS_DCCM
267
268config ARC_DCCM_BASE
269 hex "DCCM map address"
270 default "0xA0000000"
271 depends on ARC_HAS_DCCM
272
273choice
274 prompt "MMU Version"
275 default ARC_MMU_V3 if ARC_CPU_770
276 default ARC_MMU_V2 if ARC_CPU_750D
277 default ARC_MMU_V4 if ARC_CPU_HS
278
279if ISA_ARCOMPACT
280
281config ARC_MMU_V1
282 bool "MMU v1"
283 help
284 Orig ARC700 MMU
285
286config ARC_MMU_V2
287 bool "MMU v2"
288 help
289 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
290 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
291
292config ARC_MMU_V3
293 bool "MMU v3"
294 depends on ARC_CPU_770
295 help
296 Introduced with ARC700 4.10: New Features
297 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
298 Shared Address Spaces (SASID)
299
300endif
301
302config ARC_MMU_V4
303 bool "MMU v4"
304 depends on ISA_ARCV2
305
306endchoice
307
308
309choice
310 prompt "MMU Page Size"
311 default ARC_PAGE_SIZE_8K
312
313config ARC_PAGE_SIZE_8K
314 bool "8KB"
315 help
316 Choose between 8k vs 16k
317
318config ARC_PAGE_SIZE_16K
319 bool "16KB"
320 depends on ARC_MMU_V3 || ARC_MMU_V4
321
322config ARC_PAGE_SIZE_4K
323 bool "4KB"
324 depends on ARC_MMU_V3 || ARC_MMU_V4
325
326endchoice
327
328choice
329 prompt "MMU Super Page Size"
330 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
331 default ARC_HUGEPAGE_2M
332
333config ARC_HUGEPAGE_2M
334 bool "2MB"
335
336config ARC_HUGEPAGE_16M
337 bool "16MB"
338
339endchoice
340
341config NODES_SHIFT
342 int "Maximum NUMA Nodes (as a power of 2)"
343 default "0" if !DISCONTIGMEM
344 default "1" if DISCONTIGMEM
345 depends on NEED_MULTIPLE_NODES
346 ---help---
347 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
348 zones.
349
350if ISA_ARCOMPACT
351
352config ARC_COMPACT_IRQ_LEVELS
353 bool "Setup Timer IRQ as high Priority"
354 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
355 depends on !SMP
356
357config ARC_FPU_SAVE_RESTORE
358 bool "Enable FPU state persistence across context switch"
359 help
360 Double Precision Floating Point unit had dedicated regs which
361 need to be saved/restored across context-switch.
362 Note that ARC FPU is overly simplistic, unlike say x86, which has
363 hardware pieces to allow software to conditionally save/restore,
364 based on actual usage of FPU by a task. Thus our implemn does
365 this for all tasks in system.
366
367endif #ISA_ARCOMPACT
368
369config ARC_CANT_LLSC
370 def_bool n
371
372config ARC_HAS_LLSC
373 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
374 default y
375 depends on !ARC_CANT_LLSC
376
377config ARC_HAS_SWAPE
378 bool "Insn: SWAPE (endian-swap)"
379 default y
380
381if ISA_ARCV2
382
383config ARC_USE_UNALIGNED_MEM_ACCESS
384 bool "Enable unaligned access in HW"
385 default y
386 select HAVE_EFFICIENT_UNALIGNED_ACCESS
387 help
388 The ARC HS architecture supports unaligned memory access
389 which is disabled by default. Enable unaligned access in
390 hardware and use software to use it
391
392config ARC_HAS_LL64
393 bool "Insn: 64bit LDD/STD"
394 help
395 Enable gcc to generate 64-bit load/store instructions
396 ISA mandates even/odd registers to allow encoding of two
397 dest operands with 2 possible source operands.
398 default y
399
400config ARC_HAS_DIV_REM
401 bool "Insn: div, divu, rem, remu"
402 default y
403
404config ARC_HAS_ACCL_REGS
405 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
406 default y
407 help
408 Depending on the configuration, CPU can contain accumulator reg-pair
409 (also referred to as r58:r59). These can also be used by gcc as GPR so
410 kernel needs to save/restore per process
411
412config ARC_IRQ_NO_AUTOSAVE
413 bool "Disable hardware autosave regfile on interrupts"
414 default n
415 help
416 On HS cores, taken interrupt auto saves the regfile on stack.
417 This is programmable and can be optionally disabled in which case
418 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
419
420endif # ISA_ARCV2
421
422endmenu # "ARC CPU Configuration"
423
424config LINUX_LINK_BASE
425 hex "Kernel link address"
426 default "0x80000000"
427 help
428 ARC700 divides the 32 bit phy address space into two equal halves
429 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
430 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
431 Typically Linux kernel is linked at the start of untransalted addr,
432 hence the default value of 0x8zs.
433 However some customers have peripherals mapped at this addr, so
434 Linux needs to be scooted a bit.
435 If you don't know what the above means, leave this setting alone.
436 This needs to match memory start address specified in Device Tree
437
438config LINUX_RAM_BASE
439 hex "RAM base address"
440 default LINUX_LINK_BASE
441 help
442 By default Linux is linked at base of RAM. However in some special
443 cases (such as HSDK), Linux can't be linked at start of DDR, hence
444 this option.
445
446config HIGHMEM
447 bool "High Memory Support"
448 select ARCH_DISCONTIGMEM_ENABLE
449 help
450 With ARC 2G:2G address split, only upper 2G is directly addressable by
451 kernel. Enable this to potentially allow access to rest of 2G and PAE
452 in future
453
454config ARC_HAS_PAE40
455 bool "Support for the 40-bit Physical Address Extension"
456 depends on ISA_ARCV2
457 select HIGHMEM
458 select PHYS_ADDR_T_64BIT
459 help
460 Enable access to physical memory beyond 4G, only supported on
461 ARC cores with 40 bit Physical Addressing support
462
463config ARC_KVADDR_SIZE
464 int "Kernel Virtual Address Space size (MB)"
465 range 0 512
466 default "256"
467 help
468 The kernel address space is carved out of 256MB of translated address
469 space for catering to vmalloc, modules, pkmap, fixmap. This however may
470 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
471 this to be stretched to 512 MB (by extending into the reserved
472 kernel-user gutter)
473
474config ARC_CURR_IN_REG
475 bool "Dedicate Register r25 for current_task pointer"
476 default y
477 help
478 This reserved Register R25 to point to Current Task in
479 kernel mode. This saves memory access for each such access
480
481
482config ARC_EMUL_UNALIGNED
483 bool "Emulate unaligned memory access (userspace only)"
484 select SYSCTL_ARCH_UNALIGN_NO_WARN
485 select SYSCTL_ARCH_UNALIGN_ALLOW
486 depends on ISA_ARCOMPACT
487 help
488 This enables misaligned 16 & 32 bit memory access from user space.
489 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
490 potential bugs in code
491
492config HZ
493 int "Timer Frequency"
494 default 100
495
496config ARC_METAWARE_HLINK
497 bool "Support for Metaware debugger assisted Host access"
498 help
499 This options allows a Linux userland apps to directly access
500 host file system (open/creat/read/write etc) with help from
501 Metaware Debugger. This can come in handy for Linux-host communication
502 when there is no real usable peripheral such as EMAC.
503
504menuconfig ARC_DBG
505 bool "ARC debugging"
506 default y
507
508if ARC_DBG
509
510config ARC_DW2_UNWIND
511 bool "Enable DWARF specific kernel stack unwind"
512 default y
513 select KALLSYMS
514 help
515 Compiles the kernel with DWARF unwind information and can be used
516 to get stack backtraces.
517
518 If you say Y here the resulting kernel image will be slightly larger
519 but not slower, and it will give very useful debugging information.
520 If you don't debug the kernel, you can say N, but we may not be able
521 to solve problems without frame unwind information
522
523config ARC_DBG_TLB_PARANOIA
524 bool "Paranoia Checks in Low Level TLB Handlers"
525
526endif
527
528config ARC_BUILTIN_DTB_NAME
529 string "Built in DTB"
530 help
531 Set the name of the DTB to embed in the vmlinux binary
532 Leaving it blank selects the minimal "skeleton" dtb
533
534endmenu # "ARC Architecture Configuration"
535
536config FORCE_MAX_ZONEORDER
537 int "Maximum zone order"
538 default "12" if ARC_HUGEPAGE_16M
539 default "11"
540
541source "kernel/power/Kconfig"