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1TI AM654 SERDES
2
3Required properties:
4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
7 phandle while referencing this phy. Should be "2". The 1st cell
8 corresponds to the phy type (should be one of the types specified in
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
10 lane function.
11 If SERDES0 is referenced 2nd cell should be:
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
15 If SERDES1 is referenced 2nd cell should be:
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
19 - power-domains: As documented by the generic PM domain bindings in
20 Documentation/devicetree/bindings/power/power_domain.txt.
21 - clocks: List of clock-specifiers representing the input to the SERDES.
22 Should have 3 items representing the left input clock, external
23 reference clock and right input clock in that order.
24 - clock-output-names: List of clock names for each of the clock outputs of
25 SERDES. Should have 3 items for CMU reference clock,
26 left output clock and right output clock in that order.
27 - assigned-clocks: As defined in
28 Documentation/devicetree/bindings/clock/clock-bindings.txt
29 - assigned-clock-parents: As defined in
30 Documentation/devicetree/bindings/clock/clock-bindings.txt
31 - #clock-cells: Should be <1> to choose between the 3 output clocks.
32 Defined in Documentation/devicetree/bindings/clock/clock-bindings.txt
33
34 The following macros are defined in dt-bindings/phy/phy-am654-serdes.h
35 for selecting the correct reference clock. This can be used while
36 specifying the clocks created by SERDES.
37 => AM654_SERDES_CMU_REFCLK
38 => AM654_SERDES_LO_REFCLK
39 => AM654_SERDES_RO_REFCLK
40
41 - mux-controls: Phandle to the multiplexer that is used to select the lane
42 function. See #phy-cells above to see the multiplex values.
43
44Example:
45
46Example for SERDES0 is given below. It has 3 clock inputs;
47left input reference clock as indicated by <&k3_clks 153 4>, external
48reference clock as indicated by <&k3_clks 153 1> and right input
49reference clock as indicated by <&serdes1 AM654_SERDES_LO_REFCLK>. (The
50right input of SERDES0 is connected to the left output of SERDES1).
51
52SERDES0 registers 3 clock outputs as indicated in clock-output-names. The
53first refers to the CMU reference clock, second refers to the left output
54reference clock and the third refers to the right output reference clock.
55
56The assigned-clocks and assigned-clock-parents is used here to set the
57parent of left input reference clock to MAINHSDIV_CLKOUT4 and parent of
58CMU reference clock to left input reference clock.
59
60serdes0: serdes@900000 {
61 compatible = "ti,phy-am654-serdes";
62 reg = <0x0 0x900000 0x0 0x2000>;
63 reg-names = "serdes";
64 #phy-cells = <2>;
65 power-domains = <&k3_pds 153>;
66 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
67 <&serdes1 AM654_SERDES_LO_REFCLK>;
68 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk",
69 "serdes0_ro_refclk";
70 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
71 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
72 ti,serdes-clk = <&serdes0_clk>;
73 mux-controls = <&serdes_mux 0>;
74 #clock-cells = <1>;
75};
76
77Example for PCIe consumer node using the SERDES PHY specifier is given below.
78&pcie0_rc {
79 num-lanes = <2>;
80 phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
81 phy-names = "pcie-phy0", "pcie-phy1";
82};