tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AD5758 Digital to analog converters driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 *
7 * TODO: Currently CRC is not supported in this driver
8 */
9#include <linux/bsearch.h>
10#include <linux/delay.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/property.h>
14#include <linux/spi/spi.h>
15#include <linux/gpio/consumer.h>
16
17#include <linux/iio/iio.h>
18#include <linux/iio/sysfs.h>
19
20/* AD5758 registers definition */
21#define AD5758_NOP 0x00
22#define AD5758_DAC_INPUT 0x01
23#define AD5758_DAC_OUTPUT 0x02
24#define AD5758_CLEAR_CODE 0x03
25#define AD5758_USER_GAIN 0x04
26#define AD5758_USER_OFFSET 0x05
27#define AD5758_DAC_CONFIG 0x06
28#define AD5758_SW_LDAC 0x07
29#define AD5758_KEY 0x08
30#define AD5758_GP_CONFIG1 0x09
31#define AD5758_GP_CONFIG2 0x0A
32#define AD5758_DCDC_CONFIG1 0x0B
33#define AD5758_DCDC_CONFIG2 0x0C
34#define AD5758_WDT_CONFIG 0x0F
35#define AD5758_DIGITAL_DIAG_CONFIG 0x10
36#define AD5758_ADC_CONFIG 0x11
37#define AD5758_FAULT_PIN_CONFIG 0x12
38#define AD5758_TWO_STAGE_READBACK_SELECT 0x13
39#define AD5758_DIGITAL_DIAG_RESULTS 0x14
40#define AD5758_ANALOG_DIAG_RESULTS 0x15
41#define AD5758_STATUS 0x16
42#define AD5758_CHIP_ID 0x17
43#define AD5758_FREQ_MONITOR 0x18
44#define AD5758_DEVICE_ID_0 0x19
45#define AD5758_DEVICE_ID_1 0x1A
46#define AD5758_DEVICE_ID_2 0x1B
47#define AD5758_DEVICE_ID_3 0x1C
48
49/* AD5758_DAC_CONFIG */
50#define AD5758_DAC_CONFIG_RANGE_MSK GENMASK(3, 0)
51#define AD5758_DAC_CONFIG_RANGE_MODE(x) (((x) & 0xF) << 0)
52#define AD5758_DAC_CONFIG_INT_EN_MSK BIT(5)
53#define AD5758_DAC_CONFIG_INT_EN_MODE(x) (((x) & 0x1) << 5)
54#define AD5758_DAC_CONFIG_OUT_EN_MSK BIT(6)
55#define AD5758_DAC_CONFIG_OUT_EN_MODE(x) (((x) & 0x1) << 6)
56#define AD5758_DAC_CONFIG_SR_EN_MSK BIT(8)
57#define AD5758_DAC_CONFIG_SR_EN_MODE(x) (((x) & 0x1) << 8)
58#define AD5758_DAC_CONFIG_SR_CLOCK_MSK GENMASK(12, 9)
59#define AD5758_DAC_CONFIG_SR_CLOCK_MODE(x) (((x) & 0xF) << 9)
60#define AD5758_DAC_CONFIG_SR_STEP_MSK GENMASK(15, 13)
61#define AD5758_DAC_CONFIG_SR_STEP_MODE(x) (((x) & 0x7) << 13)
62
63/* AD5758_KEY */
64#define AD5758_KEY_CODE_RESET_1 0x15FA
65#define AD5758_KEY_CODE_RESET_2 0xAF51
66#define AD5758_KEY_CODE_SINGLE_ADC_CONV 0x1ADC
67#define AD5758_KEY_CODE_RESET_WDT 0x0D06
68#define AD5758_KEY_CODE_CALIB_MEM_REFRESH 0xFCBA
69
70/* AD5758_DCDC_CONFIG1 */
71#define AD5758_DCDC_CONFIG1_DCDC_VPROG_MSK GENMASK(4, 0)
72#define AD5758_DCDC_CONFIG1_DCDC_VPROG_MODE(x) (((x) & 0x1F) << 0)
73#define AD5758_DCDC_CONFIG1_DCDC_MODE_MSK GENMASK(6, 5)
74#define AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(x) (((x) & 0x3) << 5)
75
76/* AD5758_DCDC_CONFIG2 */
77#define AD5758_DCDC_CONFIG2_ILIMIT_MSK GENMASK(3, 1)
78#define AD5758_DCDC_CONFIG2_ILIMIT_MODE(x) (((x) & 0x7) << 1)
79#define AD5758_DCDC_CONFIG2_INTR_SAT_3WI_MSK BIT(11)
80#define AD5758_DCDC_CONFIG2_BUSY_3WI_MSK BIT(12)
81
82/* AD5758_DIGITAL_DIAG_RESULTS */
83#define AD5758_CAL_MEM_UNREFRESHED_MSK BIT(15)
84
85/* AD5758_ADC_CONFIG */
86#define AD5758_ADC_CONFIG_PPC_BUF_EN(x) (((x) & 0x1) << 11)
87#define AD5758_ADC_CONFIG_PPC_BUF_MSK BIT(11)
88
89#define AD5758_WR_FLAG_MSK(x) (0x80 | ((x) & 0x1F))
90
91#define AD5758_FULL_SCALE_MICRO 65535000000ULL
92
93/**
94 * struct ad5758_state - driver instance specific data
95 * @spi: spi_device
96 * @lock: mutex lock
97 * @out_range: struct which stores the output range
98 * @dc_dc_mode: variable which stores the mode of operation
99 * @dc_dc_ilim: variable which stores the dc-to-dc converter current limit
100 * @slew_time: variable which stores the target slew time
101 * @pwr_down: variable which contains whether a channel is powered down or not
102 * @data: spi transfer buffers
103 */
104
105struct ad5758_range {
106 int reg;
107 int min;
108 int max;
109};
110
111struct ad5758_state {
112 struct spi_device *spi;
113 struct mutex lock;
114 struct gpio_desc *gpio_reset;
115 struct ad5758_range out_range;
116 unsigned int dc_dc_mode;
117 unsigned int dc_dc_ilim;
118 unsigned int slew_time;
119 bool pwr_down;
120 __be32 d32[3];
121};
122
123/**
124 * Output ranges corresponding to bits [3:0] from DAC_CONFIG register
125 * 0000: 0 V to 5 V voltage range
126 * 0001: 0 V to 10 V voltage range
127 * 0010: ±5 V voltage range
128 * 0011: ±10 V voltage range
129 * 1000: 0 mA to 20 mA current range
130 * 1001: 0 mA to 24 mA current range
131 * 1010: 4 mA to 20 mA current range
132 * 1011: ±20 mA current range
133 * 1100: ±24 mA current range
134 * 1101: -1 mA to +22 mA current range
135 */
136enum ad5758_output_range {
137 AD5758_RANGE_0V_5V,
138 AD5758_RANGE_0V_10V,
139 AD5758_RANGE_PLUSMINUS_5V,
140 AD5758_RANGE_PLUSMINUS_10V,
141 AD5758_RANGE_0mA_20mA = 8,
142 AD5758_RANGE_0mA_24mA,
143 AD5758_RANGE_4mA_24mA,
144 AD5758_RANGE_PLUSMINUS_20mA,
145 AD5758_RANGE_PLUSMINUS_24mA,
146 AD5758_RANGE_MINUS_1mA_PLUS_22mA,
147};
148
149enum ad5758_dc_dc_mode {
150 AD5758_DCDC_MODE_POWER_OFF,
151 AD5758_DCDC_MODE_DPC_CURRENT,
152 AD5758_DCDC_MODE_DPC_VOLTAGE,
153 AD5758_DCDC_MODE_PPC_CURRENT,
154};
155
156static const struct ad5758_range ad5758_voltage_range[] = {
157 { AD5758_RANGE_0V_5V, 0, 5000000 },
158 { AD5758_RANGE_0V_10V, 0, 10000000 },
159 { AD5758_RANGE_PLUSMINUS_5V, -5000000, 5000000 },
160 { AD5758_RANGE_PLUSMINUS_10V, -10000000, 10000000 }
161};
162
163static const struct ad5758_range ad5758_current_range[] = {
164 { AD5758_RANGE_0mA_20mA, 0, 20000},
165 { AD5758_RANGE_0mA_24mA, 0, 24000 },
166 { AD5758_RANGE_4mA_24mA, 4, 24000 },
167 { AD5758_RANGE_PLUSMINUS_20mA, -20000, 20000 },
168 { AD5758_RANGE_PLUSMINUS_24mA, -24000, 24000 },
169 { AD5758_RANGE_MINUS_1mA_PLUS_22mA, -1000, 22000 },
170};
171
172static const int ad5758_sr_clk[16] = {
173 240000, 200000, 150000, 128000, 64000, 32000, 16000, 8000, 4000, 2000,
174 1000, 512, 256, 128, 64, 16
175};
176
177static const int ad5758_sr_step[8] = {
178 4, 12, 64, 120, 256, 500, 1820, 2048
179};
180
181static const int ad5758_dc_dc_ilim[6] = {
182 150000, 200000, 250000, 300000, 350000, 400000
183};
184
185static int ad5758_spi_reg_read(struct ad5758_state *st, unsigned int addr)
186{
187 struct spi_transfer t[] = {
188 {
189 .tx_buf = &st->d32[0],
190 .len = 4,
191 .cs_change = 1,
192 }, {
193 .tx_buf = &st->d32[1],
194 .rx_buf = &st->d32[2],
195 .len = 4,
196 },
197 };
198 int ret;
199
200 st->d32[0] = cpu_to_be32(
201 (AD5758_WR_FLAG_MSK(AD5758_TWO_STAGE_READBACK_SELECT) << 24) |
202 (addr << 8));
203 st->d32[1] = cpu_to_be32(AD5758_WR_FLAG_MSK(AD5758_NOP) << 24);
204
205 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
206 if (ret < 0)
207 return ret;
208
209 return (be32_to_cpu(st->d32[2]) >> 8) & 0xFFFF;
210}
211
212static int ad5758_spi_reg_write(struct ad5758_state *st,
213 unsigned int addr,
214 unsigned int val)
215{
216 st->d32[0] = cpu_to_be32((AD5758_WR_FLAG_MSK(addr) << 24) |
217 ((val & 0xFFFF) << 8));
218
219 return spi_write(st->spi, &st->d32[0], sizeof(st->d32[0]));
220}
221
222static int ad5758_spi_write_mask(struct ad5758_state *st,
223 unsigned int addr,
224 unsigned long int mask,
225 unsigned int val)
226{
227 int regval;
228
229 regval = ad5758_spi_reg_read(st, addr);
230 if (regval < 0)
231 return regval;
232
233 regval &= ~mask;
234 regval |= val;
235
236 return ad5758_spi_reg_write(st, addr, regval);
237}
238
239static int cmpfunc(const void *a, const void *b)
240{
241 return *(int *)a - *(int *)b;
242}
243
244static int ad5758_find_closest_match(const int *array,
245 unsigned int size, int val)
246{
247 int i;
248
249 for (i = 0; i < size; i++) {
250 if (val <= array[i])
251 return i;
252 }
253
254 return size - 1;
255}
256
257static int ad5758_wait_for_task_complete(struct ad5758_state *st,
258 unsigned int reg,
259 unsigned int mask)
260{
261 unsigned int timeout;
262 int ret;
263
264 timeout = 10;
265 do {
266 ret = ad5758_spi_reg_read(st, reg);
267 if (ret < 0)
268 return ret;
269
270 if (!(ret & mask))
271 return 0;
272
273 usleep_range(100, 1000);
274 } while (--timeout);
275
276 dev_err(&st->spi->dev,
277 "Error reading bit 0x%x in 0x%x register\n", mask, reg);
278
279 return -EIO;
280}
281
282static int ad5758_calib_mem_refresh(struct ad5758_state *st)
283{
284 int ret;
285
286 ret = ad5758_spi_reg_write(st, AD5758_KEY,
287 AD5758_KEY_CODE_CALIB_MEM_REFRESH);
288 if (ret < 0) {
289 dev_err(&st->spi->dev,
290 "Failed to initiate a calibration memory refresh\n");
291 return ret;
292 }
293
294 /* Wait to allow time for the internal calibrations to complete */
295 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
296 AD5758_CAL_MEM_UNREFRESHED_MSK);
297}
298
299static int ad5758_soft_reset(struct ad5758_state *st)
300{
301 int ret;
302
303 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_1);
304 if (ret < 0)
305 return ret;
306
307 ret = ad5758_spi_reg_write(st, AD5758_KEY, AD5758_KEY_CODE_RESET_2);
308
309 /* Perform a software reset and wait at least 100us */
310 usleep_range(100, 1000);
311
312 return ret;
313}
314
315static int ad5758_set_dc_dc_conv_mode(struct ad5758_state *st,
316 enum ad5758_dc_dc_mode mode)
317{
318 int ret;
319
320 /*
321 * The ENABLE_PPC_BUFFERS bit must be set prior to enabling PPC current
322 * mode.
323 */
324 if (mode == AD5758_DCDC_MODE_PPC_CURRENT) {
325 ret = ad5758_spi_write_mask(st, AD5758_ADC_CONFIG,
326 AD5758_ADC_CONFIG_PPC_BUF_MSK,
327 AD5758_ADC_CONFIG_PPC_BUF_EN(1));
328 if (ret < 0)
329 return ret;
330 }
331
332 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG1,
333 AD5758_DCDC_CONFIG1_DCDC_MODE_MSK,
334 AD5758_DCDC_CONFIG1_DCDC_MODE_MODE(mode));
335 if (ret < 0)
336 return ret;
337
338 /*
339 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
340 * This allows the 3-wire interface communication to complete.
341 */
342 ret = ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
343 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
344 if (ret < 0)
345 return ret;
346
347 st->dc_dc_mode = mode;
348
349 return ret;
350}
351
352static int ad5758_set_dc_dc_ilim(struct ad5758_state *st, unsigned int ilim)
353{
354 int ret;
355
356 ret = ad5758_spi_write_mask(st, AD5758_DCDC_CONFIG2,
357 AD5758_DCDC_CONFIG2_ILIMIT_MSK,
358 AD5758_DCDC_CONFIG2_ILIMIT_MODE(ilim));
359 if (ret < 0)
360 return ret;
361 /*
362 * Poll the BUSY_3WI bit in the DCDC_CONFIG2 register until it is 0.
363 * This allows the 3-wire interface communication to complete.
364 */
365 return ad5758_wait_for_task_complete(st, AD5758_DCDC_CONFIG2,
366 AD5758_DCDC_CONFIG2_BUSY_3WI_MSK);
367}
368
369static int ad5758_slew_rate_set(struct ad5758_state *st,
370 unsigned int sr_clk_idx,
371 unsigned int sr_step_idx)
372{
373 unsigned int mode;
374 unsigned long int mask;
375 int ret;
376
377 mask = AD5758_DAC_CONFIG_SR_EN_MSK |
378 AD5758_DAC_CONFIG_SR_CLOCK_MSK |
379 AD5758_DAC_CONFIG_SR_STEP_MSK;
380 mode = AD5758_DAC_CONFIG_SR_EN_MODE(1) |
381 AD5758_DAC_CONFIG_SR_STEP_MODE(sr_step_idx) |
382 AD5758_DAC_CONFIG_SR_CLOCK_MODE(sr_clk_idx);
383
384 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode);
385 if (ret < 0)
386 return ret;
387
388 /* Wait to allow time for the internal calibrations to complete */
389 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
390 AD5758_CAL_MEM_UNREFRESHED_MSK);
391}
392
393static int ad5758_slew_rate_config(struct ad5758_state *st)
394{
395 unsigned int sr_clk_idx, sr_step_idx;
396 int i, res;
397 s64 diff_new, diff_old;
398 u64 sr_step, calc_slew_time;
399
400 sr_clk_idx = 0;
401 sr_step_idx = 0;
402 diff_old = S64_MAX;
403 /*
404 * The slew time can be determined by using the formula:
405 * Slew Time = (Full Scale Out / (Step Size x Update Clk Freq))
406 * where Slew time is expressed in microseconds
407 * Given the desired slew time, the following algorithm determines the
408 * best match for the step size and the update clock frequency.
409 */
410 for (i = 0; i < ARRAY_SIZE(ad5758_sr_clk); i++) {
411 /*
412 * Go through each valid update clock freq and determine a raw
413 * value for the step size by using the formula:
414 * Step Size = Full Scale Out / (Update Clk Freq * Slew Time)
415 */
416 sr_step = AD5758_FULL_SCALE_MICRO;
417 do_div(sr_step, ad5758_sr_clk[i]);
418 do_div(sr_step, st->slew_time);
419 /*
420 * After a raw value for step size was determined, find the
421 * closest valid match
422 */
423 res = ad5758_find_closest_match(ad5758_sr_step,
424 ARRAY_SIZE(ad5758_sr_step),
425 sr_step);
426 /* Calculate the slew time */
427 calc_slew_time = AD5758_FULL_SCALE_MICRO;
428 do_div(calc_slew_time, ad5758_sr_step[res]);
429 do_div(calc_slew_time, ad5758_sr_clk[i]);
430 /*
431 * Determine with how many microseconds the calculated slew time
432 * is different from the desired slew time and store the diff
433 * for the next iteration
434 */
435 diff_new = abs(st->slew_time - calc_slew_time);
436 if (diff_new < diff_old) {
437 diff_old = diff_new;
438 sr_clk_idx = i;
439 sr_step_idx = res;
440 }
441 }
442
443 return ad5758_slew_rate_set(st, sr_clk_idx, sr_step_idx);
444}
445
446static int ad5758_set_out_range(struct ad5758_state *st, int range)
447{
448 int ret;
449
450 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
451 AD5758_DAC_CONFIG_RANGE_MSK,
452 AD5758_DAC_CONFIG_RANGE_MODE(range));
453 if (ret < 0)
454 return ret;
455
456 /* Wait to allow time for the internal calibrations to complete */
457 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
458 AD5758_CAL_MEM_UNREFRESHED_MSK);
459}
460
461static int ad5758_internal_buffers_en(struct ad5758_state *st, bool enable)
462{
463 int ret;
464
465 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
466 AD5758_DAC_CONFIG_INT_EN_MSK,
467 AD5758_DAC_CONFIG_INT_EN_MODE(enable));
468 if (ret < 0)
469 return ret;
470
471 /* Wait to allow time for the internal calibrations to complete */
472 return ad5758_wait_for_task_complete(st, AD5758_DIGITAL_DIAG_RESULTS,
473 AD5758_CAL_MEM_UNREFRESHED_MSK);
474}
475
476static int ad5758_reset(struct ad5758_state *st)
477{
478 if (st->gpio_reset) {
479 gpiod_set_value(st->gpio_reset, 0);
480 usleep_range(100, 1000);
481 gpiod_set_value(st->gpio_reset, 1);
482 usleep_range(100, 1000);
483
484 return 0;
485 } else {
486 /* Perform a software reset */
487 return ad5758_soft_reset(st);
488 }
489}
490
491static int ad5758_reg_access(struct iio_dev *indio_dev,
492 unsigned int reg,
493 unsigned int writeval,
494 unsigned int *readval)
495{
496 struct ad5758_state *st = iio_priv(indio_dev);
497 int ret;
498
499 mutex_lock(&st->lock);
500 if (readval) {
501 ret = ad5758_spi_reg_read(st, reg);
502 if (ret < 0) {
503 mutex_unlock(&st->lock);
504 return ret;
505 }
506
507 *readval = ret;
508 ret = 0;
509 } else {
510 ret = ad5758_spi_reg_write(st, reg, writeval);
511 }
512 mutex_unlock(&st->lock);
513
514 return ret;
515}
516
517static int ad5758_read_raw(struct iio_dev *indio_dev,
518 struct iio_chan_spec const *chan,
519 int *val, int *val2, long info)
520{
521 struct ad5758_state *st = iio_priv(indio_dev);
522 int max, min, ret;
523
524 switch (info) {
525 case IIO_CHAN_INFO_RAW:
526 mutex_lock(&st->lock);
527 ret = ad5758_spi_reg_read(st, AD5758_DAC_INPUT);
528 mutex_unlock(&st->lock);
529 if (ret < 0)
530 return ret;
531
532 *val = ret;
533 return IIO_VAL_INT;
534 case IIO_CHAN_INFO_SCALE:
535 min = st->out_range.min;
536 max = st->out_range.max;
537 *val = (max - min) / 1000;
538 *val2 = 16;
539 return IIO_VAL_FRACTIONAL_LOG2;
540 case IIO_CHAN_INFO_OFFSET:
541 min = st->out_range.min;
542 max = st->out_range.max;
543 *val = ((min * (1 << 16)) / (max - min)) / 1000;
544 return IIO_VAL_INT;
545 default:
546 return -EINVAL;
547 }
548}
549
550static int ad5758_write_raw(struct iio_dev *indio_dev,
551 struct iio_chan_spec const *chan,
552 int val, int val2, long info)
553{
554 struct ad5758_state *st = iio_priv(indio_dev);
555 int ret;
556
557 switch (info) {
558 case IIO_CHAN_INFO_RAW:
559 mutex_lock(&st->lock);
560 ret = ad5758_spi_reg_write(st, AD5758_DAC_INPUT, val);
561 mutex_unlock(&st->lock);
562 return ret;
563 default:
564 return -EINVAL;
565 }
566}
567
568static ssize_t ad5758_read_powerdown(struct iio_dev *indio_dev,
569 uintptr_t priv,
570 const struct iio_chan_spec *chan,
571 char *buf)
572{
573 struct ad5758_state *st = iio_priv(indio_dev);
574
575 return sprintf(buf, "%d\n", st->pwr_down);
576}
577
578static ssize_t ad5758_write_powerdown(struct iio_dev *indio_dev,
579 uintptr_t priv,
580 struct iio_chan_spec const *chan,
581 const char *buf, size_t len)
582{
583 struct ad5758_state *st = iio_priv(indio_dev);
584 bool pwr_down;
585 unsigned int dc_dc_mode, dac_config_mode, val;
586 unsigned long int dac_config_msk;
587 int ret;
588
589 ret = kstrtobool(buf, &pwr_down);
590 if (ret)
591 return ret;
592
593 mutex_lock(&st->lock);
594 if (pwr_down) {
595 dc_dc_mode = AD5758_DCDC_MODE_POWER_OFF;
596 val = 0;
597 } else {
598 dc_dc_mode = st->dc_dc_mode;
599 val = 1;
600 }
601
602 dac_config_mode = AD5758_DAC_CONFIG_OUT_EN_MODE(val) |
603 AD5758_DAC_CONFIG_INT_EN_MODE(val);
604 dac_config_msk = AD5758_DAC_CONFIG_OUT_EN_MSK |
605 AD5758_DAC_CONFIG_INT_EN_MSK;
606
607 ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
608 dac_config_msk,
609 dac_config_mode);
610 if (ret < 0)
611 goto err_unlock;
612
613 st->pwr_down = pwr_down;
614
615err_unlock:
616 mutex_unlock(&st->lock);
617
618 return ret ? ret : len;
619}
620
621static const struct iio_info ad5758_info = {
622 .read_raw = ad5758_read_raw,
623 .write_raw = ad5758_write_raw,
624 .debugfs_reg_access = &ad5758_reg_access,
625};
626
627static const struct iio_chan_spec_ext_info ad5758_ext_info[] = {
628 {
629 .name = "powerdown",
630 .read = ad5758_read_powerdown,
631 .write = ad5758_write_powerdown,
632 .shared = IIO_SHARED_BY_TYPE,
633 },
634 { }
635};
636
637#define AD5758_DAC_CHAN(_chan_type) { \
638 .type = (_chan_type), \
639 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_RAW) | \
640 BIT(IIO_CHAN_INFO_SCALE) | \
641 BIT(IIO_CHAN_INFO_OFFSET), \
642 .indexed = 1, \
643 .output = 1, \
644 .ext_info = ad5758_ext_info, \
645}
646
647static const struct iio_chan_spec ad5758_voltage_ch[] = {
648 AD5758_DAC_CHAN(IIO_VOLTAGE)
649};
650
651static const struct iio_chan_spec ad5758_current_ch[] = {
652 AD5758_DAC_CHAN(IIO_CURRENT)
653};
654
655static bool ad5758_is_valid_mode(enum ad5758_dc_dc_mode mode)
656{
657 switch (mode) {
658 case AD5758_DCDC_MODE_DPC_CURRENT:
659 case AD5758_DCDC_MODE_DPC_VOLTAGE:
660 case AD5758_DCDC_MODE_PPC_CURRENT:
661 return true;
662 default:
663 return false;
664 }
665}
666
667static int ad5758_crc_disable(struct ad5758_state *st)
668{
669 unsigned int mask;
670
671 mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A;
672 st->d32[0] = cpu_to_be32(mask);
673
674 return spi_write(st->spi, &st->d32[0], 4);
675}
676
677static int ad5758_find_out_range(struct ad5758_state *st,
678 const struct ad5758_range *range,
679 unsigned int size,
680 int min, int max)
681{
682 int i;
683
684 for (i = 0; i < size; i++) {
685 if ((min == range[i].min) && (max == range[i].max)) {
686 st->out_range.reg = range[i].reg;
687 st->out_range.min = range[i].min;
688 st->out_range.max = range[i].max;
689
690 return 0;
691 }
692 }
693
694 return -EINVAL;
695}
696
697static int ad5758_parse_dt(struct ad5758_state *st)
698{
699 unsigned int tmp, tmparray[2], size;
700 const struct ad5758_range *range;
701 int *index, ret;
702
703 st->dc_dc_ilim = 0;
704 ret = device_property_read_u32(&st->spi->dev,
705 "adi,dc-dc-ilim-microamp", &tmp);
706 if (ret) {
707 dev_dbg(&st->spi->dev,
708 "Missing \"dc-dc-ilim-microamp\" property\n");
709 } else {
710 index = bsearch(&tmp, ad5758_dc_dc_ilim,
711 ARRAY_SIZE(ad5758_dc_dc_ilim),
712 sizeof(int), cmpfunc);
713 if (!index)
714 dev_dbg(&st->spi->dev, "dc-dc-ilim out of range\n");
715 else
716 st->dc_dc_ilim = index - ad5758_dc_dc_ilim;
717 }
718
719 ret = device_property_read_u32(&st->spi->dev, "adi,dc-dc-mode",
720 &st->dc_dc_mode);
721 if (ret) {
722 dev_err(&st->spi->dev, "Missing \"dc-dc-mode\" property\n");
723 return ret;
724 }
725
726 if (!ad5758_is_valid_mode(st->dc_dc_mode))
727 return -EINVAL;
728
729 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE) {
730 ret = device_property_read_u32_array(&st->spi->dev,
731 "adi,range-microvolt",
732 tmparray, 2);
733 if (ret) {
734 dev_err(&st->spi->dev,
735 "Missing \"range-microvolt\" property\n");
736 return ret;
737 }
738 range = ad5758_voltage_range;
739 size = ARRAY_SIZE(ad5758_voltage_range);
740 } else {
741 ret = device_property_read_u32_array(&st->spi->dev,
742 "adi,range-microamp",
743 tmparray, 2);
744 if (ret) {
745 dev_err(&st->spi->dev,
746 "Missing \"range-microamp\" property\n");
747 return ret;
748 }
749 range = ad5758_current_range;
750 size = ARRAY_SIZE(ad5758_current_range);
751 }
752
753 ret = ad5758_find_out_range(st, range, size, tmparray[0], tmparray[1]);
754 if (ret) {
755 dev_err(&st->spi->dev, "range invalid\n");
756 return ret;
757 }
758
759 ret = device_property_read_u32(&st->spi->dev, "adi,slew-time-us", &tmp);
760 if (ret) {
761 dev_dbg(&st->spi->dev, "Missing \"slew-time-us\" property\n");
762 st->slew_time = 0;
763 } else {
764 st->slew_time = tmp;
765 }
766
767 return 0;
768}
769
770static int ad5758_init(struct ad5758_state *st)
771{
772 int regval, ret;
773
774 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
775 GPIOD_OUT_HIGH);
776 if (IS_ERR(st->gpio_reset))
777 return PTR_ERR(st->gpio_reset);
778
779 /* Disable CRC checks */
780 ret = ad5758_crc_disable(st);
781 if (ret < 0)
782 return ret;
783
784 /* Perform a reset */
785 ret = ad5758_reset(st);
786 if (ret < 0)
787 return ret;
788
789 /* Disable CRC checks */
790 ret = ad5758_crc_disable(st);
791 if (ret < 0)
792 return ret;
793
794 /* Perform a calibration memory refresh */
795 ret = ad5758_calib_mem_refresh(st);
796 if (ret < 0)
797 return ret;
798
799 regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS);
800 if (regval < 0)
801 return regval;
802
803 /* Clear all the error flags */
804 ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval);
805 if (ret < 0)
806 return ret;
807
808 /* Set the dc-to-dc current limit */
809 ret = ad5758_set_dc_dc_ilim(st, st->dc_dc_ilim);
810 if (ret < 0)
811 return ret;
812
813 /* Configure the dc-to-dc controller mode */
814 ret = ad5758_set_dc_dc_conv_mode(st, st->dc_dc_mode);
815 if (ret < 0)
816 return ret;
817
818 /* Configure the output range */
819 ret = ad5758_set_out_range(st, st->out_range.reg);
820 if (ret < 0)
821 return ret;
822
823 /* Enable Slew Rate Control, set the slew rate clock and step */
824 if (st->slew_time) {
825 ret = ad5758_slew_rate_config(st);
826 if (ret < 0)
827 return ret;
828 }
829
830 /* Power up the DAC and internal (INT) amplifiers */
831 ret = ad5758_internal_buffers_en(st, 1);
832 if (ret < 0)
833 return ret;
834
835 /* Enable VIOUT */
836 return ad5758_spi_write_mask(st, AD5758_DAC_CONFIG,
837 AD5758_DAC_CONFIG_OUT_EN_MSK,
838 AD5758_DAC_CONFIG_OUT_EN_MODE(1));
839}
840
841static int ad5758_probe(struct spi_device *spi)
842{
843 struct ad5758_state *st;
844 struct iio_dev *indio_dev;
845 int ret;
846
847 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
848 if (!indio_dev)
849 return -ENOMEM;
850
851 st = iio_priv(indio_dev);
852 spi_set_drvdata(spi, indio_dev);
853
854 st->spi = spi;
855
856 mutex_init(&st->lock);
857
858 indio_dev->dev.parent = &spi->dev;
859 indio_dev->name = spi_get_device_id(spi)->name;
860 indio_dev->info = &ad5758_info;
861 indio_dev->modes = INDIO_DIRECT_MODE;
862 indio_dev->num_channels = 1;
863
864 ret = ad5758_parse_dt(st);
865 if (ret < 0)
866 return ret;
867
868 if (st->dc_dc_mode == AD5758_DCDC_MODE_DPC_VOLTAGE)
869 indio_dev->channels = ad5758_voltage_ch;
870 else
871 indio_dev->channels = ad5758_current_ch;
872
873 ret = ad5758_init(st);
874 if (ret < 0) {
875 dev_err(&spi->dev, "AD5758 init failed\n");
876 return ret;
877 }
878
879 return devm_iio_device_register(&st->spi->dev, indio_dev);
880}
881
882static const struct spi_device_id ad5758_id[] = {
883 { "ad5758", 0 },
884 {}
885};
886MODULE_DEVICE_TABLE(spi, ad5758_id);
887
888static struct spi_driver ad5758_driver = {
889 .driver = {
890 .name = KBUILD_MODNAME,
891 },
892 .probe = ad5758_probe,
893 .id_table = ad5758_id,
894};
895
896module_spi_driver(ad5758_driver);
897
898MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
899MODULE_DESCRIPTION("Analog Devices AD5758 DAC");
900MODULE_LICENSE("GPL v2");