tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include "imx53-pinfunc.h"
7#include <dt-bindings/clock/imx5-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
19 */
20 chosen {};
21
22 aliases {
23 ethernet0 = &fec;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 gpio5 = &gpio6;
30 gpio6 = &gpio7;
31 i2c0 = &i2c1;
32 i2c1 = &i2c2;
33 i2c2 = &i2c3;
34 mmc0 = &esdhc1;
35 mmc1 = &esdhc2;
36 mmc2 = &esdhc3;
37 mmc3 = &esdhc4;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &cspi;
46 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a8";
54 reg = <0x0>;
55 clocks = <&clks IMX5_CLK_ARM>;
56 clock-latency = <61036>;
57 voltage-tolerance = <5>;
58 operating-points = <
59 /* kHz */
60 166666 850000
61 400000 900000
62 800000 1050000
63 1000000 1200000
64 1200000 1300000
65 >;
66 };
67 };
68
69 display-subsystem {
70 compatible = "fsl,imx-display-subsystem";
71 ports = <&ipu_di0>, <&ipu_di1>;
72 };
73
74 tzic: tz-interrupt-controller@fffc000 {
75 compatible = "fsl,imx53-tzic", "fsl,tzic";
76 interrupt-controller;
77 #interrupt-cells = <1>;
78 reg = <0x0fffc000 0x4000>;
79 };
80
81 clocks {
82 ckil {
83 compatible = "fsl,imx-ckil", "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32768>;
86 };
87
88 ckih1 {
89 compatible = "fsl,imx-ckih1", "fixed-clock";
90 #clock-cells = <0>;
91 clock-frequency = <22579200>;
92 };
93
94 ckih2 {
95 compatible = "fsl,imx-ckih2", "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <0>;
98 };
99
100 osc {
101 compatible = "fsl,imx-osc", "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <24000000>;
104 };
105 };
106
107 pmu: pmu {
108 compatible = "arm,cortex-a8-pmu";
109 interrupt-parent = <&tzic>;
110 interrupts = <77>;
111 };
112
113 usbphy0: usbphy-0 {
114 compatible = "usb-nop-xceiv";
115 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
116 clock-names = "main_clk";
117 #phy-cells = <0>;
118 status = "okay";
119 };
120
121 usbphy1: usbphy-1 {
122 compatible = "usb-nop-xceiv";
123 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
124 clock-names = "main_clk";
125 #phy-cells = <0>;
126 status = "okay";
127 };
128
129 soc {
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "simple-bus";
133 interrupt-parent = <&tzic>;
134 ranges;
135
136 sata: sata@10000000 {
137 compatible = "fsl,imx53-ahci";
138 reg = <0x10000000 0x1000>;
139 interrupts = <28>;
140 clocks = <&clks IMX5_CLK_SATA_GATE>,
141 <&clks IMX5_CLK_SATA_REF>,
142 <&clks IMX5_CLK_AHB>;
143 clock-names = "sata", "sata_ref", "ahb";
144 status = "disabled";
145 };
146
147 ipu: ipu@18000000 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "fsl,imx53-ipu";
151 reg = <0x18000000 0x08000000>;
152 interrupts = <11 10>;
153 clocks = <&clks IMX5_CLK_IPU_GATE>,
154 <&clks IMX5_CLK_IPU_DI0_GATE>,
155 <&clks IMX5_CLK_IPU_DI1_GATE>;
156 clock-names = "bus", "di0", "di1";
157 resets = <&src 2>;
158
159 ipu_csi0: port@0 {
160 reg = <0>;
161 };
162
163 ipu_csi1: port@1 {
164 reg = <1>;
165 };
166
167 ipu_di0: port@2 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <2>;
171
172 ipu_di0_disp0: endpoint@0 {
173 reg = <0>;
174 };
175
176 ipu_di0_lvds0: endpoint@1 {
177 reg = <1>;
178 remote-endpoint = <&lvds0_in>;
179 };
180 };
181
182 ipu_di1: port@3 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 reg = <3>;
186
187 ipu_di1_disp1: endpoint@0 {
188 reg = <0>;
189 };
190
191 ipu_di1_lvds1: endpoint@1 {
192 reg = <1>;
193 remote-endpoint = <&lvds1_in>;
194 };
195
196 ipu_di1_tve: endpoint@2 {
197 reg = <2>;
198 remote-endpoint = <&tve_in>;
199 };
200 };
201 };
202
203 gpu: gpu@30000000 {
204 compatible = "amd,imageon-200.0", "amd,imageon";
205 reg = <0x30000000 0x20000>;
206 reg-names = "kgsl_3d0_reg_memory";
207 interrupts = <12>;
208 interrupt-names = "kgsl_3d0_irq";
209 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
210 clock-names = "core_clk", "mem_iface_clk";
211 };
212
213 aips@50000000 { /* AIPS1 */
214 compatible = "fsl,aips-bus", "simple-bus";
215 #address-cells = <1>;
216 #size-cells = <1>;
217 reg = <0x50000000 0x10000000>;
218 ranges;
219
220 spba@50000000 {
221 compatible = "fsl,spba-bus", "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 reg = <0x50000000 0x40000>;
225 ranges;
226
227 esdhc1: esdhc@50004000 {
228 compatible = "fsl,imx53-esdhc";
229 reg = <0x50004000 0x4000>;
230 interrupts = <1>;
231 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
232 <&clks IMX5_CLK_DUMMY>,
233 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
234 clock-names = "ipg", "ahb", "per";
235 bus-width = <4>;
236 status = "disabled";
237 };
238
239 esdhc2: esdhc@50008000 {
240 compatible = "fsl,imx53-esdhc";
241 reg = <0x50008000 0x4000>;
242 interrupts = <2>;
243 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
244 <&clks IMX5_CLK_DUMMY>,
245 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
246 clock-names = "ipg", "ahb", "per";
247 bus-width = <4>;
248 status = "disabled";
249 };
250
251 uart3: serial@5000c000 {
252 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
253 reg = <0x5000c000 0x4000>;
254 interrupts = <33>;
255 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
256 <&clks IMX5_CLK_UART3_PER_GATE>;
257 clock-names = "ipg", "per";
258 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
259 dma-names = "rx", "tx";
260 status = "disabled";
261 };
262
263 ecspi1: spi@50010000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
267 reg = <0x50010000 0x4000>;
268 interrupts = <36>;
269 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
270 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 ssi2: ssi@50014000 {
276 #sound-dai-cells = <0>;
277 compatible = "fsl,imx53-ssi",
278 "fsl,imx51-ssi",
279 "fsl,imx21-ssi";
280 reg = <0x50014000 0x4000>;
281 interrupts = <30>;
282 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
283 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
284 clock-names = "ipg", "baud";
285 dmas = <&sdma 24 1 0>,
286 <&sdma 25 1 0>;
287 dma-names = "rx", "tx";
288 fsl,fifo-depth = <15>;
289 status = "disabled";
290 };
291
292 esdhc3: esdhc@50020000 {
293 compatible = "fsl,imx53-esdhc";
294 reg = <0x50020000 0x4000>;
295 interrupts = <3>;
296 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
297 <&clks IMX5_CLK_DUMMY>,
298 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
299 clock-names = "ipg", "ahb", "per";
300 bus-width = <4>;
301 status = "disabled";
302 };
303
304 esdhc4: esdhc@50024000 {
305 compatible = "fsl,imx53-esdhc";
306 reg = <0x50024000 0x4000>;
307 interrupts = <4>;
308 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
309 <&clks IMX5_CLK_DUMMY>,
310 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
311 clock-names = "ipg", "ahb", "per";
312 bus-width = <4>;
313 status = "disabled";
314 };
315 };
316
317 aipstz1: bridge@53f00000 {
318 compatible = "fsl,imx53-aipstz";
319 reg = <0x53f00000 0x60>;
320 };
321
322 usbotg: usb@53f80000 {
323 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
324 reg = <0x53f80000 0x0200>;
325 interrupts = <18>;
326 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
327 fsl,usbmisc = <&usbmisc 0>;
328 fsl,usbphy = <&usbphy0>;
329 status = "disabled";
330 };
331
332 usbh1: usb@53f80200 {
333 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
334 reg = <0x53f80200 0x0200>;
335 interrupts = <14>;
336 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
337 fsl,usbmisc = <&usbmisc 1>;
338 fsl,usbphy = <&usbphy1>;
339 dr_mode = "host";
340 status = "disabled";
341 };
342
343 usbh2: usb@53f80400 {
344 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
345 reg = <0x53f80400 0x0200>;
346 interrupts = <16>;
347 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
348 fsl,usbmisc = <&usbmisc 2>;
349 dr_mode = "host";
350 status = "disabled";
351 };
352
353 usbh3: usb@53f80600 {
354 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
355 reg = <0x53f80600 0x0200>;
356 interrupts = <17>;
357 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
358 fsl,usbmisc = <&usbmisc 3>;
359 dr_mode = "host";
360 status = "disabled";
361 };
362
363 usbmisc: usbmisc@53f80800 {
364 #index-cells = <1>;
365 compatible = "fsl,imx53-usbmisc";
366 reg = <0x53f80800 0x200>;
367 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
368 };
369
370 gpio1: gpio@53f84000 {
371 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
372 reg = <0x53f84000 0x4000>;
373 interrupts = <50 51>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 gpio2: gpio@53f88000 {
381 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
382 reg = <0x53f88000 0x4000>;
383 interrupts = <52 53>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 };
389
390 gpio3: gpio@53f8c000 {
391 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
392 reg = <0x53f8c000 0x4000>;
393 interrupts = <54 55>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 gpio4: gpio@53f90000 {
401 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
402 reg = <0x53f90000 0x4000>;
403 interrupts = <56 57>;
404 gpio-controller;
405 #gpio-cells = <2>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 };
409
410 kpp: kpp@53f94000 {
411 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
412 reg = <0x53f94000 0x4000>;
413 interrupts = <60>;
414 clocks = <&clks IMX5_CLK_DUMMY>;
415 status = "disabled";
416 };
417
418 wdog1: wdog@53f98000 {
419 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
420 reg = <0x53f98000 0x4000>;
421 interrupts = <58>;
422 clocks = <&clks IMX5_CLK_DUMMY>;
423 };
424
425 wdog2: wdog@53f9c000 {
426 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
427 reg = <0x53f9c000 0x4000>;
428 interrupts = <59>;
429 clocks = <&clks IMX5_CLK_DUMMY>;
430 status = "disabled";
431 };
432
433 gpt: timer@53fa0000 {
434 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
435 reg = <0x53fa0000 0x4000>;
436 interrupts = <39>;
437 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
438 <&clks IMX5_CLK_GPT_HF_GATE>;
439 clock-names = "ipg", "per";
440 };
441
442 srtc: rtc@53fa4000 {
443 compatible = "fsl,imx53-rtc";
444 reg = <0x53fa4000 0x4000>;
445 interrupts = <24>;
446 clocks = <&clks IMX5_CLK_SRTC_GATE>;
447 };
448
449 iomuxc: iomuxc@53fa8000 {
450 compatible = "fsl,imx53-iomuxc";
451 reg = <0x53fa8000 0x4000>;
452 };
453
454 gpr: iomuxc-gpr@53fa8000 {
455 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
456 reg = <0x53fa8000 0xc>;
457 };
458
459 ldb: ldb@53fa8008 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 compatible = "fsl,imx53-ldb";
463 reg = <0x53fa8008 0x4>;
464 gpr = <&gpr>;
465 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
466 <&clks IMX5_CLK_LDB_DI1_SEL>,
467 <&clks IMX5_CLK_IPU_DI0_SEL>,
468 <&clks IMX5_CLK_IPU_DI1_SEL>,
469 <&clks IMX5_CLK_LDB_DI0_GATE>,
470 <&clks IMX5_CLK_LDB_DI1_GATE>;
471 clock-names = "di0_pll", "di1_pll",
472 "di0_sel", "di1_sel",
473 "di0", "di1";
474 status = "disabled";
475
476 lvds-channel@0 {
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <0>;
480 status = "disabled";
481
482 port@0 {
483 reg = <0>;
484
485 lvds0_in: endpoint {
486 remote-endpoint = <&ipu_di0_lvds0>;
487 };
488 };
489
490 port@2 {
491 reg = <2>;
492 };
493 };
494
495 lvds-channel@1 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 reg = <1>;
499 status = "disabled";
500
501 port@1 {
502 reg = <1>;
503
504 lvds1_in: endpoint {
505 remote-endpoint = <&ipu_di1_lvds1>;
506 };
507 };
508
509 port@2 {
510 reg = <2>;
511 };
512 };
513 };
514
515 pwm1: pwm@53fb4000 {
516 #pwm-cells = <2>;
517 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
518 reg = <0x53fb4000 0x4000>;
519 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
520 <&clks IMX5_CLK_PWM1_HF_GATE>;
521 clock-names = "ipg", "per";
522 interrupts = <61>;
523 };
524
525 pwm2: pwm@53fb8000 {
526 #pwm-cells = <2>;
527 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
528 reg = <0x53fb8000 0x4000>;
529 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
530 <&clks IMX5_CLK_PWM2_HF_GATE>;
531 clock-names = "ipg", "per";
532 interrupts = <94>;
533 };
534
535 uart1: serial@53fbc000 {
536 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
537 reg = <0x53fbc000 0x4000>;
538 interrupts = <31>;
539 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
540 <&clks IMX5_CLK_UART1_PER_GATE>;
541 clock-names = "ipg", "per";
542 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
543 dma-names = "rx", "tx";
544 status = "disabled";
545 };
546
547 uart2: serial@53fc0000 {
548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
549 reg = <0x53fc0000 0x4000>;
550 interrupts = <32>;
551 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
552 <&clks IMX5_CLK_UART2_PER_GATE>;
553 clock-names = "ipg", "per";
554 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
555 dma-names = "rx", "tx";
556 status = "disabled";
557 };
558
559 can1: can@53fc8000 {
560 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
561 reg = <0x53fc8000 0x4000>;
562 interrupts = <82>;
563 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
564 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
565 clock-names = "ipg", "per";
566 status = "disabled";
567 };
568
569 can2: can@53fcc000 {
570 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
571 reg = <0x53fcc000 0x4000>;
572 interrupts = <83>;
573 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
574 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
575 clock-names = "ipg", "per";
576 status = "disabled";
577 };
578
579 src: src@53fd0000 {
580 compatible = "fsl,imx53-src", "fsl,imx51-src";
581 reg = <0x53fd0000 0x4000>;
582 #reset-cells = <1>;
583 };
584
585 clks: ccm@53fd4000{
586 compatible = "fsl,imx53-ccm";
587 reg = <0x53fd4000 0x4000>;
588 interrupts = <0 71 0x04 0 72 0x04>;
589 #clock-cells = <1>;
590 };
591
592 gpio5: gpio@53fdc000 {
593 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
594 reg = <0x53fdc000 0x4000>;
595 interrupts = <103 104>;
596 gpio-controller;
597 #gpio-cells = <2>;
598 interrupt-controller;
599 #interrupt-cells = <2>;
600 };
601
602 gpio6: gpio@53fe0000 {
603 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
604 reg = <0x53fe0000 0x4000>;
605 interrupts = <105 106>;
606 gpio-controller;
607 #gpio-cells = <2>;
608 interrupt-controller;
609 #interrupt-cells = <2>;
610 };
611
612 gpio7: gpio@53fe4000 {
613 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
614 reg = <0x53fe4000 0x4000>;
615 interrupts = <107 108>;
616 gpio-controller;
617 #gpio-cells = <2>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
620 };
621
622 i2c3: i2c@53fec000 {
623 #address-cells = <1>;
624 #size-cells = <0>;
625 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
626 reg = <0x53fec000 0x4000>;
627 interrupts = <64>;
628 clocks = <&clks IMX5_CLK_I2C3_GATE>;
629 status = "disabled";
630 };
631
632 uart4: serial@53ff0000 {
633 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
634 reg = <0x53ff0000 0x4000>;
635 interrupts = <13>;
636 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
637 <&clks IMX5_CLK_UART4_PER_GATE>;
638 clock-names = "ipg", "per";
639 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
640 dma-names = "rx", "tx";
641 status = "disabled";
642 };
643 };
644
645 aips@60000000 { /* AIPS2 */
646 compatible = "fsl,aips-bus", "simple-bus";
647 #address-cells = <1>;
648 #size-cells = <1>;
649 reg = <0x60000000 0x10000000>;
650 ranges;
651
652 aipstz2: bridge@63f00000 {
653 compatible = "fsl,imx53-aipstz";
654 reg = <0x63f00000 0x60>;
655 };
656
657 iim: iim@63f98000 {
658 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
659 reg = <0x63f98000 0x4000>;
660 interrupts = <69>;
661 clocks = <&clks IMX5_CLK_IIM_GATE>;
662 };
663
664 uart5: serial@63f90000 {
665 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
666 reg = <0x63f90000 0x4000>;
667 interrupts = <86>;
668 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
669 <&clks IMX5_CLK_UART5_PER_GATE>;
670 clock-names = "ipg", "per";
671 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
672 dma-names = "rx", "tx";
673 status = "disabled";
674 };
675
676 tigerp: tigerp@63fa0000 {
677 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
678 reg = <0x63fa0000 0x28>;
679 };
680
681 owire: owire@63fa4000 {
682 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
683 reg = <0x63fa4000 0x4000>;
684 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
685 status = "disabled";
686 };
687
688 ecspi2: spi@63fac000 {
689 #address-cells = <1>;
690 #size-cells = <0>;
691 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
692 reg = <0x63fac000 0x4000>;
693 interrupts = <37>;
694 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
695 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
696 clock-names = "ipg", "per";
697 status = "disabled";
698 };
699
700 sdma: sdma@63fb0000 {
701 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
702 reg = <0x63fb0000 0x4000>;
703 interrupts = <6>;
704 clocks = <&clks IMX5_CLK_SDMA_GATE>,
705 <&clks IMX5_CLK_AHB>;
706 clock-names = "ipg", "ahb";
707 #dma-cells = <3>;
708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
709 };
710
711 cspi: spi@63fc0000 {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
715 reg = <0x63fc0000 0x4000>;
716 interrupts = <38>;
717 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
718 <&clks IMX5_CLK_CSPI_IPG_GATE>;
719 clock-names = "ipg", "per";
720 status = "disabled";
721 };
722
723 i2c2: i2c@63fc4000 {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
727 reg = <0x63fc4000 0x4000>;
728 interrupts = <63>;
729 clocks = <&clks IMX5_CLK_I2C2_GATE>;
730 status = "disabled";
731 };
732
733 i2c1: i2c@63fc8000 {
734 #address-cells = <1>;
735 #size-cells = <0>;
736 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
737 reg = <0x63fc8000 0x4000>;
738 interrupts = <62>;
739 clocks = <&clks IMX5_CLK_I2C1_GATE>;
740 status = "disabled";
741 };
742
743 ssi1: ssi@63fcc000 {
744 #sound-dai-cells = <0>;
745 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
746 "fsl,imx21-ssi";
747 reg = <0x63fcc000 0x4000>;
748 interrupts = <29>;
749 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
750 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
751 clock-names = "ipg", "baud";
752 dmas = <&sdma 28 0 0>,
753 <&sdma 29 0 0>;
754 dma-names = "rx", "tx";
755 fsl,fifo-depth = <15>;
756 status = "disabled";
757 };
758
759 audmux: audmux@63fd0000 {
760 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
761 reg = <0x63fd0000 0x4000>;
762 status = "disabled";
763 };
764
765 nfc: nand@63fdb000 {
766 compatible = "fsl,imx53-nand";
767 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
768 interrupts = <8>;
769 clocks = <&clks IMX5_CLK_NFC_GATE>;
770 status = "disabled";
771 };
772
773 ssi3: ssi@63fe8000 {
774 #sound-dai-cells = <0>;
775 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
776 "fsl,imx21-ssi";
777 reg = <0x63fe8000 0x4000>;
778 interrupts = <96>;
779 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
780 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
781 clock-names = "ipg", "baud";
782 dmas = <&sdma 46 0 0>,
783 <&sdma 47 0 0>;
784 dma-names = "rx", "tx";
785 fsl,fifo-depth = <15>;
786 status = "disabled";
787 };
788
789 fec: ethernet@63fec000 {
790 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
791 reg = <0x63fec000 0x4000>;
792 interrupts = <87>;
793 clocks = <&clks IMX5_CLK_FEC_GATE>,
794 <&clks IMX5_CLK_FEC_GATE>,
795 <&clks IMX5_CLK_FEC_GATE>;
796 clock-names = "ipg", "ahb", "ptp";
797 status = "disabled";
798 };
799
800 tve: tve@63ff0000 {
801 compatible = "fsl,imx53-tve";
802 reg = <0x63ff0000 0x1000>;
803 interrupts = <92>;
804 clocks = <&clks IMX5_CLK_TVE_GATE>,
805 <&clks IMX5_CLK_IPU_DI1_SEL>;
806 clock-names = "tve", "di_sel";
807 status = "disabled";
808
809 port {
810 tve_in: endpoint {
811 remote-endpoint = <&ipu_di1_tve>;
812 };
813 };
814 };
815
816 vpu: vpu@63ff4000 {
817 compatible = "fsl,imx53-vpu", "cnm,coda7541";
818 reg = <0x63ff4000 0x1000>;
819 interrupts = <9>;
820 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
821 <&clks IMX5_CLK_VPU_GATE>;
822 clock-names = "per", "ahb";
823 resets = <&src 1>;
824 iram = <&ocram>;
825 };
826
827 sahara: crypto@63ff8000 {
828 compatible = "fsl,imx53-sahara";
829 reg = <0x63ff8000 0x4000>;
830 interrupts = <19 20>;
831 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
832 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
833 clock-names = "ipg", "ahb";
834 };
835 };
836
837 ocram: sram@f8000000 {
838 compatible = "mmio-sram";
839 reg = <0xf8000000 0x20000>;
840 clocks = <&clks IMX5_CLK_OCRAM>;
841 };
842 };
843};