tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2015 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26
27/ {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 model = "ARM RealView PB11MPcore";
31 compatible = "arm,realview-pb11mp";
32
33 chosen { };
34
35 aliases {
36 serial0 = &pb11mp_serial0;
37 serial1 = &pb11mp_serial1;
38 serial2 = &pb11mp_serial2;
39 serial3 = &pb11mp_serial3;
40 };
41
42 memory {
43 device_type = "memory";
44 /*
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
47 */
48 reg = <0x70000000 0x20000000>;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
55
56 MP11_0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,arm11mpcore";
59 reg = <0>;
60 next-level-cache = <&L2>;
61 };
62
63 MP11_1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,arm11mpcore";
66 reg = <1>;
67 next-level-cache = <&L2>;
68 };
69
70 MP11_2: cpu@2 {
71 device_type = "cpu";
72 compatible = "arm,arm11mpcore";
73 reg = <2>;
74 next-level-cache = <&L2>;
75 };
76
77 MP11_3: cpu@3 {
78 device_type = "cpu";
79 compatible = "arm,arm11mpcore";
80 reg = <3>;
81 next-level-cache = <&L2>;
82 };
83 };
84
85 /* Primary TestChip GIC synthesized with the CPU */
86 intc_tc11mp: interrupt-controller@1f000100 {
87 compatible = "arm,tc11mp-gic";
88 #interrupt-cells = <3>;
89 #address-cells = <1>;
90 interrupt-controller;
91 reg = <0x1f001000 0x1000>,
92 <0x1f000100 0x100>;
93 };
94
95 L2: l2-cache {
96 compatible = "arm,l220-cache";
97 reg = <0x1f002000 0x1000>;
98 interrupt-parent = <&intc_tc11mp>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
102 cache-unified;
103 cache-level = <2>;
104 /*
105 * Override default cache size, sets and
106 * associativity as these may be erroneously set
107 * up by boot loader(s), probably for safety
108 * since th outer sync operation can cause the
109 * cache to hang unless disabled.
110 */
111 cache-size = <1048576>; // 1MB
112 cache-sets = <4096>;
113 cache-line-size = <32>;
114 arm,shared-override;
115 arm,parity-enable;
116 arm,outer-sync-disable;
117 };
118
119 scu@1f000000 {
120 compatible = "arm,arm11mp-scu";
121 reg = <0x1f000000 0x100>;
122 };
123
124 timer@1f000600 {
125 compatible = "arm,arm11mp-twd-timer";
126 reg = <0x1f000600 0x20>;
127 interrupt-parent = <&intc_tc11mp>;
128 interrupts = <1 13 0xf04>;
129 };
130
131 watchdog@1f000620 {
132 compatible = "arm,arm11mp-twd-wdt";
133 reg = <0x1f000620 0x20>;
134 interrupt-parent = <&intc_tc11mp>;
135 interrupts = <1 14 0xf04>;
136 };
137
138 /* PMU with one IRQ line per core */
139 pmu {
140 compatible = "arm,arm11mpcore-pmu";
141 interrupt-parent = <&intc_tc11mp>;
142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
147 };
148
149 /* The voltage to the MMC card is hardwired at 3.3V */
150 vmmc: regulator-vmmc {
151 compatible = "regulator-fixed";
152 regulator-name = "vmmc";
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-boot-on;
156 };
157
158 veth: regulator-veth {
159 compatible = "regulator-fixed";
160 regulator-name = "veth";
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
163 regulator-boot-on;
164 };
165
166 xtal24mhz: xtal24mhz@24M {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 };
171
172 refclk32khz: refclk32khz {
173 compatible = "fixed-clock";
174 #clock-cells = <0>;
175 clock-frequency = <32768>;
176 };
177
178 timclk: timclk@1M {
179 #clock-cells = <0>;
180 compatible = "fixed-factor-clock";
181 clock-div = <24>;
182 clock-mult = <1>;
183 clocks = <&xtal24mhz>;
184 };
185
186 mclk: mclk@24M {
187 #clock-cells = <0>;
188 compatible = "fixed-factor-clock";
189 clock-div = <1>;
190 clock-mult = <1>;
191 clocks = <&xtal24mhz>;
192 };
193
194 kmiclk: kmiclk@24M {
195 #clock-cells = <0>;
196 compatible = "fixed-factor-clock";
197 clock-div = <1>;
198 clock-mult = <1>;
199 clocks = <&xtal24mhz>;
200 };
201
202 sspclk: sspclk@24M {
203 #clock-cells = <0>;
204 compatible = "fixed-factor-clock";
205 clock-div = <1>;
206 clock-mult = <1>;
207 clocks = <&xtal24mhz>;
208 };
209
210 uartclk: uartclk@24M {
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <1>;
214 clock-mult = <1>;
215 clocks = <&xtal24mhz>;
216 };
217
218 wdogclk: wdogclk@24M {
219 #clock-cells = <0>;
220 compatible = "fixed-factor-clock";
221 clock-div = <1>;
222 clock-mult = <1>;
223 clocks = <&xtal24mhz>;
224 };
225
226 /* FIXME: this actually hangs off the PLL clocks */
227 pclk: pclk@0 {
228 #clock-cells = <0>;
229 compatible = "fixed-clock";
230 clock-frequency = <0>;
231 };
232
233 flash0@40000000 {
234 /* 2 * 32MiB NOR Flash memory */
235 compatible = "arm,versatile-flash", "cfi-flash";
236 reg = <0x40000000 0x04000000>;
237 bank-width = <4>;
238 };
239
240 flash1@44000000 {
241 // 2 * 32MiB NOR Flash memory
242 compatible = "arm,versatile-flash", "cfi-flash";
243 reg = <0x44000000 0x04000000>;
244 bank-width = <4>;
245 };
246
247 bridge {
248 compatible = "ti,ths8134a", "ti,ths8134";
249 #address-cells = <1>;
250 #size-cells = <0>;
251
252 ports {
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 port@0 {
257 reg = <0>;
258
259 vga_bridge_in: endpoint {
260 remote-endpoint = <&clcd_pads>;
261 };
262 };
263
264 port@1 {
265 reg = <1>;
266
267 vga_bridge_out: endpoint {
268 remote-endpoint = <&vga_con_in>;
269 };
270 };
271 };
272 };
273
274 vga {
275 /*
276 * This DDC I2C is connected directly to the DVI portions
277 * of the connector, so it's not really working when the
278 * monitor is connected to the VGA connector.
279 */
280 compatible = "vga-connector";
281 ddc-i2c-bus = <&i2c1>;
282
283 port {
284 vga_con_in: endpoint {
285 remote-endpoint = <&vga_bridge_out>;
286 };
287 };
288 };
289
290 soc {
291 #address-cells = <1>;
292 #size-cells = <1>;
293 compatible = "arm,realview-pb11mp-soc", "simple-bus";
294 regmap = <&pb11mp_syscon>;
295 ranges;
296
297 pb11mp_syscon: syscon@10000000 {
298 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
299 reg = <0x10000000 0x1000>;
300
301 led@08.0 {
302 compatible = "register-bit-led";
303 offset = <0x08>;
304 mask = <0x01>;
305 label = "versatile:0";
306 linux,default-trigger = "heartbeat";
307 default-state = "on";
308 };
309 led@08.1 {
310 compatible = "register-bit-led";
311 offset = <0x08>;
312 mask = <0x02>;
313 label = "versatile:1";
314 linux,default-trigger = "mmc0";
315 default-state = "off";
316 };
317 led@08.2 {
318 compatible = "register-bit-led";
319 offset = <0x08>;
320 mask = <0x04>;
321 label = "versatile:2";
322 linux,default-trigger = "cpu0";
323 default-state = "off";
324 };
325 led@08.3 {
326 compatible = "register-bit-led";
327 offset = <0x08>;
328 mask = <0x08>;
329 label = "versatile:3";
330 linux,default-trigger = "cpu1";
331 default-state = "off";
332 };
333 led@08.4 {
334 compatible = "register-bit-led";
335 offset = <0x08>;
336 mask = <0x10>;
337 label = "versatile:4";
338 linux,default-trigger = "cpu2";
339 default-state = "off";
340 };
341 led@08.5 {
342 compatible = "register-bit-led";
343 offset = <0x08>;
344 mask = <0x20>;
345 label = "versatile:5";
346 linux,default-trigger = "cpu3";
347 default-state = "off";
348 };
349 led@08.6 {
350 compatible = "register-bit-led";
351 offset = <0x08>;
352 mask = <0x40>;
353 label = "versatile:6";
354 default-state = "off";
355 };
356 led@08.7 {
357 compatible = "register-bit-led";
358 offset = <0x08>;
359 mask = <0x80>;
360 label = "versatile:7";
361 default-state = "off";
362 };
363
364 oscclk0: osc0@0c {
365 compatible = "arm,syscon-icst307";
366 #clock-cells = <0>;
367 lock-offset = <0x20>;
368 vco-offset = <0x0C>;
369 clocks = <&xtal24mhz>;
370 };
371 oscclk1: osc1@10 {
372 compatible = "arm,syscon-icst307";
373 #clock-cells = <0>;
374 lock-offset = <0x20>;
375 vco-offset = <0x10>;
376 clocks = <&xtal24mhz>;
377 };
378 oscclk2: osc2@14 {
379 compatible = "arm,syscon-icst307";
380 #clock-cells = <0>;
381 lock-offset = <0x20>;
382 vco-offset = <0x14>;
383 clocks = <&xtal24mhz>;
384 };
385 oscclk3: osc3@18 {
386 compatible = "arm,syscon-icst307";
387 #clock-cells = <0>;
388 lock-offset = <0x20>;
389 vco-offset = <0x18>;
390 clocks = <&xtal24mhz>;
391 };
392 oscclk4: osc4@1c {
393 compatible = "arm,syscon-icst307";
394 #clock-cells = <0>;
395 lock-offset = <0x20>;
396 vco-offset = <0x1c>;
397 clocks = <&xtal24mhz>;
398 };
399 oscclk5: osc5@d4 {
400 compatible = "arm,syscon-icst307";
401 #clock-cells = <0>;
402 lock-offset = <0x20>;
403 vco-offset = <0xd4>;
404 clocks = <&xtal24mhz>;
405 };
406 oscclk6: osc6@d8 {
407 compatible = "arm,syscon-icst307";
408 #clock-cells = <0>;
409 lock-offset = <0x20>;
410 vco-offset = <0xd8>;
411 clocks = <&xtal24mhz>;
412 };
413 };
414
415 sp810_syscon: sysctl@10001000 {
416 compatible = "arm,sp810", "arm,primecell";
417 reg = <0x10001000 0x1000>;
418 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
419 clock-names = "refclk", "timclk", "apb_pclk";
420 #clock-cells = <1>;
421 clock-output-names = "timerclk0",
422 "timerclk1",
423 "timerclk2",
424 "timerclk3";
425 assigned-clocks = <&sp810_syscon 0>,
426 <&sp810_syscon 1>,
427 <&sp810_syscon 2>,
428 <&sp810_syscon 3>;
429 assigned-clock-parents = <&timclk>,
430 <&timclk>,
431 <&timclk>,
432 <&timclk>;
433 };
434
435 i2c0: i2c@10002000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "arm,versatile-i2c";
439 reg = <0x10002000 0x1000>;
440
441 rtc@68 {
442 compatible = "dallas,ds1338";
443 reg = <0x68>;
444 };
445 };
446
447 aaci: aaci@10004000 {
448 compatible = "arm,pl041", "arm,primecell";
449 reg = <0x10004000 0x1000>;
450 interrupt-parent = <&intc_tc11mp>;
451 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&pclk>;
453 clock-names = "apb_pclk";
454 };
455
456 mci: mmcsd@10005000 {
457 compatible = "arm,pl18x", "arm,primecell";
458 reg = <0x10005000 0x1000>;
459 interrupt-parent = <&intc_tc11mp>;
460 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
461 <0 15 IRQ_TYPE_LEVEL_HIGH>;
462 /* Due to frequent FIFO overruns, use just 500 kHz */
463 max-frequency = <500000>;
464 bus-width = <4>;
465 cap-sd-highspeed;
466 cap-mmc-highspeed;
467 clocks = <&mclk>, <&pclk>;
468 clock-names = "mclk", "apb_pclk";
469 vmmc-supply = <&vmmc>;
470 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
471 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
472 };
473
474 kmi0: kmi@10006000 {
475 compatible = "arm,pl050", "arm,primecell";
476 reg = <0x10006000 0x1000>;
477 interrupt-parent = <&intc_tc11mp>;
478 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&kmiclk>, <&pclk>;
480 clock-names = "KMIREFCLK", "apb_pclk";
481 };
482
483 kmi1: kmi@10007000 {
484 compatible = "arm,pl050", "arm,primecell";
485 reg = <0x10007000 0x1000>;
486 interrupt-parent = <&intc_tc11mp>;
487 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&kmiclk>, <&pclk>;
489 clock-names = "KMIREFCLK", "apb_pclk";
490 };
491
492 pb11mp_serial0: serial@10009000 {
493 compatible = "arm,pl011", "arm,primecell";
494 reg = <0x10009000 0x1000>;
495 interrupt-parent = <&intc_tc11mp>;
496 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&uartclk>, <&pclk>;
498 clock-names = "uartclk", "apb_pclk";
499 };
500
501 pb11mp_serial1: serial@1000a000 {
502 compatible = "arm,pl011", "arm,primecell";
503 reg = <0x1000a000 0x1000>;
504 interrupt-parent = <&intc_tc11mp>;
505 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&uartclk>, <&pclk>;
507 clock-names = "uartclk", "apb_pclk";
508 };
509
510 pb11mp_serial2: serial@1000b000 {
511 compatible = "arm,pl011", "arm,primecell";
512 reg = <0x1000b000 0x1000>;
513 interrupt-parent = <&intc_pb11mp>;
514 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&uartclk>, <&pclk>;
516 clock-names = "uartclk", "apb_pclk";
517 };
518
519 pb11mp_serial3: serial@1000c000 {
520 compatible = "arm,pl011", "arm,primecell";
521 reg = <0x1000c000 0x1000>;
522 interrupt-parent = <&intc_pb11mp>;
523 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&uartclk>, <&pclk>;
525 clock-names = "uartclk", "apb_pclk";
526 };
527
528 spi@1000d000 {
529 compatible = "arm,pl022", "arm,primecell";
530 reg = <0x1000d000 0x1000>;
531 interrupt-parent = <&intc_pb11mp>;
532 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&sspclk>, <&pclk>;
534 clock-names = "SSPCLK", "apb_pclk";
535 };
536
537 watchdog@1000f000 {
538 compatible = "arm,sp805", "arm,primecell";
539 reg = <0x1000f000 0x1000>;
540 interrupt-parent = <&intc_pb11mp>;
541 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&wdogclk>, <&pclk>;
543 clock-names = "wdogclk", "apb_pclk";
544 status = "disabled";
545 };
546
547 watchdog@10010000 {
548 compatible = "arm,sp805", "arm,primecell";
549 reg = <0x10010000 0x1000>;
550 interrupt-parent = <&intc_pb11mp>;
551 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&wdogclk>, <&pclk>;
553 clock-names = "wdogclk", "apb_pclk";
554 };
555
556 timer01: timer@10011000 {
557 compatible = "arm,sp804", "arm,primecell";
558 reg = <0x10011000 0x1000>;
559 interrupt-parent = <&intc_tc11mp>;
560 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
561 arm,sp804-has-irq = <1>;
562 clocks = <&sp810_syscon 0>,
563 <&sp810_syscon 1>,
564 <&pclk>;
565 clock-names = "timerclk0",
566 "timerclk1",
567 "apb_pclk";
568 };
569
570 timer23: timer@10012000 {
571 compatible = "arm,sp804", "arm,primecell";
572 reg = <0x10012000 0x1000>;
573 interrupt-parent = <&intc_tc11mp>;
574 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
575 arm,sp804-has-irq = <1>;
576 clocks = <&sp810_syscon 2>,
577 <&sp810_syscon 3>,
578 <&pclk>;
579 clock-names = "timerclk2",
580 "timerclk3",
581 "apb_pclk";
582 };
583
584 gpio0: gpio@10013000 {
585 compatible = "arm,pl061", "arm,primecell";
586 reg = <0x10013000 0x1000>;
587 gpio-controller;
588 interrupt-parent = <&intc_pb11mp>;
589 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 clocks = <&pclk>;
594 clock-names = "apb_pclk";
595 };
596
597 gpio1: gpio@10014000 {
598 compatible = "arm,pl061", "arm,primecell";
599 reg = <0x10014000 0x1000>;
600 gpio-controller;
601 interrupt-parent = <&intc_pb11mp>;
602 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
603 #gpio-cells = <2>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
606 clocks = <&pclk>;
607 clock-names = "apb_pclk";
608 };
609
610 gpio2: gpio@10015000 {
611 compatible = "arm,pl061", "arm,primecell";
612 reg = <0x10015000 0x1000>;
613 gpio-controller;
614 interrupt-parent = <&intc_pb11mp>;
615 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 clocks = <&pclk>;
620 clock-names = "apb_pclk";
621 };
622
623 i2c1: i2c@10016000 {
624 #address-cells = <1>;
625 #size-cells = <0>;
626 compatible = "arm,versatile-i2c";
627 reg = <0x10016000 0x1000>;
628 };
629
630 rtc: rtc@10017000 {
631 compatible = "arm,pl031", "arm,primecell";
632 reg = <0x10017000 0x1000>;
633 interrupt-parent = <&intc_tc11mp>;
634 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&pclk>;
636 clock-names = "apb_pclk";
637 };
638
639 timer45: timer@10018000 {
640 compatible = "arm,sp804", "arm,primecell";
641 reg = <0x10018000 0x1000>;
642 clocks = <&timclk>, <&pclk>;
643 clock-names = "timer", "apb_pclk";
644 status = "disabled";
645 };
646
647 timer67: timer@10019000 {
648 compatible = "arm,sp804", "arm,primecell";
649 reg = <0x10019000 0x1000>;
650 clocks = <&timclk>, <&pclk>;
651 clock-names = "timer", "apb_pclk";
652 status = "disabled";
653 };
654
655
656 clcd@10020000 {
657 compatible = "arm,pl111", "arm,primecell";
658 reg = <0x10020000 0x1000>;
659 interrupt-parent = <&intc_pb11mp>;
660 interrupt-names = "combined";
661 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&oscclk4>, <&pclk>;
663 clock-names = "clcdclk", "apb_pclk";
664 /* 1024x768 16bpp @65MHz works fine */
665 max-memory-bandwidth = <95000000>;
666
667 port {
668 clcd_pads: endpoint {
669 remote-endpoint = <&vga_bridge_in>;
670 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
671 };
672 };
673 };
674
675 /*
676 * This GIC on the Platform Baseboard is cascaded off the
677 * TestChip GIC
678 */
679 intc_pb11mp: interrupt-controller@1e000000 {
680 compatible = "arm,arm11mp-gic";
681 #interrupt-cells = <3>;
682 #address-cells = <1>;
683 interrupt-controller;
684 reg = <0x1e001000 0x1000>,
685 <0x1e000000 0x100>;
686 interrupt-parent = <&intc_tc11mp>;
687 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
688 };
689
690 /* SMSC 9118 ethernet with PHY and EEPROM */
691 ethernet@4e000000 {
692 compatible = "smsc,lan9118", "smsc,lan9115";
693 reg = <0x4e000000 0x10000>;
694 interrupt-parent = <&intc_tc11mp>;
695 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
696 phy-mode = "mii";
697 reg-io-width = <4>;
698 smsc,irq-active-high;
699 smsc,irq-push-pull;
700 vdd33a-supply = <&veth>;
701 vddvario-supply = <&veth>;
702 };
703
704 usb@4f000000 {
705 compatible = "nxp,usb-isp1761";
706 reg = <0x4f000000 0x20000>;
707 interrupt-parent = <&intc_tc11mp>;
708 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
709 port1-otg;
710 };
711 };
712};