tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for Aquantia PHY
4 *
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
6 *
7 * Copyright 2015 Freescale Semiconductor, Inc.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/bitfield.h>
14#include <linux/phy.h>
15
16#include "aquantia.h"
17
18#define PHY_ID_AQ1202 0x03a1b445
19#define PHY_ID_AQ2104 0x03a1b460
20#define PHY_ID_AQR105 0x03a1b4a2
21#define PHY_ID_AQR106 0x03a1b4d0
22#define PHY_ID_AQR107 0x03a1b4e0
23#define PHY_ID_AQCS109 0x03a1b5c2
24#define PHY_ID_AQR405 0x03a1b4b0
25
26#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
27#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
28#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
29#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
30#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
31#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
32
33#define MDIO_AN_VEND_PROV 0xc400
34#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
35#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
36#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
37#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
38#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
39
40#define MDIO_AN_TX_VEND_STATUS1 0xc800
41#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
42#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
43#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
44#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
45#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
46#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
47#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
48#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
49
50#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
51#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
52
53#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
54
55#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
56#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
57
58#define MDIO_AN_RX_LP_STAT1 0xe820
59#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
60#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
61#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
62#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
63#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
64
65#define MDIO_AN_RX_LP_STAT4 0xe823
66#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
67#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
68
69#define MDIO_AN_RX_VEND_STAT3 0xe832
70#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
71
72/* MDIO_MMD_C22EXT */
73#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
74#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
75#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
76#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
77#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
78#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
79#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
80#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
81#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
82#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
83
84/* Vendor specific 1, MDIO_MMD_VEND1 */
85#define VEND1_GLOBAL_FW_ID 0x0020
86#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
87#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
88
89#define VEND1_GLOBAL_RSVD_STAT1 0xc885
90#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
91#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
92
93#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
94#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
95#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
96
97#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
98#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
99
100#define VEND1_GLOBAL_INT_STD_MASK 0xff00
101#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
102#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
103#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
104#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
105#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
106#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
107#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
108#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
109#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
110#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
111#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
112
113#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
114#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
115#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
116#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
117#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
118#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
119#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
120#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
121#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
122
123struct aqr107_hw_stat {
124 const char *name;
125 int reg;
126 int size;
127};
128
129#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
130static const struct aqr107_hw_stat aqr107_hw_stats[] = {
131 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
132 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
133 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
134 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
135 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
136 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
137 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
138 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
139 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
140 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
141};
142#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
143
144struct aqr107_priv {
145 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
146};
147
148static int aqr107_get_sset_count(struct phy_device *phydev)
149{
150 return AQR107_SGMII_STAT_SZ;
151}
152
153static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
154{
155 int i;
156
157 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
158 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
159 ETH_GSTRING_LEN);
160}
161
162static u64 aqr107_get_stat(struct phy_device *phydev, int index)
163{
164 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
165 int len_l = min(stat->size, 16);
166 int len_h = stat->size - len_l;
167 u64 ret;
168 int val;
169
170 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
171 if (val < 0)
172 return U64_MAX;
173
174 ret = val & GENMASK(len_l - 1, 0);
175 if (len_h) {
176 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
177 if (val < 0)
178 return U64_MAX;
179
180 ret += (val & GENMASK(len_h - 1, 0)) << 16;
181 }
182
183 return ret;
184}
185
186static void aqr107_get_stats(struct phy_device *phydev,
187 struct ethtool_stats *stats, u64 *data)
188{
189 struct aqr107_priv *priv = phydev->priv;
190 u64 val;
191 int i;
192
193 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
194 val = aqr107_get_stat(phydev, i);
195 if (val == U64_MAX)
196 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
197 aqr107_hw_stats[i].name);
198 else
199 priv->sgmii_stats[i] += val;
200
201 data[i] = priv->sgmii_stats[i];
202 }
203}
204
205static int aqr_config_aneg(struct phy_device *phydev)
206{
207 bool changed = false;
208 u16 reg;
209 int ret;
210
211 if (phydev->autoneg == AUTONEG_DISABLE)
212 return genphy_c45_pma_setup_forced(phydev);
213
214 ret = genphy_c45_an_config_aneg(phydev);
215 if (ret < 0)
216 return ret;
217 if (ret > 0)
218 changed = true;
219
220 /* Clause 45 has no standardized support for 1000BaseT, therefore
221 * use vendor registers for this mode.
222 */
223 reg = 0;
224 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
225 phydev->advertising))
226 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
227
228 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
229 phydev->advertising))
230 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
231
232 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
233 MDIO_AN_VEND_PROV_1000BASET_HALF |
234 MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
235 if (ret < 0)
236 return ret;
237 if (ret > 0)
238 changed = true;
239
240 return genphy_c45_check_and_restart_aneg(phydev, changed);
241}
242
243static int aqr_config_intr(struct phy_device *phydev)
244{
245 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
246 int err;
247
248 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
249 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
250 if (err < 0)
251 return err;
252
253 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
254 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
255 if (err < 0)
256 return err;
257
258 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
259 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
260 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
261}
262
263static int aqr_ack_interrupt(struct phy_device *phydev)
264{
265 int reg;
266
267 reg = phy_read_mmd(phydev, MDIO_MMD_AN,
268 MDIO_AN_TX_VEND_INT_STATUS2);
269 return (reg < 0) ? reg : 0;
270}
271
272static int aqr_read_status(struct phy_device *phydev)
273{
274 int val;
275
276 if (phydev->autoneg == AUTONEG_ENABLE) {
277 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
278 if (val < 0)
279 return val;
280
281 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
282 phydev->lp_advertising,
283 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
284 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
285 phydev->lp_advertising,
286 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
287 }
288
289 return genphy_c45_read_status(phydev);
290}
291
292static int aqr107_read_downshift_event(struct phy_device *phydev)
293{
294 int val;
295
296 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1);
297 if (val < 0)
298 return val;
299
300 return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT);
301}
302
303static int aqr107_read_rate(struct phy_device *phydev)
304{
305 int val;
306
307 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
308 if (val < 0)
309 return val;
310
311 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
312 case MDIO_AN_TX_VEND_STATUS1_10BASET:
313 phydev->speed = SPEED_10;
314 break;
315 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
316 phydev->speed = SPEED_100;
317 break;
318 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
319 phydev->speed = SPEED_1000;
320 break;
321 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
322 phydev->speed = SPEED_2500;
323 break;
324 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
325 phydev->speed = SPEED_5000;
326 break;
327 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
328 phydev->speed = SPEED_10000;
329 break;
330 default:
331 phydev->speed = SPEED_UNKNOWN;
332 break;
333 }
334
335 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
336 phydev->duplex = DUPLEX_FULL;
337 else
338 phydev->duplex = DUPLEX_HALF;
339
340 return 0;
341}
342
343static int aqr107_read_status(struct phy_device *phydev)
344{
345 int val, ret;
346
347 ret = aqr_read_status(phydev);
348 if (ret)
349 return ret;
350
351 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
352 return 0;
353
354 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
355 if (val < 0)
356 return val;
357
358 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
359 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
360 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
361 phydev->interface = PHY_INTERFACE_MODE_10GKR;
362 break;
363 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
364 phydev->interface = PHY_INTERFACE_MODE_SGMII;
365 break;
366 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
367 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
368 break;
369 default:
370 phydev->interface = PHY_INTERFACE_MODE_NA;
371 break;
372 }
373
374 val = aqr107_read_downshift_event(phydev);
375 if (val <= 0)
376 return val;
377
378 phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n");
379
380 /* Read downshifted rate from vendor register */
381 return aqr107_read_rate(phydev);
382}
383
384static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
385{
386 int val, cnt, enable;
387
388 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
389 if (val < 0)
390 return val;
391
392 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
393 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
394
395 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
396
397 return 0;
398}
399
400static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
401{
402 int val = 0;
403
404 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
405 return -E2BIG;
406
407 if (cnt != DOWNSHIFT_DEV_DISABLE) {
408 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
409 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
410 }
411
412 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
413 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
414 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
415}
416
417static int aqr107_get_tunable(struct phy_device *phydev,
418 struct ethtool_tunable *tuna, void *data)
419{
420 switch (tuna->id) {
421 case ETHTOOL_PHY_DOWNSHIFT:
422 return aqr107_get_downshift(phydev, data);
423 default:
424 return -EOPNOTSUPP;
425 }
426}
427
428static int aqr107_set_tunable(struct phy_device *phydev,
429 struct ethtool_tunable *tuna, const void *data)
430{
431 switch (tuna->id) {
432 case ETHTOOL_PHY_DOWNSHIFT:
433 return aqr107_set_downshift(phydev, *(const u8 *)data);
434 default:
435 return -EOPNOTSUPP;
436 }
437}
438
439/* If we configure settings whilst firmware is still initializing the chip,
440 * then these settings may be overwritten. Therefore make sure chip
441 * initialization has completed. Use presence of the firmware ID as
442 * indicator for initialization having completed.
443 * The chip also provides a "reset completed" bit, but it's cleared after
444 * read. Therefore function would time out if called again.
445 */
446static int aqr107_wait_reset_complete(struct phy_device *phydev)
447{
448 int val, retries = 100;
449
450 do {
451 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
452 if (val < 0)
453 return val;
454 msleep(20);
455 } while (!val && --retries);
456
457 return val ? 0 : -ETIMEDOUT;
458}
459
460static void aqr107_chip_info(struct phy_device *phydev)
461{
462 u8 fw_major, fw_minor, build_id, prov_id;
463 int val;
464
465 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
466 if (val < 0)
467 return;
468
469 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
470 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
471
472 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
473 if (val < 0)
474 return;
475
476 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
477 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
478
479 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
480 fw_major, fw_minor, build_id, prov_id);
481}
482
483static int aqr107_config_init(struct phy_device *phydev)
484{
485 int ret;
486
487 /* Check that the PHY interface type is compatible */
488 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
489 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
490 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
491 phydev->interface != PHY_INTERFACE_MODE_10GKR)
492 return -ENODEV;
493
494 ret = aqr107_wait_reset_complete(phydev);
495 if (!ret)
496 aqr107_chip_info(phydev);
497
498 /* ensure that a latched downshift event is cleared */
499 aqr107_read_downshift_event(phydev);
500
501 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
502}
503
504static int aqcs109_config_init(struct phy_device *phydev)
505{
506 int ret;
507
508 /* Check that the PHY interface type is compatible */
509 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
510 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
511 return -ENODEV;
512
513 ret = aqr107_wait_reset_complete(phydev);
514 if (!ret)
515 aqr107_chip_info(phydev);
516
517 /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
518 * PMA speed ability bits are the same for all members of the family,
519 * AQCS109 however supports speeds up to 2.5G only.
520 */
521 ret = phy_set_max_speed(phydev, SPEED_2500);
522 if (ret)
523 return ret;
524
525 /* ensure that a latched downshift event is cleared */
526 aqr107_read_downshift_event(phydev);
527
528 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
529}
530
531static void aqr107_link_change_notify(struct phy_device *phydev)
532{
533 u8 fw_major, fw_minor;
534 bool downshift, short_reach, afr;
535 int mode, val;
536
537 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
538 return;
539
540 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
541 /* call failed or link partner is no Aquantia PHY */
542 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
543 return;
544
545 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
546 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
547
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
549 if (val < 0)
550 return;
551
552 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
553 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
554
555 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
556 if (val < 0)
557 return;
558
559 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
560
561 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
562 fw_major, fw_minor,
563 short_reach ? ", short reach mode" : "",
564 downshift ? ", fast-retrain downshift advertised" : "",
565 afr ? ", fast reframe advertised" : "");
566
567 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
568 if (val < 0)
569 return;
570
571 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
572 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
573 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
574}
575
576static int aqr107_suspend(struct phy_device *phydev)
577{
578 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
579 MDIO_CTRL1_LPOWER);
580}
581
582static int aqr107_resume(struct phy_device *phydev)
583{
584 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
585 MDIO_CTRL1_LPOWER);
586}
587
588static int aqr107_probe(struct phy_device *phydev)
589{
590 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
591 sizeof(struct aqr107_priv), GFP_KERNEL);
592 if (!phydev->priv)
593 return -ENOMEM;
594
595 return aqr_hwmon_probe(phydev);
596}
597
598static struct phy_driver aqr_driver[] = {
599{
600 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
601 .name = "Aquantia AQ1202",
602 .config_aneg = aqr_config_aneg,
603 .config_intr = aqr_config_intr,
604 .ack_interrupt = aqr_ack_interrupt,
605 .read_status = aqr_read_status,
606},
607{
608 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
609 .name = "Aquantia AQ2104",
610 .config_aneg = aqr_config_aneg,
611 .config_intr = aqr_config_intr,
612 .ack_interrupt = aqr_ack_interrupt,
613 .read_status = aqr_read_status,
614},
615{
616 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
617 .name = "Aquantia AQR105",
618 .config_aneg = aqr_config_aneg,
619 .config_intr = aqr_config_intr,
620 .ack_interrupt = aqr_ack_interrupt,
621 .read_status = aqr_read_status,
622},
623{
624 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
625 .name = "Aquantia AQR106",
626 .config_aneg = aqr_config_aneg,
627 .config_intr = aqr_config_intr,
628 .ack_interrupt = aqr_ack_interrupt,
629 .read_status = aqr_read_status,
630},
631{
632 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
633 .name = "Aquantia AQR107",
634 .probe = aqr107_probe,
635 .config_init = aqr107_config_init,
636 .config_aneg = aqr_config_aneg,
637 .config_intr = aqr_config_intr,
638 .ack_interrupt = aqr_ack_interrupt,
639 .read_status = aqr107_read_status,
640 .get_tunable = aqr107_get_tunable,
641 .set_tunable = aqr107_set_tunable,
642 .suspend = aqr107_suspend,
643 .resume = aqr107_resume,
644 .get_sset_count = aqr107_get_sset_count,
645 .get_strings = aqr107_get_strings,
646 .get_stats = aqr107_get_stats,
647 .link_change_notify = aqr107_link_change_notify,
648},
649{
650 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
651 .name = "Aquantia AQCS109",
652 .probe = aqr107_probe,
653 .config_init = aqcs109_config_init,
654 .config_aneg = aqr_config_aneg,
655 .config_intr = aqr_config_intr,
656 .ack_interrupt = aqr_ack_interrupt,
657 .read_status = aqr107_read_status,
658 .get_tunable = aqr107_get_tunable,
659 .set_tunable = aqr107_set_tunable,
660 .suspend = aqr107_suspend,
661 .resume = aqr107_resume,
662 .get_sset_count = aqr107_get_sset_count,
663 .get_strings = aqr107_get_strings,
664 .get_stats = aqr107_get_stats,
665 .link_change_notify = aqr107_link_change_notify,
666},
667{
668 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
669 .name = "Aquantia AQR405",
670 .config_aneg = aqr_config_aneg,
671 .config_intr = aqr_config_intr,
672 .ack_interrupt = aqr_ack_interrupt,
673 .read_status = aqr_read_status,
674},
675};
676
677module_phy_driver(aqr_driver);
678
679static struct mdio_device_id __maybe_unused aqr_tbl[] = {
680 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
681 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
682 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
683 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
684 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
685 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
686 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
687 { }
688};
689
690MODULE_DEVICE_TABLE(mdio, aqr_tbl);
691
692MODULE_DESCRIPTION("Aquantia PHY driver");
693MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
694MODULE_LICENSE("GPL v2");