tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / drivers / irqchip / Kconfig
at v5.2-rc4 462 lines 9.3 kB view raw
1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_MULTI_HANDLER 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 select PM_CLK 19 20config ARM_GIC_MAX_NR 21 int 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select PCI_MSI 30 31config GIC_NON_BANKED 32 bool 33 34config ARM_GIC_V3 35 bool 36 select GENERIC_IRQ_MULTI_HANDLER 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 40 41config ARM_GIC_V3_ITS 42 bool 43 select GENERIC_MSI_IRQ_DOMAIN 44 default ARM_GIC_V3 45 46config ARM_GIC_V3_ITS_PCI 47 bool 48 depends on ARM_GIC_V3_ITS 49 depends on PCI 50 depends on PCI_MSI 51 default ARM_GIC_V3_ITS 52 53config ARM_GIC_V3_ITS_FSL_MC 54 bool 55 depends on ARM_GIC_V3_ITS 56 depends on FSL_MC_BUS 57 default ARM_GIC_V3_ITS 58 59config ARM_NVIC 60 bool 61 select IRQ_DOMAIN_HIERARCHY 62 select GENERIC_IRQ_CHIP 63 64config ARM_VIC 65 bool 66 select IRQ_DOMAIN 67 select GENERIC_IRQ_MULTI_HANDLER 68 69config ARM_VIC_NR 70 int 71 default 4 if ARCH_S5PV210 72 default 2 73 depends on ARM_VIC 74 help 75 The maximum number of VICs available in the system, for 76 power management. 77 78config ARMADA_370_XP_IRQ 79 bool 80 select GENERIC_IRQ_CHIP 81 select PCI_MSI if PCI 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 83 84config ALPINE_MSI 85 bool 86 depends on PCI 87 select PCI_MSI 88 select GENERIC_IRQ_CHIP 89 90config ATMEL_AIC_IRQ 91 bool 92 select GENERIC_IRQ_CHIP 93 select IRQ_DOMAIN 94 select GENERIC_IRQ_MULTI_HANDLER 95 select SPARSE_IRQ 96 97config ATMEL_AIC5_IRQ 98 bool 99 select GENERIC_IRQ_CHIP 100 select IRQ_DOMAIN 101 select GENERIC_IRQ_MULTI_HANDLER 102 select SPARSE_IRQ 103 104config I8259 105 bool 106 select IRQ_DOMAIN 107 108config BCM6345_L1_IRQ 109 bool 110 select GENERIC_IRQ_CHIP 111 select IRQ_DOMAIN 112 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 113 114config BCM7038_L1_IRQ 115 bool 116 select GENERIC_IRQ_CHIP 117 select IRQ_DOMAIN 118 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 119 120config BCM7120_L2_IRQ 121 bool 122 select GENERIC_IRQ_CHIP 123 select IRQ_DOMAIN 124 125config BRCMSTB_L2_IRQ 126 bool 127 select GENERIC_IRQ_CHIP 128 select IRQ_DOMAIN 129 130config DAVINCI_AINTC 131 bool 132 select GENERIC_IRQ_CHIP 133 select IRQ_DOMAIN 134 135config DAVINCI_CP_INTC 136 bool 137 select GENERIC_IRQ_CHIP 138 select IRQ_DOMAIN 139 140config DW_APB_ICTL 141 bool 142 select GENERIC_IRQ_CHIP 143 select IRQ_DOMAIN 144 145config FARADAY_FTINTC010 146 bool 147 select IRQ_DOMAIN 148 select GENERIC_IRQ_MULTI_HANDLER 149 select SPARSE_IRQ 150 151config HISILICON_IRQ_MBIGEN 152 bool 153 select ARM_GIC_V3 154 select ARM_GIC_V3_ITS 155 156config IMGPDC_IRQ 157 bool 158 select GENERIC_IRQ_CHIP 159 select IRQ_DOMAIN 160 161config IXP4XX_IRQ 162 bool 163 select IRQ_DOMAIN 164 select GENERIC_IRQ_MULTI_HANDLER 165 select SPARSE_IRQ 166 167config MADERA_IRQ 168 tristate 169 170config IRQ_MIPS_CPU 171 bool 172 select GENERIC_IRQ_CHIP 173 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING 174 select IRQ_DOMAIN 175 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI 176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 177 178config CLPS711X_IRQCHIP 179 bool 180 depends on ARCH_CLPS711X 181 select IRQ_DOMAIN 182 select GENERIC_IRQ_MULTI_HANDLER 183 select SPARSE_IRQ 184 default y 185 186config OMPIC 187 bool 188 189config OR1K_PIC 190 bool 191 select IRQ_DOMAIN 192 193config OMAP_IRQCHIP 194 bool 195 select GENERIC_IRQ_CHIP 196 select IRQ_DOMAIN 197 198config ORION_IRQCHIP 199 bool 200 select IRQ_DOMAIN 201 select GENERIC_IRQ_MULTI_HANDLER 202 203config PIC32_EVIC 204 bool 205 select GENERIC_IRQ_CHIP 206 select IRQ_DOMAIN 207 208config JCORE_AIC 209 bool "J-Core integrated AIC" if COMPILE_TEST 210 depends on OF 211 select IRQ_DOMAIN 212 help 213 Support for the J-Core integrated AIC. 214 215config RDA_INTC 216 bool 217 select IRQ_DOMAIN 218 219config RENESAS_INTC_IRQPIN 220 bool 221 select IRQ_DOMAIN 222 223config RENESAS_IRQC 224 bool 225 select GENERIC_IRQ_CHIP 226 select IRQ_DOMAIN 227 228config ST_IRQCHIP 229 bool 230 select REGMAP 231 select MFD_SYSCON 232 help 233 Enables SysCfg Controlled IRQs on STi based platforms. 234 235config TANGO_IRQ 236 bool 237 select IRQ_DOMAIN 238 select GENERIC_IRQ_CHIP 239 240config TB10X_IRQC 241 bool 242 select IRQ_DOMAIN 243 select GENERIC_IRQ_CHIP 244 245config TS4800_IRQ 246 tristate "TS-4800 IRQ controller" 247 select IRQ_DOMAIN 248 depends on HAS_IOMEM 249 depends on SOC_IMX51 || COMPILE_TEST 250 help 251 Support for the TS-4800 FPGA IRQ controller 252 253config VERSATILE_FPGA_IRQ 254 bool 255 select IRQ_DOMAIN 256 257config VERSATILE_FPGA_IRQ_NR 258 int 259 default 4 260 depends on VERSATILE_FPGA_IRQ 261 262config XTENSA_MX 263 bool 264 select IRQ_DOMAIN 265 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 266 267config XILINX_INTC 268 bool 269 select IRQ_DOMAIN 270 271config IRQ_CROSSBAR 272 bool 273 help 274 Support for a CROSSBAR ip that precedes the main interrupt controller. 275 The primary irqchip invokes the crossbar's callback which inturn allocates 276 a free irq and configures the IP. Thus the peripheral interrupts are 277 routed to one of the free irqchip interrupt lines. 278 279config KEYSTONE_IRQ 280 tristate "Keystone 2 IRQ controller IP" 281 depends on ARCH_KEYSTONE 282 help 283 Support for Texas Instruments Keystone 2 IRQ controller IP which 284 is part of the Keystone 2 IPC mechanism 285 286config MIPS_GIC 287 bool 288 select GENERIC_IRQ_IPI 289 select IRQ_DOMAIN_HIERARCHY 290 select MIPS_CM 291 292config INGENIC_IRQ 293 bool 294 depends on MACH_INGENIC 295 default y 296 297config RENESAS_H8300H_INTC 298 bool 299 select IRQ_DOMAIN 300 301config RENESAS_H8S_INTC 302 bool 303 select IRQ_DOMAIN 304 305config IMX_GPCV2 306 bool 307 select IRQ_DOMAIN 308 help 309 Enables the wakeup IRQs for IMX platforms with GPCv2 block 310 311config IRQ_MXS 312 def_bool y if MACH_ASM9260 || ARCH_MXS 313 select IRQ_DOMAIN 314 select STMP_DEVICE 315 316config MSCC_OCELOT_IRQ 317 bool 318 select IRQ_DOMAIN 319 select GENERIC_IRQ_CHIP 320 321config MVEBU_GICP 322 bool 323 324config MVEBU_ICU 325 bool 326 327config MVEBU_ODMI 328 bool 329 select GENERIC_MSI_IRQ_DOMAIN 330 331config MVEBU_PIC 332 bool 333 334config MVEBU_SEI 335 bool 336 337config LS_SCFG_MSI 338 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 339 depends on PCI && PCI_MSI 340 341config PARTITION_PERCPU 342 bool 343 344config EZNPS_GIC 345 bool "NPS400 Global Interrupt Manager (GIM)" 346 depends on ARC || (COMPILE_TEST && !64BIT) 347 select IRQ_DOMAIN 348 help 349 Support the EZchip NPS400 global interrupt controller 350 351config STM32_EXTI 352 bool 353 select IRQ_DOMAIN 354 select GENERIC_IRQ_CHIP 355 356config QCOM_IRQ_COMBINER 357 bool "QCOM IRQ combiner support" 358 depends on ARCH_QCOM && ACPI 359 select IRQ_DOMAIN_HIERARCHY 360 help 361 Say yes here to add support for the IRQ combiner devices embedded 362 in Qualcomm Technologies chips. 363 364config IRQ_UNIPHIER_AIDET 365 bool "UniPhier AIDET support" if COMPILE_TEST 366 depends on ARCH_UNIPHIER || COMPILE_TEST 367 default ARCH_UNIPHIER 368 select IRQ_DOMAIN_HIERARCHY 369 help 370 Support for the UniPhier AIDET (ARM Interrupt Detector). 371 372config MESON_IRQ_GPIO 373 bool "Meson GPIO Interrupt Multiplexer" 374 depends on ARCH_MESON 375 select IRQ_DOMAIN_HIERARCHY 376 help 377 Support Meson SoC Family GPIO Interrupt Multiplexer 378 379config GOLDFISH_PIC 380 bool "Goldfish programmable interrupt controller" 381 depends on MIPS && (GOLDFISH || COMPILE_TEST) 382 select IRQ_DOMAIN 383 help 384 Say yes here to enable Goldfish interrupt controller driver used 385 for Goldfish based virtual platforms. 386 387config QCOM_PDC 388 bool "QCOM PDC" 389 depends on ARCH_QCOM 390 select IRQ_DOMAIN_HIERARCHY 391 help 392 Power Domain Controller driver to manage and configure wakeup 393 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 394 395config CSKY_MPINTC 396 bool "C-SKY Multi Processor Interrupt Controller" 397 depends on CSKY 398 help 399 Say yes here to enable C-SKY SMP interrupt controller driver used 400 for C-SKY SMP system. 401 In fact it's not mmio map in hw and it use ld/st to visit the 402 controller's register inside CPU. 403 404config CSKY_APB_INTC 405 bool "C-SKY APB Interrupt Controller" 406 depends on CSKY 407 help 408 Say yes here to enable C-SKY APB interrupt controller driver used 409 by C-SKY single core SOC system. It use mmio map apb-bus to visit 410 the controller's register. 411 412config IMX_IRQSTEER 413 bool "i.MX IRQSTEER support" 414 depends on ARCH_MXC || COMPILE_TEST 415 default ARCH_MXC 416 select IRQ_DOMAIN 417 help 418 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 419 420config LS1X_IRQ 421 bool "Loongson-1 Interrupt Controller" 422 depends on MACH_LOONGSON32 423 default y 424 select IRQ_DOMAIN 425 select GENERIC_IRQ_CHIP 426 help 427 Support for the Loongson-1 platform Interrupt Controller. 428 429config TI_SCI_INTR_IRQCHIP 430 bool 431 depends on TI_SCI_PROTOCOL 432 select IRQ_DOMAIN_HIERARCHY 433 help 434 This enables the irqchip driver support for K3 Interrupt router 435 over TI System Control Interface available on some new TI's SoCs. 436 If you wish to use interrupt router irq resources managed by the 437 TI System Controller, say Y here. Otherwise, say N. 438 439config TI_SCI_INTA_IRQCHIP 440 bool 441 depends on TI_SCI_PROTOCOL 442 select IRQ_DOMAIN_HIERARCHY 443 select TI_SCI_INTA_MSI_DOMAIN 444 help 445 This enables the irqchip driver support for K3 Interrupt aggregator 446 over TI System Control Interface available on some new TI's SoCs. 447 If you wish to use interrupt aggregator irq resources managed by the 448 TI System Controller, say Y here. Otherwise, say N. 449 450endmenu 451 452config SIFIVE_PLIC 453 bool "SiFive Platform-Level Interrupt Controller" 454 depends on RISCV 455 help 456 This enables support for the PLIC chip found in SiFive (and 457 potentially other) RISC-V systems. The PLIC controls devices 458 interrupts and connects them to each core's local interrupt 459 controller. Aside from timer and software interrupts, all other 460 interrupt sources are subordinate to the PLIC. 461 462 If you don't know what to do here, say Y.