tjh.dev
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1MediaTek T-PHY binding
2--------------------------
3
4T-phy controller supports physical layer functionality for a number of
5controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
6
7Required properties (controller (parent) node):
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
15 "mediatek,generic-tphy-v2" on mt2712 instead.
16 - clocks : (deprecated, use port's clocks instead) a list of phandle +
17 clock-specifier pairs, one for each entry in clock-names
18 - clock-names : (deprecated, use port's one instead) must contain
19 "u3phya_ref": for reference clock of usb3.0 analog phy.
20
21Required nodes : a sub-node is required for each port the controller
22 provides. Address range information including the usual
23 'reg' property is used inside these nodes to describe
24 the controller's topology.
25
26Optional properties (controller (parent) node):
27 - reg : offset and length of register shared by multiple ports,
28 exclude port's private register. It is needed on mt2701
29 and mt8173, but not on mt2712.
30 - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
31 calibrate
32 - mediatek,src-coef : coefficient for slew rate calibrate, depends on
33 SoC process
34
35Required properties (port (child) node):
36- reg : address and length of the register set for the port.
37- clocks : a list of phandle + clock-specifier pairs, one for each
38 entry in clock-names
39- clock-names : must contain
40 "ref": 48M reference clock for HighSpeed analog phy; and 26M
41 reference clock for SuperSpeed analog phy, sometimes is
42 24M, 25M or 27M, depended on platform.
43- #phy-cells : should be 1 (See second example)
44 cell after port phandle is phy type from:
45 - PHY_TYPE_USB2
46 - PHY_TYPE_USB3
47 - PHY_TYPE_PCIE
48 - PHY_TYPE_SATA
49
50Optional properties (PHY_TYPE_USB2 port (child) node):
51- mediatek,eye-src : u32, the value of slew rate calibrate
52- mediatek,eye-vrt : u32, the selection of VRT reference voltage
53- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
54- mediatek,bc12 : bool, enable BC12 of u2phy if support it
55
56Example:
57
58u3phy: usb-phy@11290000 {
59 compatible = "mediatek,mt8173-u3phy";
60 reg = <0 0x11290000 0 0x800>;
61 #address-cells = <2>;
62 #size-cells = <2>;
63 ranges;
64
65 u2port0: usb-phy@11290800 {
66 reg = <0 0x11290800 0 0x100>;
67 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
68 clock-names = "ref";
69 #phy-cells = <1>;
70 };
71
72 u3port0: usb-phy@11290900 {
73 reg = <0 0x11290800 0 0x700>;
74 clocks = <&clk26m>;
75 clock-names = "ref";
76 #phy-cells = <1>;
77 };
78
79 u2port1: usb-phy@11291000 {
80 reg = <0 0x11291000 0 0x100>;
81 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
82 clock-names = "ref";
83 #phy-cells = <1>;
84 };
85};
86
87Specifying phy control of devices
88---------------------------------
89
90Device nodes should specify the configuration required in their "phys"
91property, containing a phandle to the phy port node and a device type;
92phy-names for each port are optional.
93
94Example:
95
96#include <dt-bindings/phy/phy.h>
97
98usb30: usb@11270000 {
99 ...
100 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
101 phy-names = "usb2-0", "usb3-0";
102 ...
103};
104
105
106Layout differences of banks between mt8173/mt2701 and mt2712
107-------------------------------------------------------------
108mt8173 and mt2701:
109port offset bank
110shared 0x0000 SPLLC
111 0x0100 FMREG
112u2 port0 0x0800 U2PHY_COM
113u3 port0 0x0900 U3PHYD
114 0x0a00 U3PHYD_BANK2
115 0x0b00 U3PHYA
116 0x0c00 U3PHYA_DA
117u2 port1 0x1000 U2PHY_COM
118u3 port1 0x1100 U3PHYD
119 0x1200 U3PHYD_BANK2
120 0x1300 U3PHYA
121 0x1400 U3PHYA_DA
122u2 port2 0x1800 U2PHY_COM
123 ...
124
125mt2712:
126port offset bank
127u2 port0 0x0000 MISC
128 0x0100 FMREG
129 0x0300 U2PHY_COM
130u3 port0 0x0700 SPLLC
131 0x0800 CHIP
132 0x0900 U3PHYD
133 0x0a00 U3PHYD_BANK2
134 0x0b00 U3PHYA
135 0x0c00 U3PHYA_DA
136u2 port1 0x1000 MISC
137 0x1100 FMREG
138 0x1300 U2PHY_COM
139u3 port1 0x1700 SPLLC
140 0x1800 CHIP
141 0x1900 U3PHYD
142 0x1a00 U3PHYD_BANK2
143 0x1b00 U3PHYA
144 0x1c00 U3PHYA_DA
145u2 port2 0x2000 MISC
146 ...
147
148 SPLLC shared by u3 ports and FMREG shared by u2 ports on
149mt8173/mt2701 are put back into each port; a new bank MISC for
150u2 ports and CHIP for u3 ports are added on mt2712.