tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23#define FDMI_DID 0xfffffaU
24#define NameServer_DID 0xfffffcU
25#define SCR_DID 0xfffffdU
26#define Fabric_DID 0xfffffeU
27#define Bcast_DID 0xffffffU
28#define Mask_DID 0xffffffU
29#define CT_DID_MASK 0xffff00U
30#define Fabric_DID_MASK 0xfff000U
31#define WELL_KNOWN_DID_MASK 0xfffff0U
32
33#define PT2PT_LocalID 1
34#define PT2PT_RemoteID 2
35
36#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38#define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44#define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71/* vendor ID used in SCSI netlink calls */
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74#define FW_REV_STR_SIZE 32
75/* Common Transport structures and definitions */
76
77union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93};
94
95/* FC4 Feature bits for RFF_ID */
96#define FC4_FEATURE_TARGET 0x1
97#define FC4_FEATURE_INIT 0x2
98#define FC4_FEATURE_NVME_DISC 0x4
99
100struct lpfc_sli_ct_request {
101 /* Structure is in Big Endian format */
102 union CtRevisionId RevisionId;
103 uint8_t FsType;
104 uint8_t FsSubType;
105 uint8_t Options;
106 uint8_t Rsrvd1;
107 union CtCommandResponse CommandResponse;
108 uint8_t Rsrvd2;
109 uint8_t ReasonCode;
110 uint8_t Explanation;
111 uint8_t VendorUnique;
112#define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
113
114 union {
115 uint32_t PortID;
116 struct gid {
117 uint8_t PortType; /* for GID_PT requests */
118#define GID_PT_N_PORT 1
119 uint8_t DomainScope;
120 uint8_t AreaScope;
121 uint8_t Fc4Type; /* for GID_FT requests */
122 } gid;
123 struct gid_ff {
124 uint8_t Flags;
125 uint8_t DomainScope;
126 uint8_t AreaScope;
127 uint8_t rsvd1;
128 uint8_t rsvd2;
129 uint8_t rsvd3;
130 uint8_t Fc4FBits;
131 uint8_t Fc4Type;
132 } gid_ff;
133 struct rft {
134 uint32_t PortId; /* For RFT_ID requests */
135
136#ifdef __BIG_ENDIAN_BITFIELD
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
139 uint32_t fcpReg:1; /* Type 8 */
140 uint32_t rsvd2:2;
141 uint32_t ipReg:1; /* Type 5 */
142 uint32_t rsvd3:5;
143#else /* __LITTLE_ENDIAN_BITFIELD */
144 uint32_t rsvd0:16;
145 uint32_t fcpReg:1; /* Type 8 */
146 uint32_t rsvd1:7;
147 uint32_t rsvd3:5;
148 uint32_t ipReg:1; /* Type 5 */
149 uint32_t rsvd2:2;
150#endif
151
152 uint32_t rsvd[7];
153 } rft;
154 struct rnn {
155 uint32_t PortId; /* For RNN_ID requests */
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn { /* For RSNN_ID requests */
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id { /* For DA_ID requests */
164 uint32_t port_id;
165 } da_id;
166 struct rspn { /* For RSPN_ID requests */
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183#define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code; /* type=8 for FCP */
189 } rff;
190 } un;
191};
192
193#define LPFC_MAX_CT_SIZE (60 * 4096)
194
195#define SLI_CT_REVISION 1
196#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198#define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202#define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217/*
218 * FsType Definitions
219 */
220
221#define SLI_CT_MANAGEMENT_SERVICE 0xFA
222#define SLI_CT_TIME_SERVICE 0xFB
223#define SLI_CT_DIRECTORY_SERVICE 0xFC
224#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226/*
227 * Directory Service Subtypes
228 */
229
230#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232/*
233 * Response Codes
234 */
235
236#define SLI_CT_RESPONSE_FS_RJT 0x8001
237#define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239/*
240 * Reason Codes
241 */
242
243#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244#define SLI_CT_INVALID_COMMAND 0x01
245#define SLI_CT_INVALID_VERSION 0x02
246#define SLI_CT_LOGICAL_ERROR 0x03
247#define SLI_CT_INVALID_IU_SIZE 0x04
248#define SLI_CT_LOGICAL_BUSY 0x05
249#define SLI_CT_PROTOCOL_ERROR 0x07
250#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259#define SLI_CT_VENDOR_UNIQUE 0xff
260
261/*
262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
263 */
264
265#define SLI_CT_NO_PORT_ID 0x01
266#define SLI_CT_NO_PORT_NAME 0x02
267#define SLI_CT_NO_NODE_NAME 0x03
268#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269#define SLI_CT_NO_IP_ADDRESS 0x05
270#define SLI_CT_NO_IPA 0x06
271#define SLI_CT_NO_FC4_TYPES 0x07
272#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274#define SLI_CT_NO_PORT_TYPE 0x0A
275#define SLI_CT_ACCESS_DENIED 0x10
276#define SLI_CT_INVALID_PORT_ID 0x11
277#define SLI_CT_DATABASE_EMPTY 0x12
278
279/*
280 * Name Server Command Codes
281 */
282
283#define SLI_CTNS_GA_NXT 0x0100
284#define SLI_CTNS_GPN_ID 0x0112
285#define SLI_CTNS_GNN_ID 0x0113
286#define SLI_CTNS_GCS_ID 0x0114
287#define SLI_CTNS_GFT_ID 0x0117
288#define SLI_CTNS_GSPN_ID 0x0118
289#define SLI_CTNS_GPT_ID 0x011A
290#define SLI_CTNS_GFF_ID 0x011F
291#define SLI_CTNS_GID_PN 0x0121
292#define SLI_CTNS_GID_NN 0x0131
293#define SLI_CTNS_GIP_NN 0x0135
294#define SLI_CTNS_GIPA_NN 0x0136
295#define SLI_CTNS_GSNN_NN 0x0139
296#define SLI_CTNS_GNN_IP 0x0153
297#define SLI_CTNS_GIPA_IP 0x0156
298#define SLI_CTNS_GID_FT 0x0171
299#define SLI_CTNS_GID_FF 0x01F1
300#define SLI_CTNS_GID_PT 0x01A1
301#define SLI_CTNS_RPN_ID 0x0212
302#define SLI_CTNS_RNN_ID 0x0213
303#define SLI_CTNS_RCS_ID 0x0214
304#define SLI_CTNS_RFT_ID 0x0217
305#define SLI_CTNS_RSPN_ID 0x0218
306#define SLI_CTNS_RPT_ID 0x021A
307#define SLI_CTNS_RFF_ID 0x021F
308#define SLI_CTNS_RIP_NN 0x0235
309#define SLI_CTNS_RIPA_NN 0x0236
310#define SLI_CTNS_RSNN_NN 0x0239
311#define SLI_CTNS_DA_ID 0x0300
312
313/*
314 * Port Types
315 */
316
317#define SLI_CTPT_N_PORT 0x01
318#define SLI_CTPT_NL_PORT 0x02
319#define SLI_CTPT_FNL_PORT 0x03
320#define SLI_CTPT_IP 0x04
321#define SLI_CTPT_FCP 0x08
322#define SLI_CTPT_NVME 0x28
323#define SLI_CTPT_NX_PORT 0x7F
324#define SLI_CTPT_F_PORT 0x81
325#define SLI_CTPT_FL_PORT 0x82
326#define SLI_CTPT_E_PORT 0x84
327
328#define SLI_CT_LAST_ENTRY 0x80000000
329
330/* Fibre Channel Service Parameter definitions */
331
332#define FC_PH_4_0 6 /* FC-PH version 4.0 */
333#define FC_PH_4_1 7 /* FC-PH version 4.1 */
334#define FC_PH_4_2 8 /* FC-PH version 4.2 */
335#define FC_PH_4_3 9 /* FC-PH version 4.3 */
336
337#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
338#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
339#define FC_PH3 0x20 /* FC-PH-3 version */
340
341#define FF_FRAME_SIZE 2048
342
343struct lpfc_name {
344 union {
345 struct {
346#ifdef __BIG_ENDIAN_BITFIELD
347 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
348 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
349 8:11 of IEEE ext */
350#else /* __LITTLE_ENDIAN_BITFIELD */
351 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
352 8:11 of IEEE ext */
353 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
354#endif
355
356#define NAME_IEEE 0x1 /* IEEE name - nameType */
357#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
358#define NAME_FC_TYPE 0x3 /* FC native name type */
359#define NAME_IP_TYPE 0x4 /* IP address */
360#define NAME_CCITT_TYPE 0xC
361#define NAME_CCITT_GR_TYPE 0xE
362 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
363 extended Lsb */
364 uint8_t IEEE[6]; /* FC IEEE address */
365 } s;
366 uint8_t wwn[8];
367 uint64_t name;
368 } u;
369};
370
371struct csp {
372 uint8_t fcphHigh; /* FC Word 0, byte 0 */
373 uint8_t fcphLow;
374 uint8_t bbCreditMsb;
375 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
376
377/*
378 * Word 1 Bit 31 in common service parameter is overloaded.
379 * Word 1 Bit 31 in FLOGI request is multiple NPort request
380 * Word 1 Bit 31 in FLOGI response is clean address bit
381 */
382#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
383/*
384 * Word 1 Bit 30 in common service parameter is overloaded.
385 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
386 * Word 1 Bit 30 in PLOGI request is random offset
387 */
388#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
389/*
390 * Word 1 Bit 29 in common service parameter is overloaded.
391 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
392 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
393 */
394#define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
395#ifdef __BIG_ENDIAN_BITFIELD
396 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
397 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
398 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
399 uint16_t fPort:1; /* FC Word 1, bit 28 */
400 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
401 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
402 uint16_t multicast:1; /* FC Word 1, bit 25 */
403 uint16_t broadcast:1; /* FC Word 1, bit 24 */
404
405 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
406 uint16_t simplex:1; /* FC Word 1, bit 22 */
407 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
408 uint16_t dhd:1; /* FC Word 1, bit 18 */
409 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
410 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
411#else /* __LITTLE_ENDIAN_BITFIELD */
412 uint16_t broadcast:1; /* FC Word 1, bit 24 */
413 uint16_t multicast:1; /* FC Word 1, bit 25 */
414 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
415 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
416 uint16_t fPort:1; /* FC Word 1, bit 28 */
417 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
418 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
419 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
420
421 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
422 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
423 uint16_t dhd:1; /* FC Word 1, bit 18 */
424 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
425 uint16_t simplex:1; /* FC Word 1, bit 22 */
426 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
427#endif
428
429 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
430 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
431 union {
432 struct {
433 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
434
435 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
436 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
437
438 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
439 } nPort;
440 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
441 } w2;
442
443 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
444};
445
446struct class_parms {
447#ifdef __BIG_ENDIAN_BITFIELD
448 uint8_t classValid:1; /* FC Word 0, bit 31 */
449 uint8_t intermix:1; /* FC Word 0, bit 30 */
450 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
451 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
452 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
453 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
454#else /* __LITTLE_ENDIAN_BITFIELD */
455 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
456 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
457 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
458 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
459 uint8_t intermix:1; /* FC Word 0, bit 30 */
460 uint8_t classValid:1; /* FC Word 0, bit 31 */
461
462#endif
463
464 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
465
466#ifdef __BIG_ENDIAN_BITFIELD
467 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
468 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
469 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
470 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
471 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
472#else /* __LITTLE_ENDIAN_BITFIELD */
473 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
474 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
475 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
476 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
477 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
478#endif
479
480 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
481
482#ifdef __BIG_ENDIAN_BITFIELD
483 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
484 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
485 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
486 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
487 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
488 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
489#else /* __LITTLE_ENDIAN_BITFIELD */
490 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
491 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
492 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
493 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
494 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
495 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
496#endif
497
498 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
499 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
500 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
501
502 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
503 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
504 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
505 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
506
507 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
508 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
509 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
510 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
511};
512
513#define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/
514
515struct serv_parm { /* Structure is in Big Endian format */
516 struct csp cmn;
517 struct lpfc_name portName;
518 struct lpfc_name nodeName;
519 struct class_parms cls1;
520 struct class_parms cls2;
521 struct class_parms cls3;
522 struct class_parms cls4;
523 union {
524 uint8_t vendorVersion[16];
525 struct {
526 uint32_t vid;
527#define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
528 uint32_t flags;
529#define LPFC_VV_SUPPRESS_RSP 1
530 } vv;
531 } un;
532};
533
534/*
535 * Virtual Fabric Tagging Header
536 */
537struct fc_vft_header {
538 uint32_t word0;
539#define fc_vft_hdr_r_ctl_SHIFT 24
540#define fc_vft_hdr_r_ctl_MASK 0xFF
541#define fc_vft_hdr_r_ctl_WORD word0
542#define fc_vft_hdr_ver_SHIFT 22
543#define fc_vft_hdr_ver_MASK 0x3
544#define fc_vft_hdr_ver_WORD word0
545#define fc_vft_hdr_type_SHIFT 18
546#define fc_vft_hdr_type_MASK 0xF
547#define fc_vft_hdr_type_WORD word0
548#define fc_vft_hdr_e_SHIFT 16
549#define fc_vft_hdr_e_MASK 0x1
550#define fc_vft_hdr_e_WORD word0
551#define fc_vft_hdr_priority_SHIFT 13
552#define fc_vft_hdr_priority_MASK 0x7
553#define fc_vft_hdr_priority_WORD word0
554#define fc_vft_hdr_vf_id_SHIFT 1
555#define fc_vft_hdr_vf_id_MASK 0xFFF
556#define fc_vft_hdr_vf_id_WORD word0
557 uint32_t word1;
558#define fc_vft_hdr_hopct_SHIFT 24
559#define fc_vft_hdr_hopct_MASK 0xFF
560#define fc_vft_hdr_hopct_WORD word1
561};
562
563#include <uapi/scsi/fc/fc_els.h>
564
565/*
566 * Extended Link Service LS_COMMAND codes (Payload Word 0)
567 */
568#ifdef __BIG_ENDIAN_BITFIELD
569#define ELS_CMD_MASK 0xffff0000
570#define ELS_RSP_MASK 0xff000000
571#define ELS_CMD_LS_RJT 0x01000000
572#define ELS_CMD_ACC 0x02000000
573#define ELS_CMD_PLOGI 0x03000000
574#define ELS_CMD_FLOGI 0x04000000
575#define ELS_CMD_LOGO 0x05000000
576#define ELS_CMD_ABTX 0x06000000
577#define ELS_CMD_RCS 0x07000000
578#define ELS_CMD_RES 0x08000000
579#define ELS_CMD_RSS 0x09000000
580#define ELS_CMD_RSI 0x0A000000
581#define ELS_CMD_ESTS 0x0B000000
582#define ELS_CMD_ESTC 0x0C000000
583#define ELS_CMD_ADVC 0x0D000000
584#define ELS_CMD_RTV 0x0E000000
585#define ELS_CMD_RLS 0x0F000000
586#define ELS_CMD_ECHO 0x10000000
587#define ELS_CMD_TEST 0x11000000
588#define ELS_CMD_RRQ 0x12000000
589#define ELS_CMD_REC 0x13000000
590#define ELS_CMD_RDP 0x18000000
591#define ELS_CMD_PRLI 0x20100014
592#define ELS_CMD_NVMEPRLI 0x20140018
593#define ELS_CMD_PRLO 0x21100014
594#define ELS_CMD_PRLO_ACC 0x02100014
595#define ELS_CMD_PDISC 0x50000000
596#define ELS_CMD_FDISC 0x51000000
597#define ELS_CMD_ADISC 0x52000000
598#define ELS_CMD_FARP 0x54000000
599#define ELS_CMD_FARPR 0x55000000
600#define ELS_CMD_RPS 0x56000000
601#define ELS_CMD_RPL 0x57000000
602#define ELS_CMD_FAN 0x60000000
603#define ELS_CMD_RSCN 0x61040000
604#define ELS_CMD_SCR 0x62000000
605#define ELS_CMD_RNID 0x78000000
606#define ELS_CMD_LIRR 0x7A000000
607#define ELS_CMD_LCB 0x81000000
608#define ELS_CMD_FPIN 0x16000000
609#else /* __LITTLE_ENDIAN_BITFIELD */
610#define ELS_CMD_MASK 0xffff
611#define ELS_RSP_MASK 0xff
612#define ELS_CMD_LS_RJT 0x01
613#define ELS_CMD_ACC 0x02
614#define ELS_CMD_PLOGI 0x03
615#define ELS_CMD_FLOGI 0x04
616#define ELS_CMD_LOGO 0x05
617#define ELS_CMD_ABTX 0x06
618#define ELS_CMD_RCS 0x07
619#define ELS_CMD_RES 0x08
620#define ELS_CMD_RSS 0x09
621#define ELS_CMD_RSI 0x0A
622#define ELS_CMD_ESTS 0x0B
623#define ELS_CMD_ESTC 0x0C
624#define ELS_CMD_ADVC 0x0D
625#define ELS_CMD_RTV 0x0E
626#define ELS_CMD_RLS 0x0F
627#define ELS_CMD_ECHO 0x10
628#define ELS_CMD_TEST 0x11
629#define ELS_CMD_RRQ 0x12
630#define ELS_CMD_REC 0x13
631#define ELS_CMD_RDP 0x18
632#define ELS_CMD_PRLI 0x14001020
633#define ELS_CMD_NVMEPRLI 0x18001420
634#define ELS_CMD_PRLO 0x14001021
635#define ELS_CMD_PRLO_ACC 0x14001002
636#define ELS_CMD_PDISC 0x50
637#define ELS_CMD_FDISC 0x51
638#define ELS_CMD_ADISC 0x52
639#define ELS_CMD_FARP 0x54
640#define ELS_CMD_FARPR 0x55
641#define ELS_CMD_RPS 0x56
642#define ELS_CMD_RPL 0x57
643#define ELS_CMD_FAN 0x60
644#define ELS_CMD_RSCN 0x0461
645#define ELS_CMD_SCR 0x62
646#define ELS_CMD_RNID 0x78
647#define ELS_CMD_LIRR 0x7A
648#define ELS_CMD_LCB 0x81
649#define ELS_CMD_FPIN ELS_FPIN
650#endif
651
652/*
653 * LS_RJT Payload Definition
654 */
655
656struct ls_rjt { /* Structure is in Big Endian format */
657 union {
658 uint32_t lsRjtError;
659 struct {
660 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
661
662 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
663 /* LS_RJT reason codes */
664#define LSRJT_INVALID_CMD 0x01
665#define LSRJT_LOGICAL_ERR 0x03
666#define LSRJT_LOGICAL_BSY 0x05
667#define LSRJT_PROTOCOL_ERR 0x07
668#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
669#define LSRJT_CMD_UNSUPPORTED 0x0B
670#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
671
672 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
673 /* LS_RJT reason explanation */
674#define LSEXP_NOTHING_MORE 0x00
675#define LSEXP_SPARM_OPTIONS 0x01
676#define LSEXP_SPARM_ICTL 0x03
677#define LSEXP_SPARM_RCTL 0x05
678#define LSEXP_SPARM_RCV_SIZE 0x07
679#define LSEXP_SPARM_CONCUR_SEQ 0x09
680#define LSEXP_SPARM_CREDIT 0x0B
681#define LSEXP_INVALID_PNAME 0x0D
682#define LSEXP_INVALID_NNAME 0x0E
683#define LSEXP_INVALID_CSP 0x0F
684#define LSEXP_INVALID_ASSOC_HDR 0x11
685#define LSEXP_ASSOC_HDR_REQ 0x13
686#define LSEXP_INVALID_O_SID 0x15
687#define LSEXP_INVALID_OX_RX 0x17
688#define LSEXP_CMD_IN_PROGRESS 0x19
689#define LSEXP_PORT_LOGIN_REQ 0x1E
690#define LSEXP_INVALID_NPORT_ID 0x1F
691#define LSEXP_INVALID_SEQ_ID 0x21
692#define LSEXP_INVALID_XCHG 0x23
693#define LSEXP_INACTIVE_XCHG 0x25
694#define LSEXP_RQ_REQUIRED 0x27
695#define LSEXP_OUT_OF_RESOURCE 0x29
696#define LSEXP_CANT_GIVE_DATA 0x2A
697#define LSEXP_REQ_UNSUPPORTED 0x2C
698 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
699 } b;
700 } un;
701};
702
703/*
704 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
705 */
706
707typedef struct _LOGO { /* Structure is in Big Endian format */
708 union {
709 uint32_t nPortId32; /* Access nPortId as a word */
710 struct {
711 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
712 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
713 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
714 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
715 } b;
716 } un;
717 struct lpfc_name portName; /* N_port name field */
718} LOGO;
719
720/*
721 * FCP Login (PRLI Request / ACC) Payload Definition
722 */
723
724#define PRLX_PAGE_LEN 0x10
725#define TPRLO_PAGE_LEN 0x14
726
727typedef struct _PRLI { /* Structure is in Big Endian format */
728 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
729
730#define PRLI_FCP_TYPE 0x08
731#define PRLI_NVME_TYPE 0x28
732 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
733
734#ifdef __BIG_ENDIAN_BITFIELD
735 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
736 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
737 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
738
739 /* ACC = imagePairEstablished */
740 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
741 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
742#else /* __LITTLE_ENDIAN_BITFIELD */
743 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
744 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
745 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
746 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
747 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
748 /* ACC = imagePairEstablished */
749#endif
750
751#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
752#define PRLI_NO_RESOURCES 0x2
753#define PRLI_INIT_INCOMPLETE 0x3
754#define PRLI_NO_SUCH_PA 0x4
755#define PRLI_PREDEF_CONFIG 0x5
756#define PRLI_PARTIAL_SUCCESS 0x6
757#define PRLI_INVALID_PAGE_CNT 0x7
758 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
759
760 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
761
762 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
763
764 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
765 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
766
767#ifdef __BIG_ENDIAN_BITFIELD
768 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
769 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
770 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
771 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
772 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
773 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
774 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
775 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
776 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
777 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
778 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
779 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
780 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
781 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
782 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
783 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
784#else /* __LITTLE_ENDIAN_BITFIELD */
785 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
786 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
787 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
788 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
789 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
790 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
791 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
792 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
793 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
794 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
795 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
796 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
797 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
798 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
799 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
800 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
801#endif
802} PRLI;
803
804/*
805 * FCP Logout (PRLO Request / ACC) Payload Definition
806 */
807
808typedef struct _PRLO { /* Structure is in Big Endian format */
809 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
810
811#define PRLO_FCP_TYPE 0x08
812 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
813
814#ifdef __BIG_ENDIAN_BITFIELD
815 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
816 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
817 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
818 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
819#else /* __LITTLE_ENDIAN_BITFIELD */
820 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
821 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
822 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
823 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
824#endif
825
826#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
827#define PRLO_NO_SUCH_IMAGE 0x4
828#define PRLO_INVALID_PAGE_CNT 0x7
829
830 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
831
832 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
833
834 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
835
836 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
837} PRLO;
838
839typedef struct _ADISC { /* Structure is in Big Endian format */
840 uint32_t hardAL_PA;
841 struct lpfc_name portName;
842 struct lpfc_name nodeName;
843 uint32_t DID;
844} ADISC;
845
846typedef struct _FARP { /* Structure is in Big Endian format */
847 uint32_t Mflags:8;
848 uint32_t Odid:24;
849#define FARP_NO_ACTION 0 /* FARP information enclosed, no
850 action */
851#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
852#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
853#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
854#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
855 supported */
856#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
857 supported */
858 uint32_t Rflags:8;
859 uint32_t Rdid:24;
860#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
861#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
862 struct lpfc_name OportName;
863 struct lpfc_name OnodeName;
864 struct lpfc_name RportName;
865 struct lpfc_name RnodeName;
866 uint8_t Oipaddr[16];
867 uint8_t Ripaddr[16];
868} FARP;
869
870typedef struct _FAN { /* Structure is in Big Endian format */
871 uint32_t Fdid;
872 struct lpfc_name FportName;
873 struct lpfc_name FnodeName;
874} FAN;
875
876typedef struct _SCR { /* Structure is in Big Endian format */
877 uint8_t resvd1;
878 uint8_t resvd2;
879 uint8_t resvd3;
880 uint8_t Function;
881#define SCR_FUNC_FABRIC 0x01
882#define SCR_FUNC_NPORT 0x02
883#define SCR_FUNC_FULL 0x03
884#define SCR_CLEAR 0xff
885} SCR;
886
887typedef struct _RNID_TOP_DISC {
888 struct lpfc_name portName;
889 uint8_t resvd[8];
890 uint32_t unitType;
891#define RNID_HBA 0x7
892#define RNID_HOST 0xa
893#define RNID_DRIVER 0xd
894 uint32_t physPort;
895 uint32_t attachedNodes;
896 uint16_t ipVersion;
897#define RNID_IPV4 0x1
898#define RNID_IPV6 0x2
899 uint16_t UDPport;
900 uint8_t ipAddr[16];
901 uint16_t resvd1;
902 uint16_t flags;
903#define RNID_TD_SUPPORT 0x1
904#define RNID_LP_VALID 0x2
905} RNID_TOP_DISC;
906
907typedef struct _RNID { /* Structure is in Big Endian format */
908 uint8_t Format;
909#define RNID_TOPOLOGY_DISC 0xdf
910 uint8_t CommonLen;
911 uint8_t resvd1;
912 uint8_t SpecificLen;
913 struct lpfc_name portName;
914 struct lpfc_name nodeName;
915 union {
916 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
917 } un;
918} RNID;
919
920typedef struct _RPS { /* Structure is in Big Endian format */
921 union {
922 uint32_t portNum;
923 struct lpfc_name portName;
924 } un;
925} RPS;
926
927typedef struct _RPS_RSP { /* Structure is in Big Endian format */
928 uint16_t rsvd1;
929 uint16_t portStatus;
930 uint32_t linkFailureCnt;
931 uint32_t lossSyncCnt;
932 uint32_t lossSignalCnt;
933 uint32_t primSeqErrCnt;
934 uint32_t invalidXmitWord;
935 uint32_t crcCnt;
936} RPS_RSP;
937
938struct RLS { /* Structure is in Big Endian format */
939 uint32_t rls;
940#define rls_rsvd_SHIFT 24
941#define rls_rsvd_MASK 0x000000ff
942#define rls_rsvd_WORD rls
943#define rls_did_SHIFT 0
944#define rls_did_MASK 0x00ffffff
945#define rls_did_WORD rls
946};
947
948struct RLS_RSP { /* Structure is in Big Endian format */
949 uint32_t linkFailureCnt;
950 uint32_t lossSyncCnt;
951 uint32_t lossSignalCnt;
952 uint32_t primSeqErrCnt;
953 uint32_t invalidXmitWord;
954 uint32_t crcCnt;
955};
956
957struct RRQ { /* Structure is in Big Endian format */
958 uint32_t rrq;
959#define rrq_rsvd_SHIFT 24
960#define rrq_rsvd_MASK 0x000000ff
961#define rrq_rsvd_WORD rrq
962#define rrq_did_SHIFT 0
963#define rrq_did_MASK 0x00ffffff
964#define rrq_did_WORD rrq
965 uint32_t rrq_exchg;
966#define rrq_oxid_SHIFT 16
967#define rrq_oxid_MASK 0xffff
968#define rrq_oxid_WORD rrq_exchg
969#define rrq_rxid_SHIFT 0
970#define rrq_rxid_MASK 0xffff
971#define rrq_rxid_WORD rrq_exchg
972};
973
974#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
975#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
976
977struct RTV_RSP { /* Structure is in Big Endian format */
978 uint32_t ratov;
979 uint32_t edtov;
980 uint32_t qtov;
981#define qtov_rsvd0_SHIFT 28
982#define qtov_rsvd0_MASK 0x0000000f
983#define qtov_rsvd0_WORD qtov /* reserved */
984#define qtov_edtovres_SHIFT 27
985#define qtov_edtovres_MASK 0x00000001
986#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
987#define qtov__rsvd1_SHIFT 19
988#define qtov_rsvd1_MASK 0x0000003f
989#define qtov_rsvd1_WORD qtov /* reserved */
990#define qtov_rttov_SHIFT 18
991#define qtov_rttov_MASK 0x00000001
992#define qtov_rttov_WORD qtov /* R_T_TOV value */
993#define qtov_rsvd2_SHIFT 0
994#define qtov_rsvd2_MASK 0x0003ffff
995#define qtov_rsvd2_WORD qtov /* reserved */
996};
997
998
999typedef struct _RPL { /* Structure is in Big Endian format */
1000 uint32_t maxsize;
1001 uint32_t index;
1002} RPL;
1003
1004typedef struct _PORT_NUM_BLK {
1005 uint32_t portNum;
1006 uint32_t portID;
1007 struct lpfc_name portName;
1008} PORT_NUM_BLK;
1009
1010typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1011 uint32_t listLen;
1012 uint32_t index;
1013 PORT_NUM_BLK port_num_blk;
1014} RPL_RSP;
1015
1016/* This is used for RSCN command */
1017typedef struct _D_ID { /* Structure is in Big Endian format */
1018 union {
1019 uint32_t word;
1020 struct {
1021#ifdef __BIG_ENDIAN_BITFIELD
1022 uint8_t resv;
1023 uint8_t domain;
1024 uint8_t area;
1025 uint8_t id;
1026#else /* __LITTLE_ENDIAN_BITFIELD */
1027 uint8_t id;
1028 uint8_t area;
1029 uint8_t domain;
1030 uint8_t resv;
1031#endif
1032 } b;
1033 } un;
1034} D_ID;
1035
1036#define RSCN_ADDRESS_FORMAT_PORT 0x0
1037#define RSCN_ADDRESS_FORMAT_AREA 0x1
1038#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1039#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1040#define RSCN_ADDRESS_FORMAT_MASK 0x3
1041
1042/*
1043 * Structure to define all ELS Payload types
1044 */
1045
1046typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1047 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1048 uint8_t elsByte1;
1049 uint8_t elsByte2;
1050 uint8_t elsByte3;
1051 union {
1052 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1053 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1054 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1055 PRLI prli; /* Payload for PRLI/ACC */
1056 PRLO prlo; /* Payload for PRLO/ACC */
1057 ADISC adisc; /* Payload for ADISC/ACC */
1058 FARP farp; /* Payload for FARP/ACC */
1059 FAN fan; /* Payload for FAN */
1060 SCR scr; /* Payload for SCR/ACC */
1061 RNID rnid; /* Payload for RNID */
1062 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1063 } un;
1064} ELS_PKT;
1065
1066/*
1067 * Link Cable Beacon (LCB) ELS Frame
1068 */
1069
1070struct fc_lcb_request_frame {
1071 uint32_t lcb_command; /* ELS command opcode (0x81) */
1072 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1073#define LPFC_LCB_ON 0x1
1074#define LPFC_LCB_OFF 0x2
1075 uint8_t reserved[2];
1076 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1077 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1078#define LPFC_LCB_GREEN 0x1
1079#define LPFC_LCB_AMBER 0x2
1080 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1081#define LCB_CAPABILITY_DURATION 1
1082#define BEACON_VERSION_V1 1
1083#define BEACON_VERSION_V0 0
1084 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1085};
1086
1087/*
1088 * Link Cable Beacon (LCB) ELS Response Frame
1089 */
1090struct fc_lcb_res_frame {
1091 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1092 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1093 uint8_t reserved[2];
1094 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1095 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1096 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1097 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1098};
1099
1100/*
1101 * Read Diagnostic Parameters (RDP) ELS frame.
1102 */
1103#define SFF_PG0_IDENT_SFP 0x3
1104
1105#define SFP_FLAG_PT_OPTICAL 0x0
1106#define SFP_FLAG_PT_SWLASER 0x01
1107#define SFP_FLAG_PT_LWLASER_LC1310 0x02
1108#define SFP_FLAG_PT_LWLASER_LL1550 0x03
1109#define SFP_FLAG_PT_MASK 0x0F
1110#define SFP_FLAG_PT_SHIFT 0
1111
1112#define SFP_FLAG_IS_OPTICAL_PORT 0x01
1113#define SFP_FLAG_IS_OPTICAL_MASK 0x010
1114#define SFP_FLAG_IS_OPTICAL_SHIFT 4
1115
1116#define SFP_FLAG_IS_DESC_VALID 0x01
1117#define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1118#define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1119
1120#define SFP_FLAG_CT_UNKNOWN 0x0
1121#define SFP_FLAG_CT_SFP_PLUS 0x01
1122#define SFP_FLAG_CT_MASK 0x3C
1123#define SFP_FLAG_CT_SHIFT 6
1124
1125struct fc_rdp_port_name_info {
1126 uint8_t wwnn[8];
1127 uint8_t wwpn[8];
1128};
1129
1130
1131/*
1132 * Link Error Status Block Structure (FC-FS-3) for RDP
1133 * This similar to RPS ELS
1134 */
1135struct fc_link_status {
1136 uint32_t link_failure_cnt;
1137 uint32_t loss_of_synch_cnt;
1138 uint32_t loss_of_signal_cnt;
1139 uint32_t primitive_seq_proto_err;
1140 uint32_t invalid_trans_word;
1141 uint32_t invalid_crc_cnt;
1142
1143};
1144
1145#define RDP_PORT_NAMES_DESC_TAG 0x00010003
1146struct fc_rdp_port_name_desc {
1147 uint32_t tag; /* 0001 0003h */
1148 uint32_t length; /* set to size of payload struct */
1149 struct fc_rdp_port_name_info port_names;
1150};
1151
1152
1153struct fc_rdp_fec_info {
1154 uint32_t CorrectedBlocks;
1155 uint32_t UncorrectableBlocks;
1156};
1157
1158#define RDP_FEC_DESC_TAG 0x00010005
1159struct fc_fec_rdp_desc {
1160 uint32_t tag;
1161 uint32_t length;
1162 struct fc_rdp_fec_info info;
1163};
1164
1165struct fc_rdp_link_error_status_payload_info {
1166 struct fc_link_status link_status; /* 24 bytes */
1167 uint32_t port_type; /* bits 31-30 only */
1168};
1169
1170#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1171struct fc_rdp_link_error_status_desc {
1172 uint32_t tag; /* 0001 0002h */
1173 uint32_t length; /* set to size of payload struct */
1174 struct fc_rdp_link_error_status_payload_info info;
1175};
1176
1177#define VN_PT_PHY_UNKNOWN 0x00
1178#define VN_PT_PHY_PF_PORT 0x01
1179#define VN_PT_PHY_ETH_MAC 0x10
1180#define VN_PT_PHY_SHIFT 30
1181
1182#define RDP_PS_1GB 0x8000
1183#define RDP_PS_2GB 0x4000
1184#define RDP_PS_4GB 0x2000
1185#define RDP_PS_10GB 0x1000
1186#define RDP_PS_8GB 0x0800
1187#define RDP_PS_16GB 0x0400
1188#define RDP_PS_32GB 0x0200
1189#define RDP_PS_64GB 0x0100
1190#define RDP_PS_128GB 0x0080
1191#define RDP_PS_256GB 0x0040
1192
1193#define RDP_CAP_USER_CONFIGURED 0x0002
1194#define RDP_CAP_UNKNOWN 0x0001
1195#define RDP_PS_UNKNOWN 0x0002
1196#define RDP_PS_NOT_ESTABLISHED 0x0001
1197
1198struct fc_rdp_port_speed {
1199 uint16_t capabilities;
1200 uint16_t speed;
1201};
1202
1203struct fc_rdp_port_speed_info {
1204 struct fc_rdp_port_speed port_speed;
1205};
1206
1207#define RDP_PORT_SPEED_DESC_TAG 0x00010001
1208struct fc_rdp_port_speed_desc {
1209 uint32_t tag; /* 00010001h */
1210 uint32_t length; /* set to size of payload struct */
1211 struct fc_rdp_port_speed_info info;
1212};
1213
1214#define RDP_NPORT_ID_SIZE 4
1215#define RDP_N_PORT_DESC_TAG 0x00000003
1216struct fc_rdp_nport_desc {
1217 uint32_t tag; /* 0000 0003h, big endian */
1218 uint32_t length; /* size of RDP_N_PORT_ID struct */
1219 uint32_t nport_id : 12;
1220 uint32_t reserved : 8;
1221};
1222
1223
1224struct fc_rdp_link_service_info {
1225 uint32_t els_req; /* Request payload word 0 value.*/
1226};
1227
1228#define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1229struct fc_rdp_link_service_desc {
1230 uint32_t tag; /* Descriptor tag 1 */
1231 uint32_t length; /* set to size of payload struct. */
1232 struct fc_rdp_link_service_info payload;
1233 /* must be ELS req Word 0(0x18) */
1234};
1235
1236struct fc_rdp_sfp_info {
1237 uint16_t temperature;
1238 uint16_t vcc;
1239 uint16_t tx_bias;
1240 uint16_t tx_power;
1241 uint16_t rx_power;
1242 uint16_t flags;
1243};
1244
1245#define RDP_SFP_DESC_TAG 0x00010000
1246struct fc_rdp_sfp_desc {
1247 uint32_t tag;
1248 uint32_t length; /* set to size of sfp_info struct */
1249 struct fc_rdp_sfp_info sfp_info;
1250};
1251
1252/* Buffer Credit Descriptor */
1253struct fc_rdp_bbc_info {
1254 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1255 uint32_t attached_port_bbc;
1256 uint32_t rtt; /* Round trip time */
1257};
1258#define RDP_BBC_DESC_TAG 0x00010006
1259struct fc_rdp_bbc_desc {
1260 uint32_t tag;
1261 uint32_t length;
1262 struct fc_rdp_bbc_info bbc_info;
1263};
1264
1265/* Optical Element Type Transgression Flags */
1266#define RDP_OET_LOW_WARNING 0x1
1267#define RDP_OET_HIGH_WARNING 0x2
1268#define RDP_OET_LOW_ALARM 0x4
1269#define RDP_OET_HIGH_ALARM 0x8
1270
1271#define RDP_OED_TEMPERATURE 0x1
1272#define RDP_OED_VOLTAGE 0x2
1273#define RDP_OED_TXBIAS 0x3
1274#define RDP_OED_TXPOWER 0x4
1275#define RDP_OED_RXPOWER 0x5
1276
1277#define RDP_OED_TYPE_SHIFT 28
1278/* Optical Element Data descriptor */
1279struct fc_rdp_oed_info {
1280 uint16_t hi_alarm;
1281 uint16_t lo_alarm;
1282 uint16_t hi_warning;
1283 uint16_t lo_warning;
1284 uint32_t function_flags;
1285};
1286#define RDP_OED_DESC_TAG 0x00010007
1287struct fc_rdp_oed_sfp_desc {
1288 uint32_t tag;
1289 uint32_t length;
1290 struct fc_rdp_oed_info oed_info;
1291};
1292
1293/* Optical Product Data descriptor */
1294struct fc_rdp_opd_sfp_info {
1295 uint8_t vendor_name[16];
1296 uint8_t model_number[16];
1297 uint8_t serial_number[16];
1298 uint8_t revision[4];
1299 uint8_t date[8];
1300};
1301
1302#define RDP_OPD_DESC_TAG 0x00010008
1303struct fc_rdp_opd_sfp_desc {
1304 uint32_t tag;
1305 uint32_t length;
1306 struct fc_rdp_opd_sfp_info opd_info;
1307};
1308
1309struct fc_rdp_req_frame {
1310 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1311 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1312 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1313};
1314
1315
1316struct fc_rdp_res_frame {
1317 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1318 uint32_t length; /* FC Word 1 */
1319 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1320 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1321 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1322 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1323 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1324 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1325 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1326 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1327 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1328 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1329 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1330 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1331 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1332 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1333};
1334
1335
1336/******** FDMI ********/
1337
1338/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1339#define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1340
1341/*
1342 * Registered Port List Format
1343 */
1344struct lpfc_fdmi_reg_port_list {
1345 uint32_t EntryCnt;
1346 uint32_t pe; /* Variable-length array */
1347};
1348
1349
1350/* Definitions for HBA / Port attribute entries */
1351
1352struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1353 /* Structure is in Big Endian format */
1354 uint32_t AttrType:16;
1355 uint32_t AttrLen:16;
1356 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */
1357};
1358
1359
1360/* Attribute Entry */
1361struct lpfc_fdmi_attr_entry {
1362 union {
1363 uint32_t AttrInt;
1364 uint8_t AttrTypes[32];
1365 uint8_t AttrString[256];
1366 struct lpfc_name AttrWWN;
1367 } un;
1368};
1369
1370#define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry)
1371
1372/*
1373 * HBA Attribute Block
1374 */
1375struct lpfc_fdmi_attr_block {
1376 uint32_t EntryCnt; /* Number of HBA attribute entries */
1377 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1378};
1379
1380/*
1381 * Port Entry
1382 */
1383struct lpfc_fdmi_port_entry {
1384 struct lpfc_name PortName;
1385};
1386
1387/*
1388 * HBA Identifier
1389 */
1390struct lpfc_fdmi_hba_ident {
1391 struct lpfc_name PortName;
1392};
1393
1394/*
1395 * Register HBA(RHBA)
1396 */
1397struct lpfc_fdmi_reg_hba {
1398 struct lpfc_fdmi_hba_ident hi;
1399 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */
1400/* struct lpfc_fdmi_attr_block ab; */
1401};
1402
1403/*
1404 * Register HBA Attributes (RHAT)
1405 */
1406struct lpfc_fdmi_reg_hbaattr {
1407 struct lpfc_name HBA_PortName;
1408 struct lpfc_fdmi_attr_block ab;
1409};
1410
1411/*
1412 * Register Port Attributes (RPA)
1413 */
1414struct lpfc_fdmi_reg_portattr {
1415 struct lpfc_name PortName;
1416 struct lpfc_fdmi_attr_block ab;
1417};
1418
1419/*
1420 * HBA MAnagement Operations Command Codes
1421 */
1422#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1423#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1424#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1425#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1426#define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1427#define SLI_MGMT_RHBA 0x200 /* Register HBA */
1428#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1429#define SLI_MGMT_RPRT 0x210 /* Register Port */
1430#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1431#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1432#define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1433#define SLI_MGMT_DPRT 0x310 /* De-register Port */
1434#define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1435
1436#define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1437
1438/*
1439 * HBA Attribute Types
1440 */
1441#define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1442#define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1443#define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1444#define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1445#define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1446#define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1447#define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1448#define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1449#define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1450#define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1451#define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1452#define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1453#define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1454#define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1455#define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1456#define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1457#define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1458#define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1459
1460/* Bit mask for all individual HBA attributes */
1461#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1462#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1463#define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1464#define LPFC_FDMI_HBA_ATTR_model 0x00000008
1465#define LPFC_FDMI_HBA_ATTR_description 0x00000010
1466#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1467#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1468#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1469#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1470#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1471#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1472#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1473#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1474#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1475#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1476#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1477#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1478#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1479
1480/* Bit mask for FDMI-1 defined HBA attributes */
1481#define LPFC_FDMI1_HBA_ATTR 0x000007ff
1482
1483/* Bit mask for FDMI-2 defined HBA attributes */
1484/* Skip vendor_info and bios_state */
1485#define LPFC_FDMI2_HBA_ATTR 0x0002efff
1486
1487/*
1488 * Port Attrubute Types
1489 */
1490#define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1491#define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1492#define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1493#define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1494#define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1495#define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1496#define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1497#define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1498#define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1499#define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1500#define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1501#define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1502#define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1503#define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1504#define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1505#define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1506#define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1507#define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1508#define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1509#define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1510#define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1511#define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1512#define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1513
1514/* Bit mask for all individual PORT attributes */
1515#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1516#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1517#define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1518#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1519#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1520#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1521#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1522#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1523#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1524#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1525#define LPFC_FDMI_PORT_ATTR_class 0x00000400
1526#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1527#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1528#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1529#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1530#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1531#define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1532#define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1533#define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1534#define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1535#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1536#define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1537#define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1538
1539/* Bit mask for FDMI-1 defined PORT attributes */
1540#define LPFC_FDMI1_PORT_ATTR 0x0000003f
1541
1542/* Bit mask for FDMI-2 defined PORT attributes */
1543#define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1544
1545/* Bit mask for Smart SAN defined PORT attributes */
1546#define LPFC_FDMI2_SMART_ATTR 0x007fffff
1547
1548/* Defines for PORT port state attribute */
1549#define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1550#define LPFC_FDMI_PORTSTATE_ONLINE 2
1551
1552/* Defines for PORT port type attribute */
1553#define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1554#define LPFC_FDMI_PORTTYPE_NPORT 1
1555#define LPFC_FDMI_PORTTYPE_NLPORT 2
1556
1557/*
1558 * Begin HBA configuration parameters.
1559 * The PCI configuration register BAR assignments are:
1560 * BAR0, offset 0x10 - SLIM base memory address
1561 * BAR1, offset 0x14 - SLIM base memory high address
1562 * BAR2, offset 0x18 - REGISTER base memory address
1563 * BAR3, offset 0x1c - REGISTER base memory high address
1564 * BAR4, offset 0x20 - BIU I/O registers
1565 * BAR5, offset 0x24 - REGISTER base io high address
1566 */
1567
1568/* Number of rings currently used and available. */
1569#define MAX_SLI3_CONFIGURED_RINGS 3
1570#define MAX_SLI3_RINGS 4
1571
1572/* IOCB / Mailbox is owned by FireFly */
1573#define OWN_CHIP 1
1574
1575/* IOCB / Mailbox is owned by Host */
1576#define OWN_HOST 0
1577
1578/* Number of 4-byte words in an IOCB. */
1579#define IOCB_WORD_SZ 8
1580
1581/* network headers for Dfctl field */
1582#define FC_NET_HDR 0x20
1583
1584/* Start FireFly Register definitions */
1585#define PCI_VENDOR_ID_EMULEX 0x10df
1586#define PCI_DEVICE_ID_FIREFLY 0x1ae5
1587#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1588#define PCI_DEVICE_ID_BALIUS 0xe131
1589#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1590#define PCI_DEVICE_ID_LANCER_FC 0xe200
1591#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1592#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1593#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1594#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1595#define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1596#define PCI_DEVICE_ID_SAT_SMB 0xf011
1597#define PCI_DEVICE_ID_SAT_MID 0xf015
1598#define PCI_DEVICE_ID_RFLY 0xf095
1599#define PCI_DEVICE_ID_PFLY 0xf098
1600#define PCI_DEVICE_ID_LP101 0xf0a1
1601#define PCI_DEVICE_ID_TFLY 0xf0a5
1602#define PCI_DEVICE_ID_BSMB 0xf0d1
1603#define PCI_DEVICE_ID_BMID 0xf0d5
1604#define PCI_DEVICE_ID_ZSMB 0xf0e1
1605#define PCI_DEVICE_ID_ZMID 0xf0e5
1606#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1607#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1608#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1609#define PCI_DEVICE_ID_SAT 0xf100
1610#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1611#define PCI_DEVICE_ID_SAT_DCSP 0xf112
1612#define PCI_DEVICE_ID_FALCON 0xf180
1613#define PCI_DEVICE_ID_SUPERFLY 0xf700
1614#define PCI_DEVICE_ID_DRAGONFLY 0xf800
1615#define PCI_DEVICE_ID_CENTAUR 0xf900
1616#define PCI_DEVICE_ID_PEGASUS 0xf980
1617#define PCI_DEVICE_ID_THOR 0xfa00
1618#define PCI_DEVICE_ID_VIPER 0xfb00
1619#define PCI_DEVICE_ID_LP10000S 0xfc00
1620#define PCI_DEVICE_ID_LP11000S 0xfc10
1621#define PCI_DEVICE_ID_LPE11000S 0xfc20
1622#define PCI_DEVICE_ID_SAT_S 0xfc40
1623#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1624#define PCI_DEVICE_ID_HELIOS 0xfd00
1625#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1626#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1627#define PCI_DEVICE_ID_ZEPHYR 0xfe00
1628#define PCI_DEVICE_ID_HORNET 0xfe05
1629#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1630#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1631#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1632#define PCI_DEVICE_ID_TIGERSHARK 0x0704
1633#define PCI_DEVICE_ID_TOMCAT 0x0714
1634#define PCI_DEVICE_ID_SKYHAWK 0x0724
1635#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1636
1637#define JEDEC_ID_ADDRESS 0x0080001c
1638#define FIREFLY_JEDEC_ID 0x1ACC
1639#define SUPERFLY_JEDEC_ID 0x0020
1640#define DRAGONFLY_JEDEC_ID 0x0021
1641#define DRAGONFLY_V2_JEDEC_ID 0x0025
1642#define CENTAUR_2G_JEDEC_ID 0x0026
1643#define CENTAUR_1G_JEDEC_ID 0x0028
1644#define PEGASUS_ORION_JEDEC_ID 0x0036
1645#define PEGASUS_JEDEC_ID 0x0038
1646#define THOR_JEDEC_ID 0x0012
1647#define HELIOS_JEDEC_ID 0x0364
1648#define ZEPHYR_JEDEC_ID 0x0577
1649#define VIPER_JEDEC_ID 0x4838
1650#define SATURN_JEDEC_ID 0x1004
1651#define HORNET_JDEC_ID 0x2057706D
1652
1653#define JEDEC_ID_MASK 0x0FFFF000
1654#define JEDEC_ID_SHIFT 12
1655#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1656
1657typedef struct { /* FireFly BIU registers */
1658 uint32_t hostAtt; /* See definitions for Host Attention
1659 register */
1660 uint32_t chipAtt; /* See definitions for Chip Attention
1661 register */
1662 uint32_t hostStatus; /* See definitions for Host Status register */
1663 uint32_t hostControl; /* See definitions for Host Control register */
1664 uint32_t buiConfig; /* See definitions for BIU configuration
1665 register */
1666} FF_REGS;
1667
1668/* IO Register size in bytes */
1669#define FF_REG_AREA_SIZE 256
1670
1671/* Host Attention Register */
1672
1673#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1674
1675#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1676#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1677#define HA_R0ATT 0x00000008 /* Bit 3 */
1678#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1679#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1680#define HA_R1ATT 0x00000080 /* Bit 7 */
1681#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1682#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1683#define HA_R2ATT 0x00000800 /* Bit 11 */
1684#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1685#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1686#define HA_R3ATT 0x00008000 /* Bit 15 */
1687#define HA_LATT 0x20000000 /* Bit 29 */
1688#define HA_MBATT 0x40000000 /* Bit 30 */
1689#define HA_ERATT 0x80000000 /* Bit 31 */
1690
1691#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1692#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1693#define HA_RXATT 0x00000008 /* Bit 3 */
1694#define HA_RXMASK 0x0000000f
1695
1696#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1697#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1698#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1699#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1700
1701#define HA_R0_POS 3
1702#define HA_R1_POS 7
1703#define HA_R2_POS 11
1704#define HA_R3_POS 15
1705#define HA_LE_POS 29
1706#define HA_MB_POS 30
1707#define HA_ER_POS 31
1708/* Chip Attention Register */
1709
1710#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1711
1712#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1713#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1714#define CA_R0ATT 0x00000008 /* Bit 3 */
1715#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1716#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1717#define CA_R1ATT 0x00000080 /* Bit 7 */
1718#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1719#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1720#define CA_R2ATT 0x00000800 /* Bit 11 */
1721#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1722#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1723#define CA_R3ATT 0x00008000 /* Bit 15 */
1724#define CA_MBATT 0x40000000 /* Bit 30 */
1725
1726/* Host Status Register */
1727
1728#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1729
1730#define HS_MBRDY 0x00400000 /* Bit 22 */
1731#define HS_FFRDY 0x00800000 /* Bit 23 */
1732#define HS_FFER8 0x01000000 /* Bit 24 */
1733#define HS_FFER7 0x02000000 /* Bit 25 */
1734#define HS_FFER6 0x04000000 /* Bit 26 */
1735#define HS_FFER5 0x08000000 /* Bit 27 */
1736#define HS_FFER4 0x10000000 /* Bit 28 */
1737#define HS_FFER3 0x20000000 /* Bit 29 */
1738#define HS_FFER2 0x40000000 /* Bit 30 */
1739#define HS_FFER1 0x80000000 /* Bit 31 */
1740#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1741#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1742#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1743/* Host Control Register */
1744
1745#define HC_REG_OFFSET 12 /* Byte offset from register base address */
1746
1747#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1748#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1749#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1750#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1751#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1752#define HC_INITHBI 0x02000000 /* Bit 25 */
1753#define HC_INITMB 0x04000000 /* Bit 26 */
1754#define HC_INITFF 0x08000000 /* Bit 27 */
1755#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1756#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1757
1758/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1759#define MSIX_DFLT_ID 0
1760#define MSIX_RNG0_ID 0
1761#define MSIX_RNG1_ID 1
1762#define MSIX_RNG2_ID 2
1763#define MSIX_RNG3_ID 3
1764
1765#define MSIX_LINK_ID 4
1766#define MSIX_MBOX_ID 5
1767
1768#define MSIX_SPARE0_ID 6
1769#define MSIX_SPARE1_ID 7
1770
1771/* Mailbox Commands */
1772#define MBX_SHUTDOWN 0x00 /* terminate testing */
1773#define MBX_LOAD_SM 0x01
1774#define MBX_READ_NV 0x02
1775#define MBX_WRITE_NV 0x03
1776#define MBX_RUN_BIU_DIAG 0x04
1777#define MBX_INIT_LINK 0x05
1778#define MBX_DOWN_LINK 0x06
1779#define MBX_CONFIG_LINK 0x07
1780#define MBX_CONFIG_RING 0x09
1781#define MBX_RESET_RING 0x0A
1782#define MBX_READ_CONFIG 0x0B
1783#define MBX_READ_RCONFIG 0x0C
1784#define MBX_READ_SPARM 0x0D
1785#define MBX_READ_STATUS 0x0E
1786#define MBX_READ_RPI 0x0F
1787#define MBX_READ_XRI 0x10
1788#define MBX_READ_REV 0x11
1789#define MBX_READ_LNK_STAT 0x12
1790#define MBX_REG_LOGIN 0x13
1791#define MBX_UNREG_LOGIN 0x14
1792#define MBX_CLEAR_LA 0x16
1793#define MBX_DUMP_MEMORY 0x17
1794#define MBX_DUMP_CONTEXT 0x18
1795#define MBX_RUN_DIAGS 0x19
1796#define MBX_RESTART 0x1A
1797#define MBX_UPDATE_CFG 0x1B
1798#define MBX_DOWN_LOAD 0x1C
1799#define MBX_DEL_LD_ENTRY 0x1D
1800#define MBX_RUN_PROGRAM 0x1E
1801#define MBX_SET_MASK 0x20
1802#define MBX_SET_VARIABLE 0x21
1803#define MBX_UNREG_D_ID 0x23
1804#define MBX_KILL_BOARD 0x24
1805#define MBX_CONFIG_FARP 0x25
1806#define MBX_BEACON 0x2A
1807#define MBX_CONFIG_MSI 0x30
1808#define MBX_HEARTBEAT 0x31
1809#define MBX_WRITE_VPARMS 0x32
1810#define MBX_ASYNCEVT_ENABLE 0x33
1811#define MBX_READ_EVENT_LOG_STATUS 0x37
1812#define MBX_READ_EVENT_LOG 0x38
1813#define MBX_WRITE_EVENT_LOG 0x39
1814
1815#define MBX_PORT_CAPABILITIES 0x3B
1816#define MBX_PORT_IOV_CONTROL 0x3C
1817
1818#define MBX_CONFIG_HBQ 0x7C
1819#define MBX_LOAD_AREA 0x81
1820#define MBX_RUN_BIU_DIAG64 0x84
1821#define MBX_CONFIG_PORT 0x88
1822#define MBX_READ_SPARM64 0x8D
1823#define MBX_READ_RPI64 0x8F
1824#define MBX_REG_LOGIN64 0x93
1825#define MBX_READ_TOPOLOGY 0x95
1826#define MBX_REG_VPI 0x96
1827#define MBX_UNREG_VPI 0x97
1828
1829#define MBX_WRITE_WWN 0x98
1830#define MBX_SET_DEBUG 0x99
1831#define MBX_LOAD_EXP_ROM 0x9C
1832#define MBX_SLI4_CONFIG 0x9B
1833#define MBX_SLI4_REQ_FTRS 0x9D
1834#define MBX_MAX_CMDS 0x9E
1835#define MBX_RESUME_RPI 0x9E
1836#define MBX_SLI2_CMD_MASK 0x80
1837#define MBX_REG_VFI 0x9F
1838#define MBX_REG_FCFI 0xA0
1839#define MBX_UNREG_VFI 0xA1
1840#define MBX_UNREG_FCFI 0xA2
1841#define MBX_INIT_VFI 0xA3
1842#define MBX_INIT_VPI 0xA4
1843#define MBX_ACCESS_VDATA 0xA5
1844#define MBX_REG_FCFI_MRQ 0xAF
1845
1846#define MBX_AUTH_PORT 0xF8
1847#define MBX_SECURITY_MGMT 0xF9
1848
1849/* IOCB Commands */
1850
1851#define CMD_RCV_SEQUENCE_CX 0x01
1852#define CMD_XMIT_SEQUENCE_CR 0x02
1853#define CMD_XMIT_SEQUENCE_CX 0x03
1854#define CMD_XMIT_BCAST_CN 0x04
1855#define CMD_XMIT_BCAST_CX 0x05
1856#define CMD_QUE_RING_BUF_CN 0x06
1857#define CMD_QUE_XRI_BUF_CX 0x07
1858#define CMD_IOCB_CONTINUE_CN 0x08
1859#define CMD_RET_XRI_BUF_CX 0x09
1860#define CMD_ELS_REQUEST_CR 0x0A
1861#define CMD_ELS_REQUEST_CX 0x0B
1862#define CMD_RCV_ELS_REQ_CX 0x0D
1863#define CMD_ABORT_XRI_CN 0x0E
1864#define CMD_ABORT_XRI_CX 0x0F
1865#define CMD_CLOSE_XRI_CN 0x10
1866#define CMD_CLOSE_XRI_CX 0x11
1867#define CMD_CREATE_XRI_CR 0x12
1868#define CMD_CREATE_XRI_CX 0x13
1869#define CMD_GET_RPI_CN 0x14
1870#define CMD_XMIT_ELS_RSP_CX 0x15
1871#define CMD_GET_RPI_CR 0x16
1872#define CMD_XRI_ABORTED_CX 0x17
1873#define CMD_FCP_IWRITE_CR 0x18
1874#define CMD_FCP_IWRITE_CX 0x19
1875#define CMD_FCP_IREAD_CR 0x1A
1876#define CMD_FCP_IREAD_CX 0x1B
1877#define CMD_FCP_ICMND_CR 0x1C
1878#define CMD_FCP_ICMND_CX 0x1D
1879#define CMD_FCP_TSEND_CX 0x1F
1880#define CMD_FCP_TRECEIVE_CX 0x21
1881#define CMD_FCP_TRSP_CX 0x23
1882#define CMD_FCP_AUTO_TRSP_CX 0x29
1883
1884#define CMD_ADAPTER_MSG 0x20
1885#define CMD_ADAPTER_DUMP 0x22
1886
1887/* SLI_2 IOCB Command Set */
1888
1889#define CMD_ASYNC_STATUS 0x7C
1890#define CMD_RCV_SEQUENCE64_CX 0x81
1891#define CMD_XMIT_SEQUENCE64_CR 0x82
1892#define CMD_XMIT_SEQUENCE64_CX 0x83
1893#define CMD_XMIT_BCAST64_CN 0x84
1894#define CMD_XMIT_BCAST64_CX 0x85
1895#define CMD_QUE_RING_BUF64_CN 0x86
1896#define CMD_QUE_XRI_BUF64_CX 0x87
1897#define CMD_IOCB_CONTINUE64_CN 0x88
1898#define CMD_RET_XRI_BUF64_CX 0x89
1899#define CMD_ELS_REQUEST64_CR 0x8A
1900#define CMD_ELS_REQUEST64_CX 0x8B
1901#define CMD_ABORT_MXRI64_CN 0x8C
1902#define CMD_RCV_ELS_REQ64_CX 0x8D
1903#define CMD_XMIT_ELS_RSP64_CX 0x95
1904#define CMD_XMIT_BLS_RSP64_CX 0x97
1905#define CMD_FCP_IWRITE64_CR 0x98
1906#define CMD_FCP_IWRITE64_CX 0x99
1907#define CMD_FCP_IREAD64_CR 0x9A
1908#define CMD_FCP_IREAD64_CX 0x9B
1909#define CMD_FCP_ICMND64_CR 0x9C
1910#define CMD_FCP_ICMND64_CX 0x9D
1911#define CMD_FCP_TSEND64_CX 0x9F
1912#define CMD_FCP_TRECEIVE64_CX 0xA1
1913#define CMD_FCP_TRSP64_CX 0xA3
1914
1915#define CMD_QUE_XRI64_CX 0xB3
1916#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1917#define CMD_IOCB_RCV_ELS64_CX 0xB7
1918#define CMD_IOCB_RET_XRI64_CX 0xB9
1919#define CMD_IOCB_RCV_CONT64_CX 0xBB
1920
1921#define CMD_GEN_REQUEST64_CR 0xC2
1922#define CMD_GEN_REQUEST64_CX 0xC3
1923
1924/* Unhandled SLI-3 Commands */
1925#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1926#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1927#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1928#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1929#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1930#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1931#define CMD_IOCB_RET_HBQE64_CN 0xCA
1932#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1933#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1934#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1935#define CMD_IOCB_LOGENTRY_CN 0x94
1936#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1937
1938/* Data Security SLI Commands */
1939#define DSSCMD_IWRITE64_CR 0xF8
1940#define DSSCMD_IWRITE64_CX 0xF9
1941#define DSSCMD_IREAD64_CR 0xFA
1942#define DSSCMD_IREAD64_CX 0xFB
1943
1944#define CMD_MAX_IOCB_CMD 0xFB
1945#define CMD_IOCB_MASK 0xff
1946
1947#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1948 iocb */
1949#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1950/*
1951 * Define Status
1952 */
1953#define MBX_SUCCESS 0
1954#define MBXERR_NUM_RINGS 1
1955#define MBXERR_NUM_IOCBS 2
1956#define MBXERR_IOCBS_EXCEEDED 3
1957#define MBXERR_BAD_RING_NUMBER 4
1958#define MBXERR_MASK_ENTRIES_RANGE 5
1959#define MBXERR_MASKS_EXCEEDED 6
1960#define MBXERR_BAD_PROFILE 7
1961#define MBXERR_BAD_DEF_CLASS 8
1962#define MBXERR_BAD_MAX_RESPONDER 9
1963#define MBXERR_BAD_MAX_ORIGINATOR 10
1964#define MBXERR_RPI_REGISTERED 11
1965#define MBXERR_RPI_FULL 12
1966#define MBXERR_NO_RESOURCES 13
1967#define MBXERR_BAD_RCV_LENGTH 14
1968#define MBXERR_DMA_ERROR 15
1969#define MBXERR_ERROR 16
1970#define MBXERR_LINK_DOWN 0x33
1971#define MBXERR_SEC_NO_PERMISSION 0xF02
1972#define MBX_NOT_FINISHED 255
1973
1974#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1975#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1976
1977#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1978
1979/*
1980 * return code Fail
1981 */
1982#define FAILURE 1
1983
1984/*
1985 * Begin Structure Definitions for Mailbox Commands
1986 */
1987
1988typedef struct {
1989#ifdef __BIG_ENDIAN_BITFIELD
1990 uint8_t tval;
1991 uint8_t tmask;
1992 uint8_t rval;
1993 uint8_t rmask;
1994#else /* __LITTLE_ENDIAN_BITFIELD */
1995 uint8_t rmask;
1996 uint8_t rval;
1997 uint8_t tmask;
1998 uint8_t tval;
1999#endif
2000} RR_REG;
2001
2002struct ulp_bde {
2003 uint32_t bdeAddress;
2004#ifdef __BIG_ENDIAN_BITFIELD
2005 uint32_t bdeReserved:4;
2006 uint32_t bdeAddrHigh:4;
2007 uint32_t bdeSize:24;
2008#else /* __LITTLE_ENDIAN_BITFIELD */
2009 uint32_t bdeSize:24;
2010 uint32_t bdeAddrHigh:4;
2011 uint32_t bdeReserved:4;
2012#endif
2013};
2014
2015typedef struct ULP_BDL { /* SLI-2 */
2016#ifdef __BIG_ENDIAN_BITFIELD
2017 uint32_t bdeFlags:8; /* BDL Flags */
2018 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2019#else /* __LITTLE_ENDIAN_BITFIELD */
2020 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2021 uint32_t bdeFlags:8; /* BDL Flags */
2022#endif
2023
2024 uint32_t addrLow; /* Address 0:31 */
2025 uint32_t addrHigh; /* Address 32:63 */
2026 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2027} ULP_BDL;
2028
2029/*
2030 * BlockGuard Definitions
2031 */
2032
2033enum lpfc_protgrp_type {
2034 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2035 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2036 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2037 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2038};
2039
2040/* PDE Descriptors */
2041#define LPFC_PDE5_DESCRIPTOR 0x85
2042#define LPFC_PDE6_DESCRIPTOR 0x86
2043#define LPFC_PDE7_DESCRIPTOR 0x87
2044
2045/* BlockGuard Opcodes */
2046#define BG_OP_IN_NODIF_OUT_CRC 0x0
2047#define BG_OP_IN_CRC_OUT_NODIF 0x1
2048#define BG_OP_IN_NODIF_OUT_CSUM 0x2
2049#define BG_OP_IN_CSUM_OUT_NODIF 0x3
2050#define BG_OP_IN_CRC_OUT_CRC 0x4
2051#define BG_OP_IN_CSUM_OUT_CSUM 0x5
2052#define BG_OP_IN_CRC_OUT_CSUM 0x6
2053#define BG_OP_IN_CSUM_OUT_CRC 0x7
2054#define BG_OP_RAW_MODE 0x8
2055
2056struct lpfc_pde5 {
2057 uint32_t word0;
2058#define pde5_type_SHIFT 24
2059#define pde5_type_MASK 0x000000ff
2060#define pde5_type_WORD word0
2061#define pde5_rsvd0_SHIFT 0
2062#define pde5_rsvd0_MASK 0x00ffffff
2063#define pde5_rsvd0_WORD word0
2064 uint32_t reftag; /* Reference Tag Value */
2065 uint32_t reftagtr; /* Reference Tag Translation Value */
2066};
2067
2068struct lpfc_pde6 {
2069 uint32_t word0;
2070#define pde6_type_SHIFT 24
2071#define pde6_type_MASK 0x000000ff
2072#define pde6_type_WORD word0
2073#define pde6_rsvd0_SHIFT 0
2074#define pde6_rsvd0_MASK 0x00ffffff
2075#define pde6_rsvd0_WORD word0
2076 uint32_t word1;
2077#define pde6_rsvd1_SHIFT 26
2078#define pde6_rsvd1_MASK 0x0000003f
2079#define pde6_rsvd1_WORD word1
2080#define pde6_na_SHIFT 25
2081#define pde6_na_MASK 0x00000001
2082#define pde6_na_WORD word1
2083#define pde6_rsvd2_SHIFT 16
2084#define pde6_rsvd2_MASK 0x000001FF
2085#define pde6_rsvd2_WORD word1
2086#define pde6_apptagtr_SHIFT 0
2087#define pde6_apptagtr_MASK 0x0000ffff
2088#define pde6_apptagtr_WORD word1
2089 uint32_t word2;
2090#define pde6_optx_SHIFT 28
2091#define pde6_optx_MASK 0x0000000f
2092#define pde6_optx_WORD word2
2093#define pde6_oprx_SHIFT 24
2094#define pde6_oprx_MASK 0x0000000f
2095#define pde6_oprx_WORD word2
2096#define pde6_nr_SHIFT 23
2097#define pde6_nr_MASK 0x00000001
2098#define pde6_nr_WORD word2
2099#define pde6_ce_SHIFT 22
2100#define pde6_ce_MASK 0x00000001
2101#define pde6_ce_WORD word2
2102#define pde6_re_SHIFT 21
2103#define pde6_re_MASK 0x00000001
2104#define pde6_re_WORD word2
2105#define pde6_ae_SHIFT 20
2106#define pde6_ae_MASK 0x00000001
2107#define pde6_ae_WORD word2
2108#define pde6_ai_SHIFT 19
2109#define pde6_ai_MASK 0x00000001
2110#define pde6_ai_WORD word2
2111#define pde6_bs_SHIFT 16
2112#define pde6_bs_MASK 0x00000007
2113#define pde6_bs_WORD word2
2114#define pde6_apptagval_SHIFT 0
2115#define pde6_apptagval_MASK 0x0000ffff
2116#define pde6_apptagval_WORD word2
2117};
2118
2119struct lpfc_pde7 {
2120 uint32_t word0;
2121#define pde7_type_SHIFT 24
2122#define pde7_type_MASK 0x000000ff
2123#define pde7_type_WORD word0
2124#define pde7_rsvd0_SHIFT 0
2125#define pde7_rsvd0_MASK 0x00ffffff
2126#define pde7_rsvd0_WORD word0
2127 uint32_t addrHigh;
2128 uint32_t addrLow;
2129};
2130
2131/* Structure for MB Command LOAD_SM and DOWN_LOAD */
2132
2133typedef struct {
2134#ifdef __BIG_ENDIAN_BITFIELD
2135 uint32_t rsvd2:25;
2136 uint32_t acknowledgment:1;
2137 uint32_t version:1;
2138 uint32_t erase_or_prog:1;
2139 uint32_t update_flash:1;
2140 uint32_t update_ram:1;
2141 uint32_t method:1;
2142 uint32_t load_cmplt:1;
2143#else /* __LITTLE_ENDIAN_BITFIELD */
2144 uint32_t load_cmplt:1;
2145 uint32_t method:1;
2146 uint32_t update_ram:1;
2147 uint32_t update_flash:1;
2148 uint32_t erase_or_prog:1;
2149 uint32_t version:1;
2150 uint32_t acknowledgment:1;
2151 uint32_t rsvd2:25;
2152#endif
2153
2154 uint32_t dl_to_adr_low;
2155 uint32_t dl_to_adr_high;
2156 uint32_t dl_len;
2157 union {
2158 uint32_t dl_from_mbx_offset;
2159 struct ulp_bde dl_from_bde;
2160 struct ulp_bde64 dl_from_bde64;
2161 } un;
2162
2163} LOAD_SM_VAR;
2164
2165/* Structure for MB Command READ_NVPARM (02) */
2166
2167typedef struct {
2168 uint32_t rsvd1[3]; /* Read as all one's */
2169 uint32_t rsvd2; /* Read as all zero's */
2170 uint32_t portname[2]; /* N_PORT name */
2171 uint32_t nodename[2]; /* NODE name */
2172
2173#ifdef __BIG_ENDIAN_BITFIELD
2174 uint32_t pref_DID:24;
2175 uint32_t hardAL_PA:8;
2176#else /* __LITTLE_ENDIAN_BITFIELD */
2177 uint32_t hardAL_PA:8;
2178 uint32_t pref_DID:24;
2179#endif
2180
2181 uint32_t rsvd3[21]; /* Read as all one's */
2182} READ_NV_VAR;
2183
2184/* Structure for MB Command WRITE_NVPARMS (03) */
2185
2186typedef struct {
2187 uint32_t rsvd1[3]; /* Must be all one's */
2188 uint32_t rsvd2; /* Must be all zero's */
2189 uint32_t portname[2]; /* N_PORT name */
2190 uint32_t nodename[2]; /* NODE name */
2191
2192#ifdef __BIG_ENDIAN_BITFIELD
2193 uint32_t pref_DID:24;
2194 uint32_t hardAL_PA:8;
2195#else /* __LITTLE_ENDIAN_BITFIELD */
2196 uint32_t hardAL_PA:8;
2197 uint32_t pref_DID:24;
2198#endif
2199
2200 uint32_t rsvd3[21]; /* Must be all one's */
2201} WRITE_NV_VAR;
2202
2203/* Structure for MB Command RUN_BIU_DIAG (04) */
2204/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2205
2206typedef struct {
2207 uint32_t rsvd1;
2208 union {
2209 struct {
2210 struct ulp_bde xmit_bde;
2211 struct ulp_bde rcv_bde;
2212 } s1;
2213 struct {
2214 struct ulp_bde64 xmit_bde64;
2215 struct ulp_bde64 rcv_bde64;
2216 } s2;
2217 } un;
2218} BIU_DIAG_VAR;
2219
2220/* Structure for MB command READ_EVENT_LOG (0x38) */
2221struct READ_EVENT_LOG_VAR {
2222 uint32_t word1;
2223#define lpfc_event_log_SHIFT 29
2224#define lpfc_event_log_MASK 0x00000001
2225#define lpfc_event_log_WORD word1
2226#define USE_MAILBOX_RESPONSE 1
2227 uint32_t offset;
2228 struct ulp_bde64 rcv_bde64;
2229};
2230
2231/* Structure for MB Command INIT_LINK (05) */
2232
2233typedef struct {
2234#ifdef __BIG_ENDIAN_BITFIELD
2235 uint32_t rsvd1:24;
2236 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2237#else /* __LITTLE_ENDIAN_BITFIELD */
2238 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2239 uint32_t rsvd1:24;
2240#endif
2241
2242#ifdef __BIG_ENDIAN_BITFIELD
2243 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2244 uint8_t rsvd2;
2245 uint16_t link_flags;
2246#else /* __LITTLE_ENDIAN_BITFIELD */
2247 uint16_t link_flags;
2248 uint8_t rsvd2;
2249 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2250#endif
2251
2252#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2253#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2254#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2255#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2256#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2257#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2258#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2259
2260#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2261#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2262#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2263
2264 uint32_t link_speed;
2265#define LINK_SPEED_AUTO 0x0 /* Auto selection */
2266#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2267#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2268#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2269#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2270#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2271#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2272#define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2273#define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2274#define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2275#define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2276
2277} INIT_LINK_VAR;
2278
2279/* Structure for MB Command DOWN_LINK (06) */
2280
2281typedef struct {
2282 uint32_t rsvd1;
2283} DOWN_LINK_VAR;
2284
2285/* Structure for MB Command CONFIG_LINK (07) */
2286
2287typedef struct {
2288#ifdef __BIG_ENDIAN_BITFIELD
2289 uint32_t cr:1;
2290 uint32_t ci:1;
2291 uint32_t cr_delay:6;
2292 uint32_t cr_count:8;
2293 uint32_t rsvd1:8;
2294 uint32_t MaxBBC:8;
2295#else /* __LITTLE_ENDIAN_BITFIELD */
2296 uint32_t MaxBBC:8;
2297 uint32_t rsvd1:8;
2298 uint32_t cr_count:8;
2299 uint32_t cr_delay:6;
2300 uint32_t ci:1;
2301 uint32_t cr:1;
2302#endif
2303
2304 uint32_t myId;
2305 uint32_t rsvd2;
2306 uint32_t edtov;
2307 uint32_t arbtov;
2308 uint32_t ratov;
2309 uint32_t rttov;
2310 uint32_t altov;
2311 uint32_t crtov;
2312
2313#ifdef __BIG_ENDIAN_BITFIELD
2314 uint32_t rsvd4:19;
2315 uint32_t cscn:1;
2316 uint32_t bbscn:4;
2317 uint32_t rsvd3:8;
2318#else /* __LITTLE_ENDIAN_BITFIELD */
2319 uint32_t rsvd3:8;
2320 uint32_t bbscn:4;
2321 uint32_t cscn:1;
2322 uint32_t rsvd4:19;
2323#endif
2324
2325#ifdef __BIG_ENDIAN_BITFIELD
2326 uint32_t rrq_enable:1;
2327 uint32_t rrq_immed:1;
2328 uint32_t rsvd5:29;
2329 uint32_t ack0_enable:1;
2330#else /* __LITTLE_ENDIAN_BITFIELD */
2331 uint32_t ack0_enable:1;
2332 uint32_t rsvd5:29;
2333 uint32_t rrq_immed:1;
2334 uint32_t rrq_enable:1;
2335#endif
2336} CONFIG_LINK;
2337
2338/* Structure for MB Command PART_SLIM (08)
2339 * will be removed since SLI1 is no longer supported!
2340 */
2341typedef struct {
2342#ifdef __BIG_ENDIAN_BITFIELD
2343 uint16_t offCiocb;
2344 uint16_t numCiocb;
2345 uint16_t offRiocb;
2346 uint16_t numRiocb;
2347#else /* __LITTLE_ENDIAN_BITFIELD */
2348 uint16_t numCiocb;
2349 uint16_t offCiocb;
2350 uint16_t numRiocb;
2351 uint16_t offRiocb;
2352#endif
2353} RING_DEF;
2354
2355typedef struct {
2356#ifdef __BIG_ENDIAN_BITFIELD
2357 uint32_t unused1:24;
2358 uint32_t numRing:8;
2359#else /* __LITTLE_ENDIAN_BITFIELD */
2360 uint32_t numRing:8;
2361 uint32_t unused1:24;
2362#endif
2363
2364 RING_DEF ringdef[4];
2365 uint32_t hbainit;
2366} PART_SLIM_VAR;
2367
2368/* Structure for MB Command CONFIG_RING (09) */
2369
2370typedef struct {
2371#ifdef __BIG_ENDIAN_BITFIELD
2372 uint32_t unused2:6;
2373 uint32_t recvSeq:1;
2374 uint32_t recvNotify:1;
2375 uint32_t numMask:8;
2376 uint32_t profile:8;
2377 uint32_t unused1:4;
2378 uint32_t ring:4;
2379#else /* __LITTLE_ENDIAN_BITFIELD */
2380 uint32_t ring:4;
2381 uint32_t unused1:4;
2382 uint32_t profile:8;
2383 uint32_t numMask:8;
2384 uint32_t recvNotify:1;
2385 uint32_t recvSeq:1;
2386 uint32_t unused2:6;
2387#endif
2388
2389#ifdef __BIG_ENDIAN_BITFIELD
2390 uint16_t maxRespXchg;
2391 uint16_t maxOrigXchg;
2392#else /* __LITTLE_ENDIAN_BITFIELD */
2393 uint16_t maxOrigXchg;
2394 uint16_t maxRespXchg;
2395#endif
2396
2397 RR_REG rrRegs[6];
2398} CONFIG_RING_VAR;
2399
2400/* Structure for MB Command RESET_RING (10) */
2401
2402typedef struct {
2403 uint32_t ring_no;
2404} RESET_RING_VAR;
2405
2406/* Structure for MB Command READ_CONFIG (11) */
2407
2408typedef struct {
2409#ifdef __BIG_ENDIAN_BITFIELD
2410 uint32_t cr:1;
2411 uint32_t ci:1;
2412 uint32_t cr_delay:6;
2413 uint32_t cr_count:8;
2414 uint32_t InitBBC:8;
2415 uint32_t MaxBBC:8;
2416#else /* __LITTLE_ENDIAN_BITFIELD */
2417 uint32_t MaxBBC:8;
2418 uint32_t InitBBC:8;
2419 uint32_t cr_count:8;
2420 uint32_t cr_delay:6;
2421 uint32_t ci:1;
2422 uint32_t cr:1;
2423#endif
2424
2425#ifdef __BIG_ENDIAN_BITFIELD
2426 uint32_t topology:8;
2427 uint32_t myDid:24;
2428#else /* __LITTLE_ENDIAN_BITFIELD */
2429 uint32_t myDid:24;
2430 uint32_t topology:8;
2431#endif
2432
2433 /* Defines for topology (defined previously) */
2434#ifdef __BIG_ENDIAN_BITFIELD
2435 uint32_t AR:1;
2436 uint32_t IR:1;
2437 uint32_t rsvd1:29;
2438 uint32_t ack0:1;
2439#else /* __LITTLE_ENDIAN_BITFIELD */
2440 uint32_t ack0:1;
2441 uint32_t rsvd1:29;
2442 uint32_t IR:1;
2443 uint32_t AR:1;
2444#endif
2445
2446 uint32_t edtov;
2447 uint32_t arbtov;
2448 uint32_t ratov;
2449 uint32_t rttov;
2450 uint32_t altov;
2451 uint32_t lmt;
2452#define LMT_RESERVED 0x000 /* Not used */
2453#define LMT_1Gb 0x004
2454#define LMT_2Gb 0x008
2455#define LMT_4Gb 0x040
2456#define LMT_8Gb 0x080
2457#define LMT_10Gb 0x100
2458#define LMT_16Gb 0x200
2459#define LMT_32Gb 0x400
2460#define LMT_64Gb 0x800
2461#define LMT_128Gb 0x1000
2462#define LMT_256Gb 0x2000
2463 uint32_t rsvd2;
2464 uint32_t rsvd3;
2465 uint32_t max_xri;
2466 uint32_t max_iocb;
2467 uint32_t max_rpi;
2468 uint32_t avail_xri;
2469 uint32_t avail_iocb;
2470 uint32_t avail_rpi;
2471 uint32_t max_vpi;
2472 uint32_t rsvd4;
2473 uint32_t rsvd5;
2474 uint32_t avail_vpi;
2475} READ_CONFIG_VAR;
2476
2477/* Structure for MB Command READ_RCONFIG (12) */
2478
2479typedef struct {
2480#ifdef __BIG_ENDIAN_BITFIELD
2481 uint32_t rsvd2:7;
2482 uint32_t recvNotify:1;
2483 uint32_t numMask:8;
2484 uint32_t profile:8;
2485 uint32_t rsvd1:4;
2486 uint32_t ring:4;
2487#else /* __LITTLE_ENDIAN_BITFIELD */
2488 uint32_t ring:4;
2489 uint32_t rsvd1:4;
2490 uint32_t profile:8;
2491 uint32_t numMask:8;
2492 uint32_t recvNotify:1;
2493 uint32_t rsvd2:7;
2494#endif
2495
2496#ifdef __BIG_ENDIAN_BITFIELD
2497 uint16_t maxResp;
2498 uint16_t maxOrig;
2499#else /* __LITTLE_ENDIAN_BITFIELD */
2500 uint16_t maxOrig;
2501 uint16_t maxResp;
2502#endif
2503
2504 RR_REG rrRegs[6];
2505
2506#ifdef __BIG_ENDIAN_BITFIELD
2507 uint16_t cmdRingOffset;
2508 uint16_t cmdEntryCnt;
2509 uint16_t rspRingOffset;
2510 uint16_t rspEntryCnt;
2511 uint16_t nextCmdOffset;
2512 uint16_t rsvd3;
2513 uint16_t nextRspOffset;
2514 uint16_t rsvd4;
2515#else /* __LITTLE_ENDIAN_BITFIELD */
2516 uint16_t cmdEntryCnt;
2517 uint16_t cmdRingOffset;
2518 uint16_t rspEntryCnt;
2519 uint16_t rspRingOffset;
2520 uint16_t rsvd3;
2521 uint16_t nextCmdOffset;
2522 uint16_t rsvd4;
2523 uint16_t nextRspOffset;
2524#endif
2525} READ_RCONF_VAR;
2526
2527/* Structure for MB Command READ_SPARM (13) */
2528/* Structure for MB Command READ_SPARM64 (0x8D) */
2529
2530typedef struct {
2531 uint32_t rsvd1;
2532 uint32_t rsvd2;
2533 union {
2534 struct ulp_bde sp; /* This BDE points to struct serv_parm
2535 structure */
2536 struct ulp_bde64 sp64;
2537 } un;
2538#ifdef __BIG_ENDIAN_BITFIELD
2539 uint16_t rsvd3;
2540 uint16_t vpi;
2541#else /* __LITTLE_ENDIAN_BITFIELD */
2542 uint16_t vpi;
2543 uint16_t rsvd3;
2544#endif
2545} READ_SPARM_VAR;
2546
2547/* Structure for MB Command READ_STATUS (14) */
2548
2549typedef struct {
2550#ifdef __BIG_ENDIAN_BITFIELD
2551 uint32_t rsvd1:31;
2552 uint32_t clrCounters:1;
2553 uint16_t activeXriCnt;
2554 uint16_t activeRpiCnt;
2555#else /* __LITTLE_ENDIAN_BITFIELD */
2556 uint32_t clrCounters:1;
2557 uint32_t rsvd1:31;
2558 uint16_t activeRpiCnt;
2559 uint16_t activeXriCnt;
2560#endif
2561
2562 uint32_t xmitByteCnt;
2563 uint32_t rcvByteCnt;
2564 uint32_t xmitFrameCnt;
2565 uint32_t rcvFrameCnt;
2566 uint32_t xmitSeqCnt;
2567 uint32_t rcvSeqCnt;
2568 uint32_t totalOrigExchanges;
2569 uint32_t totalRespExchanges;
2570 uint32_t rcvPbsyCnt;
2571 uint32_t rcvFbsyCnt;
2572} READ_STATUS_VAR;
2573
2574/* Structure for MB Command READ_RPI (15) */
2575/* Structure for MB Command READ_RPI64 (0x8F) */
2576
2577typedef struct {
2578#ifdef __BIG_ENDIAN_BITFIELD
2579 uint16_t nextRpi;
2580 uint16_t reqRpi;
2581 uint32_t rsvd2:8;
2582 uint32_t DID:24;
2583#else /* __LITTLE_ENDIAN_BITFIELD */
2584 uint16_t reqRpi;
2585 uint16_t nextRpi;
2586 uint32_t DID:24;
2587 uint32_t rsvd2:8;
2588#endif
2589
2590 union {
2591 struct ulp_bde sp;
2592 struct ulp_bde64 sp64;
2593 } un;
2594
2595} READ_RPI_VAR;
2596
2597/* Structure for MB Command READ_XRI (16) */
2598
2599typedef struct {
2600#ifdef __BIG_ENDIAN_BITFIELD
2601 uint16_t nextXri;
2602 uint16_t reqXri;
2603 uint16_t rsvd1;
2604 uint16_t rpi;
2605 uint32_t rsvd2:8;
2606 uint32_t DID:24;
2607 uint32_t rsvd3:8;
2608 uint32_t SID:24;
2609 uint32_t rsvd4;
2610 uint8_t seqId;
2611 uint8_t rsvd5;
2612 uint16_t seqCount;
2613 uint16_t oxId;
2614 uint16_t rxId;
2615 uint32_t rsvd6:30;
2616 uint32_t si:1;
2617 uint32_t exchOrig:1;
2618#else /* __LITTLE_ENDIAN_BITFIELD */
2619 uint16_t reqXri;
2620 uint16_t nextXri;
2621 uint16_t rpi;
2622 uint16_t rsvd1;
2623 uint32_t DID:24;
2624 uint32_t rsvd2:8;
2625 uint32_t SID:24;
2626 uint32_t rsvd3:8;
2627 uint32_t rsvd4;
2628 uint16_t seqCount;
2629 uint8_t rsvd5;
2630 uint8_t seqId;
2631 uint16_t rxId;
2632 uint16_t oxId;
2633 uint32_t exchOrig:1;
2634 uint32_t si:1;
2635 uint32_t rsvd6:30;
2636#endif
2637} READ_XRI_VAR;
2638
2639/* Structure for MB Command READ_REV (17) */
2640
2641typedef struct {
2642#ifdef __BIG_ENDIAN_BITFIELD
2643 uint32_t cv:1;
2644 uint32_t rr:1;
2645 uint32_t rsvd2:2;
2646 uint32_t v3req:1;
2647 uint32_t v3rsp:1;
2648 uint32_t rsvd1:25;
2649 uint32_t rv:1;
2650#else /* __LITTLE_ENDIAN_BITFIELD */
2651 uint32_t rv:1;
2652 uint32_t rsvd1:25;
2653 uint32_t v3rsp:1;
2654 uint32_t v3req:1;
2655 uint32_t rsvd2:2;
2656 uint32_t rr:1;
2657 uint32_t cv:1;
2658#endif
2659
2660 uint32_t biuRev;
2661 uint32_t smRev;
2662 union {
2663 uint32_t smFwRev;
2664 struct {
2665#ifdef __BIG_ENDIAN_BITFIELD
2666 uint8_t ProgType;
2667 uint8_t ProgId;
2668 uint16_t ProgVer:4;
2669 uint16_t ProgRev:4;
2670 uint16_t ProgFixLvl:2;
2671 uint16_t ProgDistType:2;
2672 uint16_t DistCnt:4;
2673#else /* __LITTLE_ENDIAN_BITFIELD */
2674 uint16_t DistCnt:4;
2675 uint16_t ProgDistType:2;
2676 uint16_t ProgFixLvl:2;
2677 uint16_t ProgRev:4;
2678 uint16_t ProgVer:4;
2679 uint8_t ProgId;
2680 uint8_t ProgType;
2681#endif
2682
2683 } b;
2684 } un;
2685 uint32_t endecRev;
2686#ifdef __BIG_ENDIAN_BITFIELD
2687 uint8_t feaLevelHigh;
2688 uint8_t feaLevelLow;
2689 uint8_t fcphHigh;
2690 uint8_t fcphLow;
2691#else /* __LITTLE_ENDIAN_BITFIELD */
2692 uint8_t fcphLow;
2693 uint8_t fcphHigh;
2694 uint8_t feaLevelLow;
2695 uint8_t feaLevelHigh;
2696#endif
2697
2698 uint32_t postKernRev;
2699 uint32_t opFwRev;
2700 uint8_t opFwName[16];
2701 uint32_t sli1FwRev;
2702 uint8_t sli1FwName[16];
2703 uint32_t sli2FwRev;
2704 uint8_t sli2FwName[16];
2705 uint32_t sli3Feat;
2706 uint32_t RandomData[6];
2707} READ_REV_VAR;
2708
2709/* Structure for MB Command READ_LINK_STAT (18) */
2710
2711typedef struct {
2712 uint32_t word0;
2713
2714#define lpfc_read_link_stat_rec_SHIFT 0
2715#define lpfc_read_link_stat_rec_MASK 0x1
2716#define lpfc_read_link_stat_rec_WORD word0
2717
2718#define lpfc_read_link_stat_gec_SHIFT 1
2719#define lpfc_read_link_stat_gec_MASK 0x1
2720#define lpfc_read_link_stat_gec_WORD word0
2721
2722#define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2723#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2724#define lpfc_read_link_stat_w02oftow23of_WORD word0
2725
2726#define lpfc_read_link_stat_rsvd_SHIFT 24
2727#define lpfc_read_link_stat_rsvd_MASK 0x1F
2728#define lpfc_read_link_stat_rsvd_WORD word0
2729
2730#define lpfc_read_link_stat_gec2_SHIFT 29
2731#define lpfc_read_link_stat_gec2_MASK 0x1
2732#define lpfc_read_link_stat_gec2_WORD word0
2733
2734#define lpfc_read_link_stat_clrc_SHIFT 30
2735#define lpfc_read_link_stat_clrc_MASK 0x1
2736#define lpfc_read_link_stat_clrc_WORD word0
2737
2738#define lpfc_read_link_stat_clof_SHIFT 31
2739#define lpfc_read_link_stat_clof_MASK 0x1
2740#define lpfc_read_link_stat_clof_WORD word0
2741
2742 uint32_t linkFailureCnt;
2743 uint32_t lossSyncCnt;
2744 uint32_t lossSignalCnt;
2745 uint32_t primSeqErrCnt;
2746 uint32_t invalidXmitWord;
2747 uint32_t crcCnt;
2748 uint32_t primSeqTimeout;
2749 uint32_t elasticOverrun;
2750 uint32_t arbTimeout;
2751 uint32_t advRecBufCredit;
2752 uint32_t curRecBufCredit;
2753 uint32_t advTransBufCredit;
2754 uint32_t curTransBufCredit;
2755 uint32_t recEofCount;
2756 uint32_t recEofdtiCount;
2757 uint32_t recEofniCount;
2758 uint32_t recSofcount;
2759 uint32_t rsvd1;
2760 uint32_t rsvd2;
2761 uint32_t recDrpXriCount;
2762 uint32_t fecCorrBlkCount;
2763 uint32_t fecUncorrBlkCount;
2764} READ_LNK_VAR;
2765
2766/* Structure for MB Command REG_LOGIN (19) */
2767/* Structure for MB Command REG_LOGIN64 (0x93) */
2768
2769typedef struct {
2770#ifdef __BIG_ENDIAN_BITFIELD
2771 uint16_t rsvd1;
2772 uint16_t rpi;
2773 uint32_t rsvd2:8;
2774 uint32_t did:24;
2775#else /* __LITTLE_ENDIAN_BITFIELD */
2776 uint16_t rpi;
2777 uint16_t rsvd1;
2778 uint32_t did:24;
2779 uint32_t rsvd2:8;
2780#endif
2781
2782 union {
2783 struct ulp_bde sp;
2784 struct ulp_bde64 sp64;
2785 } un;
2786
2787#ifdef __BIG_ENDIAN_BITFIELD
2788 uint16_t rsvd6;
2789 uint16_t vpi;
2790#else /* __LITTLE_ENDIAN_BITFIELD */
2791 uint16_t vpi;
2792 uint16_t rsvd6;
2793#endif
2794
2795} REG_LOGIN_VAR;
2796
2797/* Word 30 contents for REG_LOGIN */
2798typedef union {
2799 struct {
2800#ifdef __BIG_ENDIAN_BITFIELD
2801 uint16_t rsvd1:12;
2802 uint16_t wd30_class:4;
2803 uint16_t xri;
2804#else /* __LITTLE_ENDIAN_BITFIELD */
2805 uint16_t xri;
2806 uint16_t wd30_class:4;
2807 uint16_t rsvd1:12;
2808#endif
2809 } f;
2810 uint32_t word;
2811} REG_WD30;
2812
2813/* Structure for MB Command UNREG_LOGIN (20) */
2814
2815typedef struct {
2816#ifdef __BIG_ENDIAN_BITFIELD
2817 uint16_t rsvd1;
2818 uint16_t rpi;
2819 uint32_t rsvd2;
2820 uint32_t rsvd3;
2821 uint32_t rsvd4;
2822 uint32_t rsvd5;
2823 uint16_t rsvd6;
2824 uint16_t vpi;
2825#else /* __LITTLE_ENDIAN_BITFIELD */
2826 uint16_t rpi;
2827 uint16_t rsvd1;
2828 uint32_t rsvd2;
2829 uint32_t rsvd3;
2830 uint32_t rsvd4;
2831 uint32_t rsvd5;
2832 uint16_t vpi;
2833 uint16_t rsvd6;
2834#endif
2835} UNREG_LOGIN_VAR;
2836
2837/* Structure for MB Command REG_VPI (0x96) */
2838typedef struct {
2839#ifdef __BIG_ENDIAN_BITFIELD
2840 uint32_t rsvd1;
2841 uint32_t rsvd2:7;
2842 uint32_t upd:1;
2843 uint32_t sid:24;
2844 uint32_t wwn[2];
2845 uint32_t rsvd5;
2846 uint16_t vfi;
2847 uint16_t vpi;
2848#else /* __LITTLE_ENDIAN */
2849 uint32_t rsvd1;
2850 uint32_t sid:24;
2851 uint32_t upd:1;
2852 uint32_t rsvd2:7;
2853 uint32_t wwn[2];
2854 uint32_t rsvd5;
2855 uint16_t vpi;
2856 uint16_t vfi;
2857#endif
2858} REG_VPI_VAR;
2859
2860/* Structure for MB Command UNREG_VPI (0x97) */
2861typedef struct {
2862 uint32_t rsvd1;
2863#ifdef __BIG_ENDIAN_BITFIELD
2864 uint16_t rsvd2;
2865 uint16_t sli4_vpi;
2866#else /* __LITTLE_ENDIAN */
2867 uint16_t sli4_vpi;
2868 uint16_t rsvd2;
2869#endif
2870 uint32_t rsvd3;
2871 uint32_t rsvd4;
2872 uint32_t rsvd5;
2873#ifdef __BIG_ENDIAN_BITFIELD
2874 uint16_t rsvd6;
2875 uint16_t vpi;
2876#else /* __LITTLE_ENDIAN */
2877 uint16_t vpi;
2878 uint16_t rsvd6;
2879#endif
2880} UNREG_VPI_VAR;
2881
2882/* Structure for MB Command UNREG_D_ID (0x23) */
2883
2884typedef struct {
2885 uint32_t did;
2886 uint32_t rsvd2;
2887 uint32_t rsvd3;
2888 uint32_t rsvd4;
2889 uint32_t rsvd5;
2890#ifdef __BIG_ENDIAN_BITFIELD
2891 uint16_t rsvd6;
2892 uint16_t vpi;
2893#else
2894 uint16_t vpi;
2895 uint16_t rsvd6;
2896#endif
2897} UNREG_D_ID_VAR;
2898
2899/* Structure for MB Command READ_TOPOLOGY (0x95) */
2900struct lpfc_mbx_read_top {
2901 uint32_t eventTag; /* Event tag */
2902 uint32_t word2;
2903#define lpfc_mbx_read_top_fa_SHIFT 12
2904#define lpfc_mbx_read_top_fa_MASK 0x00000001
2905#define lpfc_mbx_read_top_fa_WORD word2
2906#define lpfc_mbx_read_top_mm_SHIFT 11
2907#define lpfc_mbx_read_top_mm_MASK 0x00000001
2908#define lpfc_mbx_read_top_mm_WORD word2
2909#define lpfc_mbx_read_top_pb_SHIFT 9
2910#define lpfc_mbx_read_top_pb_MASK 0X00000001
2911#define lpfc_mbx_read_top_pb_WORD word2
2912#define lpfc_mbx_read_top_il_SHIFT 8
2913#define lpfc_mbx_read_top_il_MASK 0x00000001
2914#define lpfc_mbx_read_top_il_WORD word2
2915#define lpfc_mbx_read_top_att_type_SHIFT 0
2916#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2917#define lpfc_mbx_read_top_att_type_WORD word2
2918#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2919#define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2920#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2921#define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
2922 uint32_t word3;
2923#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2924#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2925#define lpfc_mbx_read_top_alpa_granted_WORD word3
2926#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2927#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2928#define lpfc_mbx_read_top_lip_alps_WORD word3
2929#define lpfc_mbx_read_top_lip_type_SHIFT 8
2930#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2931#define lpfc_mbx_read_top_lip_type_WORD word3
2932#define lpfc_mbx_read_top_topology_SHIFT 0
2933#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2934#define lpfc_mbx_read_top_topology_WORD word3
2935#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2936#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2937#define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2938 /* store the LILP AL_PA position map into */
2939 struct ulp_bde64 lilpBde64;
2940#define LPFC_ALPA_MAP_SIZE 128
2941 uint32_t word7;
2942#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2943#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2944#define lpfc_mbx_read_top_ld_lu_WORD word7
2945#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2946#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2947#define lpfc_mbx_read_top_ld_tf_WORD word7
2948#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2949#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2950#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2951#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2952#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2953#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2954#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2955#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2956#define lpfc_mbx_read_top_ld_tx_WORD word7
2957#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2958#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2959#define lpfc_mbx_read_top_ld_rx_WORD word7
2960 uint32_t word8;
2961#define lpfc_mbx_read_top_lu_SHIFT 31
2962#define lpfc_mbx_read_top_lu_MASK 0x00000001
2963#define lpfc_mbx_read_top_lu_WORD word8
2964#define lpfc_mbx_read_top_tf_SHIFT 30
2965#define lpfc_mbx_read_top_tf_MASK 0x00000001
2966#define lpfc_mbx_read_top_tf_WORD word8
2967#define lpfc_mbx_read_top_link_spd_SHIFT 8
2968#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2969#define lpfc_mbx_read_top_link_spd_WORD word8
2970#define lpfc_mbx_read_top_nl_port_SHIFT 4
2971#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2972#define lpfc_mbx_read_top_nl_port_WORD word8
2973#define lpfc_mbx_read_top_tx_SHIFT 2
2974#define lpfc_mbx_read_top_tx_MASK 0x00000003
2975#define lpfc_mbx_read_top_tx_WORD word8
2976#define lpfc_mbx_read_top_rx_SHIFT 0
2977#define lpfc_mbx_read_top_rx_MASK 0x00000003
2978#define lpfc_mbx_read_top_rx_WORD word8
2979#define LPFC_LINK_SPEED_UNKNOWN 0x0
2980#define LPFC_LINK_SPEED_1GHZ 0x04
2981#define LPFC_LINK_SPEED_2GHZ 0x08
2982#define LPFC_LINK_SPEED_4GHZ 0x10
2983#define LPFC_LINK_SPEED_8GHZ 0x20
2984#define LPFC_LINK_SPEED_10GHZ 0x40
2985#define LPFC_LINK_SPEED_16GHZ 0x80
2986#define LPFC_LINK_SPEED_32GHZ 0x90
2987#define LPFC_LINK_SPEED_64GHZ 0xA0
2988#define LPFC_LINK_SPEED_128GHZ 0xB0
2989#define LPFC_LINK_SPEED_256GHZ 0xC0
2990};
2991
2992/* Structure for MB Command CLEAR_LA (22) */
2993
2994typedef struct {
2995 uint32_t eventTag; /* Event tag */
2996 uint32_t rsvd1;
2997} CLEAR_LA_VAR;
2998
2999/* Structure for MB Command DUMP */
3000
3001typedef struct {
3002#ifdef __BIG_ENDIAN_BITFIELD
3003 uint32_t rsvd:25;
3004 uint32_t ra:1;
3005 uint32_t co:1;
3006 uint32_t cv:1;
3007 uint32_t type:4;
3008 uint32_t entry_index:16;
3009 uint32_t region_id:16;
3010#else /* __LITTLE_ENDIAN_BITFIELD */
3011 uint32_t type:4;
3012 uint32_t cv:1;
3013 uint32_t co:1;
3014 uint32_t ra:1;
3015 uint32_t rsvd:25;
3016 uint32_t region_id:16;
3017 uint32_t entry_index:16;
3018#endif
3019
3020 uint32_t sli4_length;
3021 uint32_t word_cnt;
3022 uint32_t resp_offset;
3023} DUMP_VAR;
3024
3025#define DMP_MEM_REG 0x1
3026#define DMP_NV_PARAMS 0x2
3027#define DMP_LMSD 0x3 /* Link Module Serial Data */
3028#define DMP_WELL_KNOWN 0x4
3029
3030#define DMP_REGION_VPD 0xe
3031#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3032#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3033#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3034
3035#define DMP_REGION_VPORT 0x16 /* VPort info region */
3036#define DMP_VPORT_REGION_SIZE 0x200
3037#define DMP_MBOX_OFFSET_WORD 0x5
3038
3039#define DMP_REGION_23 0x17 /* fcoe param and port state region */
3040#define DMP_RGN23_SIZE 0x400
3041
3042#define WAKE_UP_PARMS_REGION_ID 4
3043#define WAKE_UP_PARMS_WORD_SIZE 15
3044
3045struct vport_rec {
3046 uint8_t wwpn[8];
3047 uint8_t wwnn[8];
3048};
3049
3050#define VPORT_INFO_SIG 0x32324752
3051#define VPORT_INFO_REV_MASK 0xff
3052#define VPORT_INFO_REV 0x1
3053#define MAX_STATIC_VPORT_COUNT 16
3054struct static_vport_info {
3055 uint32_t signature;
3056 uint32_t rev;
3057 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3058 uint32_t resvd[66];
3059};
3060
3061/* Option rom version structure */
3062struct prog_id {
3063#ifdef __BIG_ENDIAN_BITFIELD
3064 uint8_t type;
3065 uint8_t id;
3066 uint32_t ver:4; /* Major Version */
3067 uint32_t rev:4; /* Revision */
3068 uint32_t lev:2; /* Level */
3069 uint32_t dist:2; /* Dist Type */
3070 uint32_t num:4; /* number after dist type */
3071#else /* __LITTLE_ENDIAN_BITFIELD */
3072 uint32_t num:4; /* number after dist type */
3073 uint32_t dist:2; /* Dist Type */
3074 uint32_t lev:2; /* Level */
3075 uint32_t rev:4; /* Revision */
3076 uint32_t ver:4; /* Major Version */
3077 uint8_t id;
3078 uint8_t type;
3079#endif
3080};
3081
3082/* Structure for MB Command UPDATE_CFG (0x1B) */
3083
3084struct update_cfg_var {
3085#ifdef __BIG_ENDIAN_BITFIELD
3086 uint32_t rsvd2:16;
3087 uint32_t type:8;
3088 uint32_t rsvd:1;
3089 uint32_t ra:1;
3090 uint32_t co:1;
3091 uint32_t cv:1;
3092 uint32_t req:4;
3093 uint32_t entry_length:16;
3094 uint32_t region_id:16;
3095#else /* __LITTLE_ENDIAN_BITFIELD */
3096 uint32_t req:4;
3097 uint32_t cv:1;
3098 uint32_t co:1;
3099 uint32_t ra:1;
3100 uint32_t rsvd:1;
3101 uint32_t type:8;
3102 uint32_t rsvd2:16;
3103 uint32_t region_id:16;
3104 uint32_t entry_length:16;
3105#endif
3106
3107 uint32_t resp_info;
3108 uint32_t byte_cnt;
3109 uint32_t data_offset;
3110};
3111
3112struct hbq_mask {
3113#ifdef __BIG_ENDIAN_BITFIELD
3114 uint8_t tmatch;
3115 uint8_t tmask;
3116 uint8_t rctlmatch;
3117 uint8_t rctlmask;
3118#else /* __LITTLE_ENDIAN */
3119 uint8_t rctlmask;
3120 uint8_t rctlmatch;
3121 uint8_t tmask;
3122 uint8_t tmatch;
3123#endif
3124};
3125
3126
3127/* Structure for MB Command CONFIG_HBQ (7c) */
3128
3129struct config_hbq_var {
3130#ifdef __BIG_ENDIAN_BITFIELD
3131 uint32_t rsvd1 :7;
3132 uint32_t recvNotify :1; /* Receive Notification */
3133 uint32_t numMask :8; /* # Mask Entries */
3134 uint32_t profile :8; /* Selection Profile */
3135 uint32_t rsvd2 :8;
3136#else /* __LITTLE_ENDIAN */
3137 uint32_t rsvd2 :8;
3138 uint32_t profile :8; /* Selection Profile */
3139 uint32_t numMask :8; /* # Mask Entries */
3140 uint32_t recvNotify :1; /* Receive Notification */
3141 uint32_t rsvd1 :7;
3142#endif
3143
3144#ifdef __BIG_ENDIAN_BITFIELD
3145 uint32_t hbqId :16;
3146 uint32_t rsvd3 :12;
3147 uint32_t ringMask :4;
3148#else /* __LITTLE_ENDIAN */
3149 uint32_t ringMask :4;
3150 uint32_t rsvd3 :12;
3151 uint32_t hbqId :16;
3152#endif
3153
3154#ifdef __BIG_ENDIAN_BITFIELD
3155 uint32_t entry_count :16;
3156 uint32_t rsvd4 :8;
3157 uint32_t headerLen :8;
3158#else /* __LITTLE_ENDIAN */
3159 uint32_t headerLen :8;
3160 uint32_t rsvd4 :8;
3161 uint32_t entry_count :16;
3162#endif
3163
3164 uint32_t hbqaddrLow;
3165 uint32_t hbqaddrHigh;
3166
3167#ifdef __BIG_ENDIAN_BITFIELD
3168 uint32_t rsvd5 :31;
3169 uint32_t logEntry :1;
3170#else /* __LITTLE_ENDIAN */
3171 uint32_t logEntry :1;
3172 uint32_t rsvd5 :31;
3173#endif
3174
3175 uint32_t rsvd6; /* w7 */
3176 uint32_t rsvd7; /* w8 */
3177 uint32_t rsvd8; /* w9 */
3178
3179 struct hbq_mask hbqMasks[6];
3180
3181
3182 union {
3183 uint32_t allprofiles[12];
3184
3185 struct {
3186 #ifdef __BIG_ENDIAN_BITFIELD
3187 uint32_t seqlenoff :16;
3188 uint32_t maxlen :16;
3189 #else /* __LITTLE_ENDIAN */
3190 uint32_t maxlen :16;
3191 uint32_t seqlenoff :16;
3192 #endif
3193 #ifdef __BIG_ENDIAN_BITFIELD
3194 uint32_t rsvd1 :28;
3195 uint32_t seqlenbcnt :4;
3196 #else /* __LITTLE_ENDIAN */
3197 uint32_t seqlenbcnt :4;
3198 uint32_t rsvd1 :28;
3199 #endif
3200 uint32_t rsvd[10];
3201 } profile2;
3202
3203 struct {
3204 #ifdef __BIG_ENDIAN_BITFIELD
3205 uint32_t seqlenoff :16;
3206 uint32_t maxlen :16;
3207 #else /* __LITTLE_ENDIAN */
3208 uint32_t maxlen :16;
3209 uint32_t seqlenoff :16;
3210 #endif
3211 #ifdef __BIG_ENDIAN_BITFIELD
3212 uint32_t cmdcodeoff :28;
3213 uint32_t rsvd1 :12;
3214 uint32_t seqlenbcnt :4;
3215 #else /* __LITTLE_ENDIAN */
3216 uint32_t seqlenbcnt :4;
3217 uint32_t rsvd1 :12;
3218 uint32_t cmdcodeoff :28;
3219 #endif
3220 uint32_t cmdmatch[8];
3221
3222 uint32_t rsvd[2];
3223 } profile3;
3224
3225 struct {
3226 #ifdef __BIG_ENDIAN_BITFIELD
3227 uint32_t seqlenoff :16;
3228 uint32_t maxlen :16;
3229 #else /* __LITTLE_ENDIAN */
3230 uint32_t maxlen :16;
3231 uint32_t seqlenoff :16;
3232 #endif
3233 #ifdef __BIG_ENDIAN_BITFIELD
3234 uint32_t cmdcodeoff :28;
3235 uint32_t rsvd1 :12;
3236 uint32_t seqlenbcnt :4;
3237 #else /* __LITTLE_ENDIAN */
3238 uint32_t seqlenbcnt :4;
3239 uint32_t rsvd1 :12;
3240 uint32_t cmdcodeoff :28;
3241 #endif
3242 uint32_t cmdmatch[8];
3243
3244 uint32_t rsvd[2];
3245 } profile5;
3246
3247 } profiles;
3248
3249};
3250
3251
3252
3253/* Structure for MB Command CONFIG_PORT (0x88) */
3254typedef struct {
3255#ifdef __BIG_ENDIAN_BITFIELD
3256 uint32_t cBE : 1;
3257 uint32_t cET : 1;
3258 uint32_t cHpcb : 1;
3259 uint32_t cMA : 1;
3260 uint32_t sli_mode : 4;
3261 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3262 * config block */
3263#else /* __LITTLE_ENDIAN */
3264 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3265 * config block */
3266 uint32_t sli_mode : 4;
3267 uint32_t cMA : 1;
3268 uint32_t cHpcb : 1;
3269 uint32_t cET : 1;
3270 uint32_t cBE : 1;
3271#endif
3272
3273 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3274 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3275 uint32_t hbainit[5];
3276#ifdef __BIG_ENDIAN_BITFIELD
3277 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3278 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3279#else /* __LITTLE_ENDIAN */
3280 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3281 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3282#endif
3283
3284#ifdef __BIG_ENDIAN_BITFIELD
3285 uint32_t rsvd1 : 19; /* Reserved */
3286 uint32_t cdss : 1; /* Configure Data Security SLI */
3287 uint32_t casabt : 1; /* Configure async abts status notice */
3288 uint32_t rsvd2 : 2; /* Reserved */
3289 uint32_t cbg : 1; /* Configure BlockGuard */
3290 uint32_t cmv : 1; /* Configure Max VPIs */
3291 uint32_t ccrp : 1; /* Config Command Ring Polling */
3292 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3293 uint32_t chbs : 1; /* Cofigure Host Backing store */
3294 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3295 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3296 uint32_t cmx : 1; /* Configure Max XRIs */
3297 uint32_t cmr : 1; /* Configure Max RPIs */
3298#else /* __LITTLE_ENDIAN */
3299 uint32_t cmr : 1; /* Configure Max RPIs */
3300 uint32_t cmx : 1; /* Configure Max XRIs */
3301 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3302 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3303 uint32_t chbs : 1; /* Cofigure Host Backing store */
3304 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3305 uint32_t ccrp : 1; /* Config Command Ring Polling */
3306 uint32_t cmv : 1; /* Configure Max VPIs */
3307 uint32_t cbg : 1; /* Configure BlockGuard */
3308 uint32_t rsvd2 : 2; /* Reserved */
3309 uint32_t casabt : 1; /* Configure async abts status notice */
3310 uint32_t cdss : 1; /* Configure Data Security SLI */
3311 uint32_t rsvd1 : 19; /* Reserved */
3312#endif
3313#ifdef __BIG_ENDIAN_BITFIELD
3314 uint32_t rsvd3 : 19; /* Reserved */
3315 uint32_t gdss : 1; /* Configure Data Security SLI */
3316 uint32_t gasabt : 1; /* Grant async abts status notice */
3317 uint32_t rsvd4 : 2; /* Reserved */
3318 uint32_t gbg : 1; /* Grant BlockGuard */
3319 uint32_t gmv : 1; /* Grant Max VPIs */
3320 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3321 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3322 uint32_t ghbs : 1; /* Grant Host Backing Store */
3323 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3324 uint32_t gerbm : 1; /* Grant ERBM Request */
3325 uint32_t gmx : 1; /* Grant Max XRIs */
3326 uint32_t gmr : 1; /* Grant Max RPIs */
3327#else /* __LITTLE_ENDIAN */
3328 uint32_t gmr : 1; /* Grant Max RPIs */
3329 uint32_t gmx : 1; /* Grant Max XRIs */
3330 uint32_t gerbm : 1; /* Grant ERBM Request */
3331 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3332 uint32_t ghbs : 1; /* Grant Host Backing Store */
3333 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3334 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3335 uint32_t gmv : 1; /* Grant Max VPIs */
3336 uint32_t gbg : 1; /* Grant BlockGuard */
3337 uint32_t rsvd4 : 2; /* Reserved */
3338 uint32_t gasabt : 1; /* Grant async abts status notice */
3339 uint32_t gdss : 1; /* Configure Data Security SLI */
3340 uint32_t rsvd3 : 19; /* Reserved */
3341#endif
3342
3343#ifdef __BIG_ENDIAN_BITFIELD
3344 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3345 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3346#else /* __LITTLE_ENDIAN */
3347 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3348 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3349#endif
3350
3351#ifdef __BIG_ENDIAN_BITFIELD
3352 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3353 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3354#else /* __LITTLE_ENDIAN */
3355 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3356 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3357#endif
3358
3359 uint32_t rsvd6; /* Reserved */
3360
3361#ifdef __BIG_ENDIAN_BITFIELD
3362 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3363 uint32_t fips_level : 4; /* FIPS Level */
3364 uint32_t sec_err : 9; /* security crypto error */
3365 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3366#else /* __LITTLE_ENDIAN */
3367 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3368 uint32_t sec_err : 9; /* security crypto error */
3369 uint32_t fips_level : 4; /* FIPS Level */
3370 uint32_t fips_rev : 3; /* FIPS Spec Revision */
3371#endif
3372
3373} CONFIG_PORT_VAR;
3374
3375/* Structure for MB Command CONFIG_MSI (0x30) */
3376struct config_msi_var {
3377#ifdef __BIG_ENDIAN_BITFIELD
3378 uint32_t dfltMsgNum:8; /* Default message number */
3379 uint32_t rsvd1:11; /* Reserved */
3380 uint32_t NID:5; /* Number of secondary attention IDs */
3381 uint32_t rsvd2:5; /* Reserved */
3382 uint32_t dfltPresent:1; /* Default message number present */
3383 uint32_t addFlag:1; /* Add association flag */
3384 uint32_t reportFlag:1; /* Report association flag */
3385#else /* __LITTLE_ENDIAN_BITFIELD */
3386 uint32_t reportFlag:1; /* Report association flag */
3387 uint32_t addFlag:1; /* Add association flag */
3388 uint32_t dfltPresent:1; /* Default message number present */
3389 uint32_t rsvd2:5; /* Reserved */
3390 uint32_t NID:5; /* Number of secondary attention IDs */
3391 uint32_t rsvd1:11; /* Reserved */
3392 uint32_t dfltMsgNum:8; /* Default message number */
3393#endif
3394 uint32_t attentionConditions[2];
3395 uint8_t attentionId[16];
3396 uint8_t messageNumberByHA[64];
3397 uint8_t messageNumberByID[16];
3398 uint32_t autoClearHA[2];
3399#ifdef __BIG_ENDIAN_BITFIELD
3400 uint32_t rsvd3:16;
3401 uint32_t autoClearID:16;
3402#else /* __LITTLE_ENDIAN_BITFIELD */
3403 uint32_t autoClearID:16;
3404 uint32_t rsvd3:16;
3405#endif
3406 uint32_t rsvd4;
3407};
3408
3409/* SLI-2 Port Control Block */
3410
3411/* SLIM POINTER */
3412#define SLIMOFF 0x30 /* WORD */
3413
3414typedef struct _SLI2_RDSC {
3415 uint32_t cmdEntries;
3416 uint32_t cmdAddrLow;
3417 uint32_t cmdAddrHigh;
3418
3419 uint32_t rspEntries;
3420 uint32_t rspAddrLow;
3421 uint32_t rspAddrHigh;
3422} SLI2_RDSC;
3423
3424typedef struct _PCB {
3425#ifdef __BIG_ENDIAN_BITFIELD
3426 uint32_t type:8;
3427#define TYPE_NATIVE_SLI2 0x01
3428 uint32_t feature:8;
3429#define FEATURE_INITIAL_SLI2 0x01
3430 uint32_t rsvd:12;
3431 uint32_t maxRing:4;
3432#else /* __LITTLE_ENDIAN_BITFIELD */
3433 uint32_t maxRing:4;
3434 uint32_t rsvd:12;
3435 uint32_t feature:8;
3436#define FEATURE_INITIAL_SLI2 0x01
3437 uint32_t type:8;
3438#define TYPE_NATIVE_SLI2 0x01
3439#endif
3440
3441 uint32_t mailBoxSize;
3442 uint32_t mbAddrLow;
3443 uint32_t mbAddrHigh;
3444
3445 uint32_t hgpAddrLow;
3446 uint32_t hgpAddrHigh;
3447
3448 uint32_t pgpAddrLow;
3449 uint32_t pgpAddrHigh;
3450 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3451} PCB_t;
3452
3453/* NEW_FEATURE */
3454typedef struct {
3455#ifdef __BIG_ENDIAN_BITFIELD
3456 uint32_t rsvd0:27;
3457 uint32_t discardFarp:1;
3458 uint32_t IPEnable:1;
3459 uint32_t nodeName:1;
3460 uint32_t portName:1;
3461 uint32_t filterEnable:1;
3462#else /* __LITTLE_ENDIAN_BITFIELD */
3463 uint32_t filterEnable:1;
3464 uint32_t portName:1;
3465 uint32_t nodeName:1;
3466 uint32_t IPEnable:1;
3467 uint32_t discardFarp:1;
3468 uint32_t rsvd:27;
3469#endif
3470
3471 uint8_t portname[8]; /* Used to be struct lpfc_name */
3472 uint8_t nodename[8];
3473 uint32_t rsvd1;
3474 uint32_t rsvd2;
3475 uint32_t rsvd3;
3476 uint32_t IPAddress;
3477} CONFIG_FARP_VAR;
3478
3479/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3480
3481typedef struct {
3482#ifdef __BIG_ENDIAN_BITFIELD
3483 uint32_t rsvd:30;
3484 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3485#else /* __LITTLE_ENDIAN */
3486 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3487 uint32_t rsvd:30;
3488#endif
3489} ASYNCEVT_ENABLE_VAR;
3490
3491/* Union of all Mailbox Command types */
3492#define MAILBOX_CMD_WSIZE 32
3493#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3494/* ext_wsize times 4 bytes should not be greater than max xmit size */
3495#define MAILBOX_EXT_WSIZE 512
3496#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3497#define MAILBOX_HBA_EXT_OFFSET 0x100
3498/* max mbox xmit size is a page size for sysfs IO operations */
3499#define MAILBOX_SYSFS_MAX 4096
3500
3501typedef union {
3502 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3503 * feature/max ring number
3504 */
3505 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3506 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3507 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3508 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3509 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3510 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3511 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3512 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3513 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3514 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3515 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3516 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3517 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3518 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3519 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3520 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3521 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3522 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3523 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3524 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3525 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3526 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3527 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3528 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3529 * NEW_FEATURE
3530 */
3531 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3532 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3533 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3534 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3535 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3536 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3537 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3538 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3539 * (READ_EVENT_LOG)
3540 */
3541 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3542} MAILVARIANTS;
3543
3544/*
3545 * SLI-2 specific structures
3546 */
3547
3548struct lpfc_hgp {
3549 __le32 cmdPutInx;
3550 __le32 rspGetInx;
3551};
3552
3553struct lpfc_pgp {
3554 __le32 cmdGetInx;
3555 __le32 rspPutInx;
3556};
3557
3558struct sli2_desc {
3559 uint32_t unused1[16];
3560 struct lpfc_hgp host[MAX_SLI3_RINGS];
3561 struct lpfc_pgp port[MAX_SLI3_RINGS];
3562};
3563
3564struct sli3_desc {
3565 struct lpfc_hgp host[MAX_SLI3_RINGS];
3566 uint32_t reserved[8];
3567 uint32_t hbq_put[16];
3568};
3569
3570struct sli3_pgp {
3571 struct lpfc_pgp port[MAX_SLI3_RINGS];
3572 uint32_t hbq_get[16];
3573};
3574
3575union sli_var {
3576 struct sli2_desc s2;
3577 struct sli3_desc s3;
3578 struct sli3_pgp s3_pgp;
3579};
3580
3581typedef struct {
3582#ifdef __BIG_ENDIAN_BITFIELD
3583 uint16_t mbxStatus;
3584 uint8_t mbxCommand;
3585 uint8_t mbxReserved:6;
3586 uint8_t mbxHc:1;
3587 uint8_t mbxOwner:1; /* Low order bit first word */
3588#else /* __LITTLE_ENDIAN_BITFIELD */
3589 uint8_t mbxOwner:1; /* Low order bit first word */
3590 uint8_t mbxHc:1;
3591 uint8_t mbxReserved:6;
3592 uint8_t mbxCommand;
3593 uint16_t mbxStatus;
3594#endif
3595
3596 MAILVARIANTS un;
3597 union sli_var us;
3598} MAILBOX_t;
3599
3600/*
3601 * Begin Structure Definitions for IOCB Commands
3602 */
3603
3604typedef struct {
3605#ifdef __BIG_ENDIAN_BITFIELD
3606 uint8_t statAction;
3607 uint8_t statRsn;
3608 uint8_t statBaExp;
3609 uint8_t statLocalError;
3610#else /* __LITTLE_ENDIAN_BITFIELD */
3611 uint8_t statLocalError;
3612 uint8_t statBaExp;
3613 uint8_t statRsn;
3614 uint8_t statAction;
3615#endif
3616 /* statRsn P/F_RJT reason codes */
3617#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3618#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3619#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3620#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3621#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3622#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3623#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3624#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3625#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3626#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3627#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3628#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3629#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3630#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3631#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3632#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3633#define RJT_XCHG_ERR 0x11 /* Exchange error */
3634#define RJT_PROT_ERR 0x12 /* Protocol error */
3635#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3636#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3637#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3638#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3639#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3640#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3641#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3642#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3643
3644#define IOERR_SUCCESS 0x00 /* statLocalError */
3645#define IOERR_MISSING_CONTINUE 0x01
3646#define IOERR_SEQUENCE_TIMEOUT 0x02
3647#define IOERR_INTERNAL_ERROR 0x03
3648#define IOERR_INVALID_RPI 0x04
3649#define IOERR_NO_XRI 0x05
3650#define IOERR_ILLEGAL_COMMAND 0x06
3651#define IOERR_XCHG_DROPPED 0x07
3652#define IOERR_ILLEGAL_FIELD 0x08
3653#define IOERR_BAD_CONTINUE 0x09
3654#define IOERR_TOO_MANY_BUFFERS 0x0A
3655#define IOERR_RCV_BUFFER_WAITING 0x0B
3656#define IOERR_NO_CONNECTION 0x0C
3657#define IOERR_TX_DMA_FAILED 0x0D
3658#define IOERR_RX_DMA_FAILED 0x0E
3659#define IOERR_ILLEGAL_FRAME 0x0F
3660#define IOERR_EXTRA_DATA 0x10
3661#define IOERR_NO_RESOURCES 0x11
3662#define IOERR_RESERVED 0x12
3663#define IOERR_ILLEGAL_LENGTH 0x13
3664#define IOERR_UNSUPPORTED_FEATURE 0x14
3665#define IOERR_ABORT_IN_PROGRESS 0x15
3666#define IOERR_ABORT_REQUESTED 0x16
3667#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3668#define IOERR_LOOP_OPEN_FAILURE 0x18
3669#define IOERR_RING_RESET 0x19
3670#define IOERR_LINK_DOWN 0x1A
3671#define IOERR_CORRUPTED_DATA 0x1B
3672#define IOERR_CORRUPTED_RPI 0x1C
3673#define IOERR_OUT_OF_ORDER_DATA 0x1D
3674#define IOERR_OUT_OF_ORDER_ACK 0x1E
3675#define IOERR_DUP_FRAME 0x1F
3676#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3677#define IOERR_BAD_HOST_ADDRESS 0x21
3678#define IOERR_RCV_HDRBUF_WAITING 0x22
3679#define IOERR_MISSING_HDR_BUFFER 0x23
3680#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3681#define IOERR_ABORTMULT_REQUESTED 0x25
3682#define IOERR_BUFFER_SHORTAGE 0x28
3683#define IOERR_DEFAULT 0x29
3684#define IOERR_CNT 0x2A
3685#define IOERR_SLER_FAILURE 0x46
3686#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3687#define IOERR_SLER_REC_RJT_ERR 0x48
3688#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3689#define IOERR_SLER_SRR_RJT_ERR 0x4A
3690#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3691#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3692#define IOERR_SLER_ABTS_ERR 0x4E
3693#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3694#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3695#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3696#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3697#define IOERR_DRVR_MASK 0x100
3698#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3699#define IOERR_SLI_BRESET 0x102
3700#define IOERR_SLI_ABORTED 0x103
3701#define IOERR_PARAM_MASK 0x1ff
3702} PARM_ERR;
3703
3704typedef union {
3705 struct {
3706#ifdef __BIG_ENDIAN_BITFIELD
3707 uint8_t Rctl; /* R_CTL field */
3708 uint8_t Type; /* TYPE field */
3709 uint8_t Dfctl; /* DF_CTL field */
3710 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3711#else /* __LITTLE_ENDIAN_BITFIELD */
3712 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3713 uint8_t Dfctl; /* DF_CTL field */
3714 uint8_t Type; /* TYPE field */
3715 uint8_t Rctl; /* R_CTL field */
3716#endif
3717
3718#define BC 0x02 /* Broadcast Received - Fctl */
3719#define SI 0x04 /* Sequence Initiative */
3720#define LA 0x08 /* Ignore Link Attention state */
3721#define LS 0x80 /* Last Sequence */
3722 } hcsw;
3723 uint32_t reserved;
3724} WORD5;
3725
3726/* IOCB Command template for a generic response */
3727typedef struct {
3728 uint32_t reserved[4];
3729 PARM_ERR perr;
3730} GENERIC_RSP;
3731
3732/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3733typedef struct {
3734 struct ulp_bde xrsqbde[2];
3735 uint32_t xrsqRo; /* Starting Relative Offset */
3736 WORD5 w5; /* Header control/status word */
3737} XR_SEQ_FIELDS;
3738
3739/* IOCB Command template for ELS_REQUEST */
3740typedef struct {
3741 struct ulp_bde elsReq;
3742 struct ulp_bde elsRsp;
3743
3744#ifdef __BIG_ENDIAN_BITFIELD
3745 uint32_t word4Rsvd:7;
3746 uint32_t fl:1;
3747 uint32_t myID:24;
3748 uint32_t word5Rsvd:8;
3749 uint32_t remoteID:24;
3750#else /* __LITTLE_ENDIAN_BITFIELD */
3751 uint32_t myID:24;
3752 uint32_t fl:1;
3753 uint32_t word4Rsvd:7;
3754 uint32_t remoteID:24;
3755 uint32_t word5Rsvd:8;
3756#endif
3757} ELS_REQUEST;
3758
3759/* IOCB Command template for RCV_ELS_REQ */
3760typedef struct {
3761 struct ulp_bde elsReq[2];
3762 uint32_t parmRo;
3763
3764#ifdef __BIG_ENDIAN_BITFIELD
3765 uint32_t word5Rsvd:8;
3766 uint32_t remoteID:24;
3767#else /* __LITTLE_ENDIAN_BITFIELD */
3768 uint32_t remoteID:24;
3769 uint32_t word5Rsvd:8;
3770#endif
3771} RCV_ELS_REQ;
3772
3773/* IOCB Command template for ABORT / CLOSE_XRI */
3774typedef struct {
3775 uint32_t rsvd[3];
3776 uint32_t abortType;
3777#define ABORT_TYPE_ABTX 0x00000000
3778#define ABORT_TYPE_ABTS 0x00000001
3779 uint32_t parm;
3780#ifdef __BIG_ENDIAN_BITFIELD
3781 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3782 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3783#else /* __LITTLE_ENDIAN_BITFIELD */
3784 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3785 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3786#endif
3787} AC_XRI;
3788
3789/* IOCB Command template for ABORT_MXRI64 */
3790typedef struct {
3791 uint32_t rsvd[3];
3792 uint32_t abortType;
3793 uint32_t parm;
3794 uint32_t iotag32;
3795} A_MXRI64;
3796
3797/* IOCB Command template for GET_RPI */
3798typedef struct {
3799 uint32_t rsvd[4];
3800 uint32_t parmRo;
3801#ifdef __BIG_ENDIAN_BITFIELD
3802 uint32_t word5Rsvd:8;
3803 uint32_t remoteID:24;
3804#else /* __LITTLE_ENDIAN_BITFIELD */
3805 uint32_t remoteID:24;
3806 uint32_t word5Rsvd:8;
3807#endif
3808} GET_RPI;
3809
3810/* IOCB Command template for all FCP Initiator commands */
3811typedef struct {
3812 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3813 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3814 uint32_t fcpi_parm;
3815 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3816} FCPI_FIELDS;
3817
3818/* IOCB Command template for all FCP Target commands */
3819typedef struct {
3820 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3821 uint32_t fcpt_Offset;
3822 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3823} FCPT_FIELDS;
3824
3825/* SLI-2 IOCB structure definitions */
3826
3827/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3828typedef struct {
3829 ULP_BDL bdl;
3830 uint32_t xrsqRo; /* Starting Relative Offset */
3831 WORD5 w5; /* Header control/status word */
3832} XMT_SEQ_FIELDS64;
3833
3834/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3835#define xmit_els_remoteID xrsqRo
3836
3837/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3838typedef struct {
3839 struct ulp_bde64 rcvBde;
3840 uint32_t rsvd1;
3841 uint32_t xrsqRo; /* Starting Relative Offset */
3842 WORD5 w5; /* Header control/status word */
3843} RCV_SEQ_FIELDS64;
3844
3845/* IOCB Command template for ELS_REQUEST64 */
3846typedef struct {
3847 ULP_BDL bdl;
3848#ifdef __BIG_ENDIAN_BITFIELD
3849 uint32_t word4Rsvd:7;
3850 uint32_t fl:1;
3851 uint32_t myID:24;
3852 uint32_t word5Rsvd:8;
3853 uint32_t remoteID:24;
3854#else /* __LITTLE_ENDIAN_BITFIELD */
3855 uint32_t myID:24;
3856 uint32_t fl:1;
3857 uint32_t word4Rsvd:7;
3858 uint32_t remoteID:24;
3859 uint32_t word5Rsvd:8;
3860#endif
3861} ELS_REQUEST64;
3862
3863/* IOCB Command template for GEN_REQUEST64 */
3864typedef struct {
3865 ULP_BDL bdl;
3866 uint32_t xrsqRo; /* Starting Relative Offset */
3867 WORD5 w5; /* Header control/status word */
3868} GEN_REQUEST64;
3869
3870/* IOCB Command template for RCV_ELS_REQ64 */
3871typedef struct {
3872 struct ulp_bde64 elsReq;
3873 uint32_t rcvd1;
3874 uint32_t parmRo;
3875
3876#ifdef __BIG_ENDIAN_BITFIELD
3877 uint32_t word5Rsvd:8;
3878 uint32_t remoteID:24;
3879#else /* __LITTLE_ENDIAN_BITFIELD */
3880 uint32_t remoteID:24;
3881 uint32_t word5Rsvd:8;
3882#endif
3883} RCV_ELS_REQ64;
3884
3885/* IOCB Command template for RCV_SEQ64 */
3886struct rcv_seq64 {
3887 struct ulp_bde64 elsReq;
3888 uint32_t hbq_1;
3889 uint32_t parmRo;
3890#ifdef __BIG_ENDIAN_BITFIELD
3891 uint32_t rctl:8;
3892 uint32_t type:8;
3893 uint32_t dfctl:8;
3894 uint32_t ls:1;
3895 uint32_t fs:1;
3896 uint32_t rsvd2:3;
3897 uint32_t si:1;
3898 uint32_t bc:1;
3899 uint32_t rsvd3:1;
3900#else /* __LITTLE_ENDIAN_BITFIELD */
3901 uint32_t rsvd3:1;
3902 uint32_t bc:1;
3903 uint32_t si:1;
3904 uint32_t rsvd2:3;
3905 uint32_t fs:1;
3906 uint32_t ls:1;
3907 uint32_t dfctl:8;
3908 uint32_t type:8;
3909 uint32_t rctl:8;
3910#endif
3911};
3912
3913/* IOCB Command template for all 64 bit FCP Initiator commands */
3914typedef struct {
3915 ULP_BDL bdl;
3916 uint32_t fcpi_parm;
3917 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3918} FCPI_FIELDS64;
3919
3920/* IOCB Command template for all 64 bit FCP Target commands */
3921typedef struct {
3922 ULP_BDL bdl;
3923 uint32_t fcpt_Offset;
3924 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3925} FCPT_FIELDS64;
3926
3927/* IOCB Command template for Async Status iocb commands */
3928typedef struct {
3929 uint32_t rsvd[4];
3930 uint32_t param;
3931#ifdef __BIG_ENDIAN_BITFIELD
3932 uint16_t evt_code; /* High order bits word 5 */
3933 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3934#else /* __LITTLE_ENDIAN_BITFIELD */
3935 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3936 uint16_t evt_code; /* Low order bits word 5 */
3937#endif
3938} ASYNCSTAT_FIELDS;
3939#define ASYNC_TEMP_WARN 0x100
3940#define ASYNC_TEMP_SAFE 0x101
3941#define ASYNC_STATUS_CN 0x102
3942
3943/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3944 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3945
3946struct rcv_sli3 {
3947#ifdef __BIG_ENDIAN_BITFIELD
3948 uint16_t ox_id;
3949 uint16_t seq_cnt;
3950
3951 uint16_t vpi;
3952 uint16_t word9Rsvd;
3953#else /* __LITTLE_ENDIAN */
3954 uint16_t seq_cnt;
3955 uint16_t ox_id;
3956
3957 uint16_t word9Rsvd;
3958 uint16_t vpi;
3959#endif
3960 uint32_t word10Rsvd;
3961 uint32_t acc_len; /* accumulated length */
3962 struct ulp_bde64 bde2;
3963};
3964
3965/* Structure used for a single HBQ entry */
3966struct lpfc_hbq_entry {
3967 struct ulp_bde64 bde;
3968 uint32_t buffer_tag;
3969};
3970
3971/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3972typedef struct {
3973 struct lpfc_hbq_entry buff;
3974 uint32_t rsvd;
3975 uint32_t rsvd1;
3976} QUE_XRI64_CX_FIELDS;
3977
3978struct que_xri64cx_ext_fields {
3979 uint32_t iotag64_low;
3980 uint32_t iotag64_high;
3981 uint32_t ebde_count;
3982 uint32_t rsvd;
3983 struct lpfc_hbq_entry buff[5];
3984};
3985
3986struct sli3_bg_fields {
3987 uint32_t filler[6]; /* word 8-13 in IOCB */
3988 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3989/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3990#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3991#define BGS_BIDIR_BG_PROF_SHIFT 24
3992#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3993#define BGS_BIDIR_ERR_COND_SHIFT 16
3994#define BGS_BG_PROFILE_MASK 0x0000ff00
3995#define BGS_BG_PROFILE_SHIFT 8
3996#define BGS_INVALID_PROF_MASK 0x00000020
3997#define BGS_INVALID_PROF_SHIFT 5
3998#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3999#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
4000#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
4001#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4002#define BGS_REFTAG_ERR_MASK 0x00000004
4003#define BGS_REFTAG_ERR_SHIFT 2
4004#define BGS_APPTAG_ERR_MASK 0x00000002
4005#define BGS_APPTAG_ERR_SHIFT 1
4006#define BGS_GUARD_ERR_MASK 0x00000001
4007#define BGS_GUARD_ERR_SHIFT 0
4008 uint32_t bgstat; /* word 15 - BlockGuard Status */
4009};
4010
4011static inline uint32_t
4012lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4013{
4014 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4015 BGS_BIDIR_BG_PROF_SHIFT;
4016}
4017
4018static inline uint32_t
4019lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4020{
4021 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4022 BGS_BIDIR_ERR_COND_SHIFT;
4023}
4024
4025static inline uint32_t
4026lpfc_bgs_get_bg_prof(uint32_t bgstat)
4027{
4028 return (bgstat & BGS_BG_PROFILE_MASK) >>
4029 BGS_BG_PROFILE_SHIFT;
4030}
4031
4032static inline uint32_t
4033lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4034{
4035 return (bgstat & BGS_INVALID_PROF_MASK) >>
4036 BGS_INVALID_PROF_SHIFT;
4037}
4038
4039static inline uint32_t
4040lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4041{
4042 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4043 BGS_UNINIT_DIF_BLOCK_SHIFT;
4044}
4045
4046static inline uint32_t
4047lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4048{
4049 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4050 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4051}
4052
4053static inline uint32_t
4054lpfc_bgs_get_reftag_err(uint32_t bgstat)
4055{
4056 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4057 BGS_REFTAG_ERR_SHIFT;
4058}
4059
4060static inline uint32_t
4061lpfc_bgs_get_apptag_err(uint32_t bgstat)
4062{
4063 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4064 BGS_APPTAG_ERR_SHIFT;
4065}
4066
4067static inline uint32_t
4068lpfc_bgs_get_guard_err(uint32_t bgstat)
4069{
4070 return (bgstat & BGS_GUARD_ERR_MASK) >>
4071 BGS_GUARD_ERR_SHIFT;
4072}
4073
4074#define LPFC_EXT_DATA_BDE_COUNT 3
4075struct fcp_irw_ext {
4076 uint32_t io_tag64_low;
4077 uint32_t io_tag64_high;
4078#ifdef __BIG_ENDIAN_BITFIELD
4079 uint8_t reserved1;
4080 uint8_t reserved2;
4081 uint8_t reserved3;
4082 uint8_t ebde_count;
4083#else /* __LITTLE_ENDIAN */
4084 uint8_t ebde_count;
4085 uint8_t reserved3;
4086 uint8_t reserved2;
4087 uint8_t reserved1;
4088#endif
4089 uint32_t reserved4;
4090 struct ulp_bde64 rbde; /* response bde */
4091 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4092 uint8_t icd[32]; /* immediate command data (32 bytes) */
4093};
4094
4095typedef struct _IOCB { /* IOCB structure */
4096 union {
4097 GENERIC_RSP grsp; /* Generic response */
4098 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4099 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4100 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4101 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4102 A_MXRI64 amxri; /* abort multiple xri command overlay */
4103 GET_RPI getrpi; /* GET_RPI template */
4104 FCPI_FIELDS fcpi; /* FCP Initiator template */
4105 FCPT_FIELDS fcpt; /* FCP target template */
4106
4107 /* SLI-2 structures */
4108
4109 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4110 * bde_64s */
4111 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4112 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4113 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4114 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4115 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4116 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4117 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4118 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4119 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4120 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4121 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4122 } un;
4123 union {
4124 struct {
4125#ifdef __BIG_ENDIAN_BITFIELD
4126 uint16_t ulpContext; /* High order bits word 6 */
4127 uint16_t ulpIoTag; /* Low order bits word 6 */
4128#else /* __LITTLE_ENDIAN_BITFIELD */
4129 uint16_t ulpIoTag; /* Low order bits word 6 */
4130 uint16_t ulpContext; /* High order bits word 6 */
4131#endif
4132 } t1;
4133 struct {
4134#ifdef __BIG_ENDIAN_BITFIELD
4135 uint16_t ulpContext; /* High order bits word 6 */
4136 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4137 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4138#else /* __LITTLE_ENDIAN_BITFIELD */
4139 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4140 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4141 uint16_t ulpContext; /* High order bits word 6 */
4142#endif
4143 } t2;
4144 } un1;
4145#define ulpContext un1.t1.ulpContext
4146#define ulpIoTag un1.t1.ulpIoTag
4147#define ulpIoTag0 un1.t2.ulpIoTag0
4148
4149#ifdef __BIG_ENDIAN_BITFIELD
4150 uint32_t ulpTimeout:8;
4151 uint32_t ulpXS:1;
4152 uint32_t ulpFCP2Rcvy:1;
4153 uint32_t ulpPU:2;
4154 uint32_t ulpIr:1;
4155 uint32_t ulpClass:3;
4156 uint32_t ulpCommand:8;
4157 uint32_t ulpStatus:4;
4158 uint32_t ulpBdeCount:2;
4159 uint32_t ulpLe:1;
4160 uint32_t ulpOwner:1; /* Low order bit word 7 */
4161#else /* __LITTLE_ENDIAN_BITFIELD */
4162 uint32_t ulpOwner:1; /* Low order bit word 7 */
4163 uint32_t ulpLe:1;
4164 uint32_t ulpBdeCount:2;
4165 uint32_t ulpStatus:4;
4166 uint32_t ulpCommand:8;
4167 uint32_t ulpClass:3;
4168 uint32_t ulpIr:1;
4169 uint32_t ulpPU:2;
4170 uint32_t ulpFCP2Rcvy:1;
4171 uint32_t ulpXS:1;
4172 uint32_t ulpTimeout:8;
4173#endif
4174
4175 union {
4176 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4177
4178 /* words 8-31 used for que_xri_cx iocb */
4179 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4180 struct fcp_irw_ext fcp_ext;
4181 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4182
4183 /* words 8-15 for BlockGuard */
4184 struct sli3_bg_fields sli3_bg;
4185 } unsli3;
4186
4187#define ulpCt_h ulpXS
4188#define ulpCt_l ulpFCP2Rcvy
4189
4190#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4191#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4192#define PARM_UNUSED 0 /* PU field (Word 4) not used */
4193#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4194#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4195#define PARM_NPIV_DID 3
4196#define CLASS1 0 /* Class 1 */
4197#define CLASS2 1 /* Class 2 */
4198#define CLASS3 2 /* Class 3 */
4199#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4200
4201#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4202#define IOSTAT_FCP_RSP_ERROR 0x1
4203#define IOSTAT_REMOTE_STOP 0x2
4204#define IOSTAT_LOCAL_REJECT 0x3
4205#define IOSTAT_NPORT_RJT 0x4
4206#define IOSTAT_FABRIC_RJT 0x5
4207#define IOSTAT_NPORT_BSY 0x6
4208#define IOSTAT_FABRIC_BSY 0x7
4209#define IOSTAT_INTERMED_RSP 0x8
4210#define IOSTAT_LS_RJT 0x9
4211#define IOSTAT_BA_RJT 0xA
4212#define IOSTAT_RSVD1 0xB
4213#define IOSTAT_RSVD2 0xC
4214#define IOSTAT_RSVD3 0xD
4215#define IOSTAT_RSVD4 0xE
4216#define IOSTAT_NEED_BUFFER 0xF
4217#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4218#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4219#define IOSTAT_CNT 0x11
4220
4221} IOCB_t;
4222
4223
4224#define SLI1_SLIM_SIZE (4 * 1024)
4225
4226/* Up to 498 IOCBs will fit into 16k
4227 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4228 */
4229#define SLI2_SLIM_SIZE (64 * 1024)
4230
4231/* Maximum IOCBs that will fit in SLI2 slim */
4232#define MAX_SLI2_IOCB 498
4233#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4234 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4235 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4236
4237/* HBQ entries are 4 words each = 4k */
4238#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4239 lpfc_sli_hbq_count())
4240
4241struct lpfc_sli2_slim {
4242 MAILBOX_t mbx;
4243 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4244 PCB_t pcb;
4245 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4246};
4247
4248/*
4249 * This function checks PCI device to allow special handling for LC HBAs.
4250 *
4251 * Parameters:
4252 * device : struct pci_dev 's device field
4253 *
4254 * return 1 => TRUE
4255 * 0 => FALSE
4256 */
4257static inline int
4258lpfc_is_LC_HBA(unsigned short device)
4259{
4260 if ((device == PCI_DEVICE_ID_TFLY) ||
4261 (device == PCI_DEVICE_ID_PFLY) ||
4262 (device == PCI_DEVICE_ID_LP101) ||
4263 (device == PCI_DEVICE_ID_BMID) ||
4264 (device == PCI_DEVICE_ID_BSMB) ||
4265 (device == PCI_DEVICE_ID_ZMID) ||
4266 (device == PCI_DEVICE_ID_ZSMB) ||
4267 (device == PCI_DEVICE_ID_SAT_MID) ||
4268 (device == PCI_DEVICE_ID_SAT_SMB) ||
4269 (device == PCI_DEVICE_ID_RFLY))
4270 return 1;
4271 else
4272 return 0;
4273}
4274
4275/*
4276 * Determine if an IOCB failed because of a link event or firmware reset.
4277 */
4278
4279static inline int
4280lpfc_error_lost_link(IOCB_t *iocbp)
4281{
4282 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4283 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4284 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4285 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4286}
4287
4288#define MENLO_TRANSPORT_TYPE 0xfe
4289#define MENLO_CONTEXT 0
4290#define MENLO_PU 3
4291#define MENLO_TIMEOUT 30
4292#define SETVAR_MLOMNT 0x103107
4293#define SETVAR_MLORST 0x103007
4294
4295#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */