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1Mediatek infracfg controller
2============================
3
4The Mediatek infracfg controller provides various clocks and reset
5outputs to the system.
6
7Required Properties:
8
9- compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
15 - "mediatek,mt7629-infracfg", "syscon"
16 - "mediatek,mt8135-infracfg", "syscon"
17 - "mediatek,mt8173-infracfg", "syscon"
18 - "mediatek,mt8183-infracfg", "syscon"
19 - "mediatek,mt8516-infracfg", "syscon"
20- #clock-cells: Must be 1
21- #reset-cells: Must be 1
22
23The infracfg controller uses the common clk binding from
24Documentation/devicetree/bindings/clock/clock-bindings.txt
25The available clocks are defined in dt-bindings/clock/mt*-clk.h.
26Also it uses the common reset controller binding from
27Documentation/devicetree/bindings/reset/reset.txt.
28The available reset outputs are defined in
29dt-bindings/reset/mt*-resets.h
30
31Example:
32
33infracfg: power-controller@10001000 {
34 compatible = "mediatek,mt8173-infracfg", "syscon";
35 reg = <0 0x10001000 0 0x1000>;
36 #clock-cells = <1>;
37 #reset-cells = <1>;
38};