tjh.dev
Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2018 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#define ZYNQMP_PM_VERSION_MAJOR 1
17#define ZYNQMP_PM_VERSION_MINOR 0
18
19#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22#define ZYNQMP_TZ_VERSION_MAJOR 1
23#define ZYNQMP_TZ_VERSION_MINOR 0
24
25#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28/* SMC SIP service Call Function Identifier Prefix */
29#define PM_SIP_SVC 0xC2000000
30#define PM_GET_TRUSTZONE_VERSION 0xa03
31#define PM_SET_SUSPEND_MODE 0xa02
32#define GET_CALLBACK_DATA 0xa01
33
34/* Number of 32bits values in payload */
35#define PAYLOAD_ARG_CNT 4U
36
37/* Number of arguments for a callback */
38#define CB_ARG_CNT 4
39
40/* Payload size (consists of callback API ID + arguments) */
41#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
42
43#define ZYNQMP_PM_MAX_QOS 100U
44
45/* Node capabilities */
46#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
47#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
48#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49#define ZYNQMP_PM_CAPABILITY_POWER 0x8U
50
51/*
52 * Firmware FPGA Manager flags
53 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
54 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
55 */
56#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
57#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
58
59enum pm_api_id {
60 PM_GET_API_VERSION = 1,
61 PM_REQUEST_NODE = 13,
62 PM_RELEASE_NODE,
63 PM_SET_REQUIREMENT,
64 PM_RESET_ASSERT = 17,
65 PM_RESET_GET_STATUS,
66 PM_PM_INIT_FINALIZE = 21,
67 PM_FPGA_LOAD,
68 PM_FPGA_GET_STATUS,
69 PM_GET_CHIPID = 24,
70 PM_IOCTL = 34,
71 PM_QUERY_DATA,
72 PM_CLOCK_ENABLE,
73 PM_CLOCK_DISABLE,
74 PM_CLOCK_GETSTATE,
75 PM_CLOCK_SETDIVIDER,
76 PM_CLOCK_GETDIVIDER,
77 PM_CLOCK_SETRATE,
78 PM_CLOCK_GETRATE,
79 PM_CLOCK_SETPARENT,
80 PM_CLOCK_GETPARENT,
81};
82
83/* PMU-FW return status codes */
84enum pm_ret_status {
85 XST_PM_SUCCESS = 0,
86 XST_PM_INTERNAL = 2000,
87 XST_PM_CONFLICT,
88 XST_PM_NO_ACCESS,
89 XST_PM_INVALID_NODE,
90 XST_PM_DOUBLE_REQ,
91 XST_PM_ABORT_SUSPEND,
92};
93
94enum pm_ioctl_id {
95 IOCTL_SET_PLL_FRAC_MODE = 8,
96 IOCTL_GET_PLL_FRAC_MODE,
97 IOCTL_SET_PLL_FRAC_DATA,
98 IOCTL_GET_PLL_FRAC_DATA,
99};
100
101enum pm_query_id {
102 PM_QID_INVALID,
103 PM_QID_CLOCK_GET_NAME,
104 PM_QID_CLOCK_GET_TOPOLOGY,
105 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
106 PM_QID_CLOCK_GET_PARENTS,
107 PM_QID_CLOCK_GET_ATTRIBUTES,
108 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
109};
110
111enum zynqmp_pm_reset_action {
112 PM_RESET_ACTION_RELEASE,
113 PM_RESET_ACTION_ASSERT,
114 PM_RESET_ACTION_PULSE,
115};
116
117enum zynqmp_pm_reset {
118 ZYNQMP_PM_RESET_START = 1000,
119 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
120 ZYNQMP_PM_RESET_PCIE_BRIDGE,
121 ZYNQMP_PM_RESET_PCIE_CTRL,
122 ZYNQMP_PM_RESET_DP,
123 ZYNQMP_PM_RESET_SWDT_CRF,
124 ZYNQMP_PM_RESET_AFI_FM5,
125 ZYNQMP_PM_RESET_AFI_FM4,
126 ZYNQMP_PM_RESET_AFI_FM3,
127 ZYNQMP_PM_RESET_AFI_FM2,
128 ZYNQMP_PM_RESET_AFI_FM1,
129 ZYNQMP_PM_RESET_AFI_FM0,
130 ZYNQMP_PM_RESET_GDMA,
131 ZYNQMP_PM_RESET_GPU_PP1,
132 ZYNQMP_PM_RESET_GPU_PP0,
133 ZYNQMP_PM_RESET_GPU,
134 ZYNQMP_PM_RESET_GT,
135 ZYNQMP_PM_RESET_SATA,
136 ZYNQMP_PM_RESET_ACPU3_PWRON,
137 ZYNQMP_PM_RESET_ACPU2_PWRON,
138 ZYNQMP_PM_RESET_ACPU1_PWRON,
139 ZYNQMP_PM_RESET_ACPU0_PWRON,
140 ZYNQMP_PM_RESET_APU_L2,
141 ZYNQMP_PM_RESET_ACPU3,
142 ZYNQMP_PM_RESET_ACPU2,
143 ZYNQMP_PM_RESET_ACPU1,
144 ZYNQMP_PM_RESET_ACPU0,
145 ZYNQMP_PM_RESET_DDR,
146 ZYNQMP_PM_RESET_APM_FPD,
147 ZYNQMP_PM_RESET_SOFT,
148 ZYNQMP_PM_RESET_GEM0,
149 ZYNQMP_PM_RESET_GEM1,
150 ZYNQMP_PM_RESET_GEM2,
151 ZYNQMP_PM_RESET_GEM3,
152 ZYNQMP_PM_RESET_QSPI,
153 ZYNQMP_PM_RESET_UART0,
154 ZYNQMP_PM_RESET_UART1,
155 ZYNQMP_PM_RESET_SPI0,
156 ZYNQMP_PM_RESET_SPI1,
157 ZYNQMP_PM_RESET_SDIO0,
158 ZYNQMP_PM_RESET_SDIO1,
159 ZYNQMP_PM_RESET_CAN0,
160 ZYNQMP_PM_RESET_CAN1,
161 ZYNQMP_PM_RESET_I2C0,
162 ZYNQMP_PM_RESET_I2C1,
163 ZYNQMP_PM_RESET_TTC0,
164 ZYNQMP_PM_RESET_TTC1,
165 ZYNQMP_PM_RESET_TTC2,
166 ZYNQMP_PM_RESET_TTC3,
167 ZYNQMP_PM_RESET_SWDT_CRL,
168 ZYNQMP_PM_RESET_NAND,
169 ZYNQMP_PM_RESET_ADMA,
170 ZYNQMP_PM_RESET_GPIO,
171 ZYNQMP_PM_RESET_IOU_CC,
172 ZYNQMP_PM_RESET_TIMESTAMP,
173 ZYNQMP_PM_RESET_RPU_R50,
174 ZYNQMP_PM_RESET_RPU_R51,
175 ZYNQMP_PM_RESET_RPU_AMBA,
176 ZYNQMP_PM_RESET_OCM,
177 ZYNQMP_PM_RESET_RPU_PGE,
178 ZYNQMP_PM_RESET_USB0_CORERESET,
179 ZYNQMP_PM_RESET_USB1_CORERESET,
180 ZYNQMP_PM_RESET_USB0_HIBERRESET,
181 ZYNQMP_PM_RESET_USB1_HIBERRESET,
182 ZYNQMP_PM_RESET_USB0_APB,
183 ZYNQMP_PM_RESET_USB1_APB,
184 ZYNQMP_PM_RESET_IPI,
185 ZYNQMP_PM_RESET_APM_LPD,
186 ZYNQMP_PM_RESET_RTC,
187 ZYNQMP_PM_RESET_SYSMON,
188 ZYNQMP_PM_RESET_AFI_FM6,
189 ZYNQMP_PM_RESET_LPD_SWDT,
190 ZYNQMP_PM_RESET_FPD,
191 ZYNQMP_PM_RESET_RPU_DBG1,
192 ZYNQMP_PM_RESET_RPU_DBG0,
193 ZYNQMP_PM_RESET_DBG_LPD,
194 ZYNQMP_PM_RESET_DBG_FPD,
195 ZYNQMP_PM_RESET_APLL,
196 ZYNQMP_PM_RESET_DPLL,
197 ZYNQMP_PM_RESET_VPLL,
198 ZYNQMP_PM_RESET_IOPLL,
199 ZYNQMP_PM_RESET_RPLL,
200 ZYNQMP_PM_RESET_GPO3_PL_0,
201 ZYNQMP_PM_RESET_GPO3_PL_1,
202 ZYNQMP_PM_RESET_GPO3_PL_2,
203 ZYNQMP_PM_RESET_GPO3_PL_3,
204 ZYNQMP_PM_RESET_GPO3_PL_4,
205 ZYNQMP_PM_RESET_GPO3_PL_5,
206 ZYNQMP_PM_RESET_GPO3_PL_6,
207 ZYNQMP_PM_RESET_GPO3_PL_7,
208 ZYNQMP_PM_RESET_GPO3_PL_8,
209 ZYNQMP_PM_RESET_GPO3_PL_9,
210 ZYNQMP_PM_RESET_GPO3_PL_10,
211 ZYNQMP_PM_RESET_GPO3_PL_11,
212 ZYNQMP_PM_RESET_GPO3_PL_12,
213 ZYNQMP_PM_RESET_GPO3_PL_13,
214 ZYNQMP_PM_RESET_GPO3_PL_14,
215 ZYNQMP_PM_RESET_GPO3_PL_15,
216 ZYNQMP_PM_RESET_GPO3_PL_16,
217 ZYNQMP_PM_RESET_GPO3_PL_17,
218 ZYNQMP_PM_RESET_GPO3_PL_18,
219 ZYNQMP_PM_RESET_GPO3_PL_19,
220 ZYNQMP_PM_RESET_GPO3_PL_20,
221 ZYNQMP_PM_RESET_GPO3_PL_21,
222 ZYNQMP_PM_RESET_GPO3_PL_22,
223 ZYNQMP_PM_RESET_GPO3_PL_23,
224 ZYNQMP_PM_RESET_GPO3_PL_24,
225 ZYNQMP_PM_RESET_GPO3_PL_25,
226 ZYNQMP_PM_RESET_GPO3_PL_26,
227 ZYNQMP_PM_RESET_GPO3_PL_27,
228 ZYNQMP_PM_RESET_GPO3_PL_28,
229 ZYNQMP_PM_RESET_GPO3_PL_29,
230 ZYNQMP_PM_RESET_GPO3_PL_30,
231 ZYNQMP_PM_RESET_GPO3_PL_31,
232 ZYNQMP_PM_RESET_RPU_LS,
233 ZYNQMP_PM_RESET_PS_ONLY,
234 ZYNQMP_PM_RESET_PL,
235 ZYNQMP_PM_RESET_PS_PL0,
236 ZYNQMP_PM_RESET_PS_PL1,
237 ZYNQMP_PM_RESET_PS_PL2,
238 ZYNQMP_PM_RESET_PS_PL3,
239 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
240};
241
242enum zynqmp_pm_suspend_reason {
243 SUSPEND_POWER_REQUEST = 201,
244 SUSPEND_ALERT,
245 SUSPEND_SYSTEM_SHUTDOWN,
246};
247
248enum zynqmp_pm_request_ack {
249 ZYNQMP_PM_REQUEST_ACK_NO = 1,
250 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
251 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
252};
253
254/**
255 * struct zynqmp_pm_query_data - PM query data
256 * @qid: query ID
257 * @arg1: Argument 1 of query data
258 * @arg2: Argument 2 of query data
259 * @arg3: Argument 3 of query data
260 */
261struct zynqmp_pm_query_data {
262 u32 qid;
263 u32 arg1;
264 u32 arg2;
265 u32 arg3;
266};
267
268struct zynqmp_eemi_ops {
269 int (*get_api_version)(u32 *version);
270 int (*get_chipid)(u32 *idcode, u32 *version);
271 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
272 int (*fpga_get_status)(u32 *value);
273 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
274 int (*clock_enable)(u32 clock_id);
275 int (*clock_disable)(u32 clock_id);
276 int (*clock_getstate)(u32 clock_id, u32 *state);
277 int (*clock_setdivider)(u32 clock_id, u32 divider);
278 int (*clock_getdivider)(u32 clock_id, u32 *divider);
279 int (*clock_setrate)(u32 clock_id, u64 rate);
280 int (*clock_getrate)(u32 clock_id, u64 *rate);
281 int (*clock_setparent)(u32 clock_id, u32 parent_id);
282 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
283 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
284 int (*reset_assert)(const enum zynqmp_pm_reset reset,
285 const enum zynqmp_pm_reset_action assert_flag);
286 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
287 int (*init_finalize)(void);
288 int (*set_suspend_mode)(u32 mode);
289 int (*request_node)(const u32 node,
290 const u32 capabilities,
291 const u32 qos,
292 const enum zynqmp_pm_request_ack ack);
293 int (*release_node)(const u32 node);
294 int (*set_requirement)(const u32 node,
295 const u32 capabilities,
296 const u32 qos,
297 const enum zynqmp_pm_request_ack ack);
298};
299
300int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
301 u32 arg2, u32 arg3, u32 *ret_payload);
302
303#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
304const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
305#else
306static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
307{
308 return ERR_PTR(-ENODEV);
309}
310#endif
311
312#endif /* __FIRMWARE_ZYNQMP_H__ */