tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/init.h>
17
18#include <linux/io.h>
19#include <asm/pci-bridge.h>
20
21static int
22indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
23 int len, u32 *val)
24{
25 struct pci_controller *hose = pci_bus_to_host(bus);
26 volatile void __iomem *cfg_data;
27 u8 cfg_type = 0;
28 u32 bus_no, reg;
29
30 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
31 if (bus->number != hose->first_busno)
32 return PCIBIOS_DEVICE_NOT_FOUND;
33 if (devfn != 0)
34 return PCIBIOS_DEVICE_NOT_FOUND;
35 }
36
37 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
38 if (bus->number != hose->first_busno)
39 cfg_type = 1;
40
41 bus_no = (bus->number == hose->first_busno) ?
42 hose->self_busno : bus->number;
43
44 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
45 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
46 else
47 reg = offset & 0xfc; /* Only 3 bits for function */
48
49 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
50 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
51 (devfn << 8) | reg | cfg_type));
52 else
53 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
54 (devfn << 8) | reg | cfg_type));
55
56 /*
57 * Note: the caller has already checked that offset is
58 * suitably aligned and that len is 1, 2 or 4.
59 */
60 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
61 switch (len) {
62 case 1:
63 *val = in_8(cfg_data);
64 break;
65 case 2:
66 *val = in_le16(cfg_data);
67 break;
68 default:
69 *val = in_le32(cfg_data);
70 break;
71 }
72 return PCIBIOS_SUCCESSFUL;
73}
74
75static int
76indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
77 int len, u32 val)
78{
79 struct pci_controller *hose = pci_bus_to_host(bus);
80 volatile void __iomem *cfg_data;
81 u8 cfg_type = 0;
82 u32 bus_no, reg;
83
84 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
85 if (bus->number != hose->first_busno)
86 return PCIBIOS_DEVICE_NOT_FOUND;
87 if (devfn != 0)
88 return PCIBIOS_DEVICE_NOT_FOUND;
89 }
90
91 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
92 if (bus->number != hose->first_busno)
93 cfg_type = 1;
94
95 bus_no = (bus->number == hose->first_busno) ?
96 hose->self_busno : bus->number;
97
98 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
99 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
100 else
101 reg = offset & 0xfc;
102
103 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
104 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
105 (devfn << 8) | reg | cfg_type));
106 else
107 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
108 (devfn << 8) | reg | cfg_type));
109
110 /* suppress setting of PCI_PRIMARY_BUS */
111 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
112 if ((offset == PCI_PRIMARY_BUS) &&
113 (bus->number == hose->first_busno))
114 val &= 0xffffff00;
115
116 /* Workaround for PCI_28 Errata in 440EPx/GRx */
117 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
118 offset == PCI_CACHE_LINE_SIZE) {
119 val = 0;
120 }
121
122 /*
123 * Note: the caller has already checked that offset is
124 * suitably aligned and that len is 1, 2 or 4.
125 */
126 cfg_data = hose->cfg_data + (offset & 3);
127 switch (len) {
128 case 1:
129 out_8(cfg_data, val);
130 break;
131 case 2:
132 out_le16(cfg_data, val);
133 break;
134 default:
135 out_le32(cfg_data, val);
136 break;
137 }
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142static struct pci_ops indirect_pci_ops = {
143 .read = indirect_read_config,
144 .write = indirect_write_config,
145};
146
147void __init
148setup_indirect_pci(struct pci_controller *hose,
149 resource_size_t cfg_addr,
150 resource_size_t cfg_data, u32 flags)
151{
152 resource_size_t base = cfg_addr & PAGE_MASK;
153 void __iomem *mbase;
154
155 mbase = ioremap(base, PAGE_SIZE);
156 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
157 if ((cfg_data & PAGE_MASK) != base)
158 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
159 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
160 hose->ops = &indirect_pci_ops;
161 hose->indirect_type = flags;
162}