tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A7796 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */
13
14#include <linux/errno.h>
15#include <linux/kernel.h>
16
17#include "core.h"
18#include "sh_pfc.h"
19
20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
23
24#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37/*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
41
42/* GPSR0 */
43#define GPSR0_15 F_(D15, IP7_11_8)
44#define GPSR0_14 F_(D14, IP7_7_4)
45#define GPSR0_13 F_(D13, IP7_3_0)
46#define GPSR0_12 F_(D12, IP6_31_28)
47#define GPSR0_11 F_(D11, IP6_27_24)
48#define GPSR0_10 F_(D10, IP6_23_20)
49#define GPSR0_9 F_(D9, IP6_19_16)
50#define GPSR0_8 F_(D8, IP6_15_12)
51#define GPSR0_7 F_(D7, IP6_11_8)
52#define GPSR0_6 F_(D6, IP6_7_4)
53#define GPSR0_5 F_(D5, IP6_3_0)
54#define GPSR0_4 F_(D4, IP5_31_28)
55#define GPSR0_3 F_(D3, IP5_27_24)
56#define GPSR0_2 F_(D2, IP5_23_20)
57#define GPSR0_1 F_(D1, IP5_19_16)
58#define GPSR0_0 F_(D0, IP5_15_12)
59
60/* GPSR1 */
61#define GPSR1_28 FM(CLKOUT)
62#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63#define GPSR1_26 F_(WE1_N, IP5_7_4)
64#define GPSR1_25 F_(WE0_N, IP5_3_0)
65#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66#define GPSR1_23 F_(RD_N, IP4_27_24)
67#define GPSR1_22 F_(BS_N, IP4_23_20)
68#define GPSR1_21 F_(CS1_N, IP4_19_16)
69#define GPSR1_20 F_(CS0_N, IP4_15_12)
70#define GPSR1_19 F_(A19, IP4_11_8)
71#define GPSR1_18 F_(A18, IP4_7_4)
72#define GPSR1_17 F_(A17, IP4_3_0)
73#define GPSR1_16 F_(A16, IP3_31_28)
74#define GPSR1_15 F_(A15, IP3_27_24)
75#define GPSR1_14 F_(A14, IP3_23_20)
76#define GPSR1_13 F_(A13, IP3_19_16)
77#define GPSR1_12 F_(A12, IP3_15_12)
78#define GPSR1_11 F_(A11, IP3_11_8)
79#define GPSR1_10 F_(A10, IP3_7_4)
80#define GPSR1_9 F_(A9, IP3_3_0)
81#define GPSR1_8 F_(A8, IP2_31_28)
82#define GPSR1_7 F_(A7, IP2_27_24)
83#define GPSR1_6 F_(A6, IP2_23_20)
84#define GPSR1_5 F_(A5, IP2_19_16)
85#define GPSR1_4 F_(A4, IP2_15_12)
86#define GPSR1_3 F_(A3, IP2_11_8)
87#define GPSR1_2 F_(A2, IP2_7_4)
88#define GPSR1_1 F_(A1, IP2_3_0)
89#define GPSR1_0 F_(A0, IP1_31_28)
90
91/* GPSR2 */
92#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98#define GPSR2_8 F_(PWM2_A, IP1_27_24)
99#define GPSR2_7 F_(PWM1_A, IP1_23_20)
100#define GPSR2_6 F_(PWM0, IP1_19_16)
101#define GPSR2_5 F_(IRQ5, IP1_15_12)
102#define GPSR2_4 F_(IRQ4, IP1_11_8)
103#define GPSR2_3 F_(IRQ3, IP1_7_4)
104#define GPSR2_2 F_(IRQ2, IP1_3_0)
105#define GPSR2_1 F_(IRQ1, IP0_31_28)
106#define GPSR2_0 F_(IRQ0, IP0_27_24)
107
108/* GPSR3 */
109#define GPSR3_15 F_(SD1_WP, IP11_23_20)
110#define GPSR3_14 F_(SD1_CD, IP11_19_16)
111#define GPSR3_13 F_(SD0_WP, IP11_15_12)
112#define GPSR3_12 F_(SD0_CD, IP11_11_8)
113#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125
126/* GPSR4 */
127#define GPSR4_17 F_(SD3_DS, IP11_7_4)
128#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138#define GPSR4_6 F_(SD2_DS, IP9_27_24)
139#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145
146/* GPSR5 */
147#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150#define GPSR5_22 FM(MSIOF0_RXD)
151#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152#define GPSR5_20 FM(MSIOF0_TXD)
153#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155#define GPSR5_17 FM(MSIOF0_SCK)
156#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158#define GPSR5_14 F_(HTX0, IP13_19_16)
159#define GPSR5_13 F_(HRX0, IP13_15_12)
160#define GPSR5_12 F_(HSCK0, IP13_11_8)
161#define GPSR5_11 F_(RX2_A, IP13_7_4)
162#define GPSR5_10 F_(TX2_A, IP13_3_0)
163#define GPSR5_9 F_(SCK2, IP12_31_28)
164#define GPSR5_8 F_(RTS1_N, IP12_27_24)
165#define GPSR5_7 F_(CTS1_N, IP12_23_20)
166#define GPSR5_6 F_(TX1_A, IP12_19_16)
167#define GPSR5_5 F_(RX1_A, IP12_15_12)
168#define GPSR5_4 F_(RTS0_N, IP12_11_8)
169#define GPSR5_3 F_(CTS0_N, IP12_7_4)
170#define GPSR5_2 F_(TX0, IP12_3_0)
171#define GPSR5_1 F_(RX0, IP11_31_28)
172#define GPSR5_0 F_(SCK0, IP11_27_24)
173
174/* GPSR6 */
175#define GPSR6_31 F_(GP6_31, IP18_7_4)
176#define GPSR6_30 F_(GP6_30, IP18_3_0)
177#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193#define GPSR6_13 FM(SSI_SDATA5)
194#define GPSR6_12 FM(SSI_WS5)
195#define GPSR6_11 FM(SSI_SCK5)
196#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207
208/* GPSR7 */
209#define GPSR7_3 FM(GP7_03)
210#define GPSR7_2 FM(GP7_02)
211#define GPSR7_1 FM(AVS2)
212#define GPSR7_0 FM(AVS1)
213
214
215/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243
244/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340
341/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369
370#define PINMUX_GPSR \
371\
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404
405#define PINMUX_IPSR \
406\
407FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415\
416FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424\
425FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433\
434FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442\
443FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
451
452/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
453#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
471
472/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
495
496/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
508#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510
511#define PINMUX_MOD_SELS \
512\
513MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516MOD_SEL0_28_27 MOD_SEL2_28_27 \
517MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519MOD_SEL0_23 MOD_SEL1_23_22_21 \
520MOD_SEL0_22 MOD_SEL2_22 \
521MOD_SEL0_21 MOD_SEL2_21 \
522MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530MOD_SEL0_12 MOD_SEL1_12 \
531MOD_SEL0_11 MOD_SEL1_11 \
532MOD_SEL0_10 MOD_SEL1_10 \
533MOD_SEL0_9_8 MOD_SEL1_9 \
534MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536MOD_SEL0_5 MOD_SEL1_5 \
537MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
542
543/*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547#define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559
560#define PINMUX_PHYS \
561 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
562
563enum {
564 PINMUX_RESERVED = 0,
565
566 PINMUX_DATA_BEGIN,
567 GP_ALL(DATA),
568 PINMUX_DATA_END,
569
570#define F_(x, y)
571#define FM(x) FN_##x,
572 PINMUX_FUNCTION_BEGIN,
573 GP_ALL(FN),
574 PINMUX_GPSR
575 PINMUX_IPSR
576 PINMUX_MOD_SELS
577 PINMUX_FUNCTION_END,
578#undef F_
579#undef FM
580
581#define F_(x, y)
582#define FM(x) x##_MARK,
583 PINMUX_MARK_BEGIN,
584 PINMUX_GPSR
585 PINMUX_IPSR
586 PINMUX_MOD_SELS
587 PINMUX_STATIC
588 PINMUX_PHYS
589 PINMUX_MARK_END,
590#undef F_
591#undef FM
592};
593
594static const u16 pinmux_data[] = {
595 PINMUX_DATA_GP_ALL(),
596
597 PINMUX_SINGLE(AVS1),
598 PINMUX_SINGLE(AVS2),
599 PINMUX_SINGLE(CLKOUT),
600 PINMUX_SINGLE(GP7_03),
601 PINMUX_SINGLE(GP7_02),
602 PINMUX_SINGLE(MSIOF0_RXD),
603 PINMUX_SINGLE(MSIOF0_SCK),
604 PINMUX_SINGLE(MSIOF0_TXD),
605 PINMUX_SINGLE(SSI_SCK5),
606 PINMUX_SINGLE(SSI_SDATA5),
607 PINMUX_SINGLE(SSI_WS5),
608
609 /* IPSR0 */
610 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
611 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
612
613 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
614 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
615 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
616
617 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
618 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
619 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
620
621 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
622 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
623 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
624
625 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
626 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
627 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
628 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
629
630 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
631 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
632 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
633 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
634
635 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
636 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
637 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
638 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
641 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
642
643 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
644 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
645 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
646 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
648 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
649 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
650
651 /* IPSR1 */
652 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
653 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
654 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
655 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
657 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
658
659 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
660 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
661 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
662 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
663 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
664 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
665
666 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
667 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
668 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
669 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
670 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
671 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
672
673 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
674 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
675 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
676 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
678 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
679
680 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
681 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
682 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
684
685 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
686 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
687 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
688 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
689 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
690
691 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
692 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
693 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
694 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
695
696 PINMUX_IPSR_GPSR(IP1_31_28, A0),
697 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
698 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
700 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
701 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
702
703 /* IPSR2 */
704 PINMUX_IPSR_GPSR(IP2_3_0, A1),
705 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
706 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
707 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
708 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
709 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
710
711 PINMUX_IPSR_GPSR(IP2_7_4, A2),
712 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
713 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
714 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
715 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
716 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
717
718 PINMUX_IPSR_GPSR(IP2_11_8, A3),
719 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
720 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
721 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
722 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
723 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
724
725 PINMUX_IPSR_GPSR(IP2_15_12, A4),
726 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
727 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
730 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
731
732 PINMUX_IPSR_GPSR(IP2_19_16, A5),
733 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
734 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
735 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
738 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
739
740 PINMUX_IPSR_GPSR(IP2_23_20, A6),
741 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
742 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
743 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
746 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
747
748 PINMUX_IPSR_GPSR(IP2_27_24, A7),
749 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
750 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
751 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
754 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
755
756 PINMUX_IPSR_GPSR(IP2_31_28, A8),
757 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
758 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
760 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
761 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
762 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
763
764 /* IPSR3 */
765 PINMUX_IPSR_GPSR(IP3_3_0, A9),
766 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
767 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
768 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
769
770 PINMUX_IPSR_GPSR(IP3_7_4, A10),
771 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
774
775 PINMUX_IPSR_GPSR(IP3_11_8, A11),
776 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
778 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
779 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
780 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
781 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
782 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
783 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
784
785 PINMUX_IPSR_GPSR(IP3_15_12, A12),
786 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
787 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
788 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
789 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
790 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
791
792 PINMUX_IPSR_GPSR(IP3_19_16, A13),
793 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
794 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
795 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
796 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
797 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
798
799 PINMUX_IPSR_GPSR(IP3_23_20, A14),
800 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
801 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
802 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
803 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
804 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
805
806 PINMUX_IPSR_GPSR(IP3_27_24, A15),
807 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
808 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
809 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
810 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
811 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
812
813 PINMUX_IPSR_GPSR(IP3_31_28, A16),
814 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
815 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
816 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
817
818 /* IPSR4 */
819 PINMUX_IPSR_GPSR(IP4_3_0, A17),
820 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
821 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
822 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
823
824 PINMUX_IPSR_GPSR(IP4_7_4, A18),
825 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
826 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
827 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
828
829 PINMUX_IPSR_GPSR(IP4_11_8, A19),
830 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
831 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
832 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
833
834 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
835 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
836
837 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
838 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
839 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
840
841 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
842 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
843 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
846 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
847 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
848 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
849
850 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
851 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
852 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
855 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
856
857 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
858 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
859 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
862 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
863
864 /* IPSR5 */
865 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
866 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
867 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
868 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
869 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
870 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
871 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
872
873 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
874 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
875 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
876 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
877 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
878 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
879 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
880 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
881
882 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
883 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
885 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
886
887 PINMUX_IPSR_GPSR(IP5_15_12, D0),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
891 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
892
893 PINMUX_IPSR_GPSR(IP5_19_16, D1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
895 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
897 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
898
899 PINMUX_IPSR_GPSR(IP5_23_20, D2),
900 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
902 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
903
904 PINMUX_IPSR_GPSR(IP5_27_24, D3),
905 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
907 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
908
909 PINMUX_IPSR_GPSR(IP5_31_28, D4),
910 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
912 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
913
914 /* IPSR6 */
915 PINMUX_IPSR_GPSR(IP6_3_0, D5),
916 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
918 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
919
920 PINMUX_IPSR_GPSR(IP6_7_4, D6),
921 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
923 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
924
925 PINMUX_IPSR_GPSR(IP6_11_8, D7),
926 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
928 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
929
930 PINMUX_IPSR_GPSR(IP6_15_12, D8),
931 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
932 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
933 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
934 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
936
937 PINMUX_IPSR_GPSR(IP6_19_16, D9),
938 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
939 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
941 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
942
943 PINMUX_IPSR_GPSR(IP6_23_20, D10),
944 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
945 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
946 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
947 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
948 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
949 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
950
951 PINMUX_IPSR_GPSR(IP6_27_24, D11),
952 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
953 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
954 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
955 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
956 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
957 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
958
959 PINMUX_IPSR_GPSR(IP6_31_28, D12),
960 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
961 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
962 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
963 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
965
966 /* IPSR7 */
967 PINMUX_IPSR_GPSR(IP7_3_0, D13),
968 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
969 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
970 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
971 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
972 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
973
974 PINMUX_IPSR_GPSR(IP7_7_4, D14),
975 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
976 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
977 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
978 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
980 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
981
982 PINMUX_IPSR_GPSR(IP7_11_8, D15),
983 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
984 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
985 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
986 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
987 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
988 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
989
990 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
991 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
993
994 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
995 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
996 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
997
998 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
999 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1000 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1001 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1002
1003 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1004 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1007
1008 /* IPSR8 */
1009 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1010 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1011 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1012 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1013
1014 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1015 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1016 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1017 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1020 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1021 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1022
1023 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1024 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1025 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1026 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1027 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1028
1029 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1030 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1031 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1032 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1033 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1035
1036 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1037 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1038 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1039 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1040 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1042
1043 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1044 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1045 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1047 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1049
1050 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1051 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1052 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1053 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1054 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1056
1057 /* IPSR9 */
1058 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1059 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1060
1061 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1062 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1063
1064 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1065 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1066
1067 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1068 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1069
1070 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1071 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1072
1073 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1074 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1075
1076 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1077 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1078
1079 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1080 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1081
1082 /* IPSR10 */
1083 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1084 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1085
1086 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1087 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1088
1089 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1090 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1091
1092 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1093 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1094
1095 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1096 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1097
1098 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1099 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1100 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1101
1102 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1103 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1104 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1105
1106 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1107 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1108 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1109
1110 /* IPSR11 */
1111 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1112 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1113 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1114
1115 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1116 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1117
1118 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1119 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1120 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1122
1123 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1124 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1126
1127 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1128 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1129 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1130 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1131
1132 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1133 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1134 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1135 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1136
1137 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1140 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1141 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1143 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1145 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1146 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1147
1148 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1149 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1153
1154 /* IPSR12 */
1155 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1156 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1157 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1158 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1159 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1160
1161 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1162 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1163 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1164 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1165 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1166 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1167 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1168 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1169
1170 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1171 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1172 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1173 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1174 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1175 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1176 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1177 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1178
1179 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1190
1191 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1192 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1198
1199 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1200 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1201 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1206
1207 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1209 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1210 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1212 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1213 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1214
1215 /* IPSR13 */
1216 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1222
1223 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1224 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1225 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1227 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1228 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1229
1230 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1231 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1233 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1234 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1237 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1238
1239 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1240 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1242 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1247 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1249 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1252
1253 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1254 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1255 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1256 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1257 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1258 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1260 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1263 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1264 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1265 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1266 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1267 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1268 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1269
1270 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1271 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1272 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1273 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1274
1275 /* IPSR14 */
1276 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1277 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1278 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1279 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1280 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1281 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1282 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1283 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1284
1285 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1286 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1287 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1288 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1289 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1290 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1291 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1292 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1293
1294 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1295 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1296 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1297
1298 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1299 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1300 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1301 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1302
1303 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1304 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1305 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1308 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1309
1310 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1311 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1312
1313 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1314 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1315
1316 /* IPSR15 */
1317 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1318
1319 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1320 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1321
1322 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1323 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1324 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1325
1326 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1327 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1332 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1340 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1348 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1354
1355 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1356 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1358 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1359 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1360 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1361 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1362
1363 /* IPSR16 */
1364 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1365 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1366
1367 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1368 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1369
1370 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1371 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1372
1373 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1374 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1375 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1376 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1380
1381 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1382 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1383 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1384 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1388
1389 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1390 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1391 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1392 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1396 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1397
1398 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1399 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1400 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1401 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1405
1406 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1408 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1409 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1410 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1411 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1412 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1413 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1414
1415 /* IPSR17 */
1416 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1417
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1423
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1429 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1431
1432 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1433 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1434 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1435 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1440 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1447 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1448
1449 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1450 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1452 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1453 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1458
1459 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1470
1471 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1472 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1473 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1474 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1480
1481 /* IPSR18 */
1482 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1491
1492 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1498 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1501
1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still need mark entries in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux the pin
1507 * while still applying configuration to it.
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
1512};
1513
1514/*
1515 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521#define PIN_NONE U16_MAX
1522
1523static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1525
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a7796
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576};
1577
1578/* - AUDIO CLOCK ------------------------------------------------------------ */
1579static const unsigned int audio_clk_a_a_pins[] = {
1580 /* CLK A */
1581 RCAR_GP_PIN(6, 22),
1582};
1583static const unsigned int audio_clk_a_a_mux[] = {
1584 AUDIO_CLKA_A_MARK,
1585};
1586static const unsigned int audio_clk_a_b_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(5, 4),
1589};
1590static const unsigned int audio_clk_a_b_mux[] = {
1591 AUDIO_CLKA_B_MARK,
1592};
1593static const unsigned int audio_clk_a_c_pins[] = {
1594 /* CLK A */
1595 RCAR_GP_PIN(5, 19),
1596};
1597static const unsigned int audio_clk_a_c_mux[] = {
1598 AUDIO_CLKA_C_MARK,
1599};
1600static const unsigned int audio_clk_b_a_pins[] = {
1601 /* CLK B */
1602 RCAR_GP_PIN(5, 12),
1603};
1604static const unsigned int audio_clk_b_a_mux[] = {
1605 AUDIO_CLKB_A_MARK,
1606};
1607static const unsigned int audio_clk_b_b_pins[] = {
1608 /* CLK B */
1609 RCAR_GP_PIN(6, 23),
1610};
1611static const unsigned int audio_clk_b_b_mux[] = {
1612 AUDIO_CLKB_B_MARK,
1613};
1614static const unsigned int audio_clk_c_a_pins[] = {
1615 /* CLK C */
1616 RCAR_GP_PIN(5, 21),
1617};
1618static const unsigned int audio_clk_c_a_mux[] = {
1619 AUDIO_CLKC_A_MARK,
1620};
1621static const unsigned int audio_clk_c_b_pins[] = {
1622 /* CLK C */
1623 RCAR_GP_PIN(5, 0),
1624};
1625static const unsigned int audio_clk_c_b_mux[] = {
1626 AUDIO_CLKC_B_MARK,
1627};
1628static const unsigned int audio_clkout_a_pins[] = {
1629 /* CLKOUT */
1630 RCAR_GP_PIN(5, 18),
1631};
1632static const unsigned int audio_clkout_a_mux[] = {
1633 AUDIO_CLKOUT_A_MARK,
1634};
1635static const unsigned int audio_clkout_b_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(6, 28),
1638};
1639static const unsigned int audio_clkout_b_mux[] = {
1640 AUDIO_CLKOUT_B_MARK,
1641};
1642static const unsigned int audio_clkout_c_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(5, 3),
1645};
1646static const unsigned int audio_clkout_c_mux[] = {
1647 AUDIO_CLKOUT_C_MARK,
1648};
1649static const unsigned int audio_clkout_d_pins[] = {
1650 /* CLKOUT */
1651 RCAR_GP_PIN(5, 21),
1652};
1653static const unsigned int audio_clkout_d_mux[] = {
1654 AUDIO_CLKOUT_D_MARK,
1655};
1656static const unsigned int audio_clkout1_a_pins[] = {
1657 /* CLKOUT1 */
1658 RCAR_GP_PIN(5, 15),
1659};
1660static const unsigned int audio_clkout1_a_mux[] = {
1661 AUDIO_CLKOUT1_A_MARK,
1662};
1663static const unsigned int audio_clkout1_b_pins[] = {
1664 /* CLKOUT1 */
1665 RCAR_GP_PIN(6, 29),
1666};
1667static const unsigned int audio_clkout1_b_mux[] = {
1668 AUDIO_CLKOUT1_B_MARK,
1669};
1670static const unsigned int audio_clkout2_a_pins[] = {
1671 /* CLKOUT2 */
1672 RCAR_GP_PIN(5, 16),
1673};
1674static const unsigned int audio_clkout2_a_mux[] = {
1675 AUDIO_CLKOUT2_A_MARK,
1676};
1677static const unsigned int audio_clkout2_b_pins[] = {
1678 /* CLKOUT2 */
1679 RCAR_GP_PIN(6, 30),
1680};
1681static const unsigned int audio_clkout2_b_mux[] = {
1682 AUDIO_CLKOUT2_B_MARK,
1683};
1684
1685static const unsigned int audio_clkout3_a_pins[] = {
1686 /* CLKOUT3 */
1687 RCAR_GP_PIN(5, 19),
1688};
1689static const unsigned int audio_clkout3_a_mux[] = {
1690 AUDIO_CLKOUT3_A_MARK,
1691};
1692static const unsigned int audio_clkout3_b_pins[] = {
1693 /* CLKOUT3 */
1694 RCAR_GP_PIN(6, 31),
1695};
1696static const unsigned int audio_clkout3_b_mux[] = {
1697 AUDIO_CLKOUT3_B_MARK,
1698};
1699
1700/* - EtherAVB --------------------------------------------------------------- */
1701static const unsigned int avb_link_pins[] = {
1702 /* AVB_LINK */
1703 RCAR_GP_PIN(2, 12),
1704};
1705static const unsigned int avb_link_mux[] = {
1706 AVB_LINK_MARK,
1707};
1708static const unsigned int avb_magic_pins[] = {
1709 /* AVB_MAGIC_ */
1710 RCAR_GP_PIN(2, 10),
1711};
1712static const unsigned int avb_magic_mux[] = {
1713 AVB_MAGIC_MARK,
1714};
1715static const unsigned int avb_phy_int_pins[] = {
1716 /* AVB_PHY_INT */
1717 RCAR_GP_PIN(2, 11),
1718};
1719static const unsigned int avb_phy_int_mux[] = {
1720 AVB_PHY_INT_MARK,
1721};
1722static const unsigned int avb_mdio_pins[] = {
1723 /* AVB_MDC, AVB_MDIO */
1724 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1725};
1726static const unsigned int avb_mdio_mux[] = {
1727 AVB_MDC_MARK, AVB_MDIO_MARK,
1728};
1729static const unsigned int avb_mii_pins[] = {
1730 /*
1731 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732 * AVB_TD1, AVB_TD2, AVB_TD3,
1733 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734 * AVB_RD1, AVB_RD2, AVB_RD3,
1735 * AVB_TXCREFCLK
1736 */
1737 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741 PIN_NUMBER('A', 12),
1742
1743};
1744static const unsigned int avb_mii_mux[] = {
1745 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1749 AVB_TXCREFCLK_MARK,
1750};
1751static const unsigned int avb_avtp_pps_pins[] = {
1752 /* AVB_AVTP_PPS */
1753 RCAR_GP_PIN(2, 6),
1754};
1755static const unsigned int avb_avtp_pps_mux[] = {
1756 AVB_AVTP_PPS_MARK,
1757};
1758static const unsigned int avb_avtp_match_a_pins[] = {
1759 /* AVB_AVTP_MATCH_A */
1760 RCAR_GP_PIN(2, 13),
1761};
1762static const unsigned int avb_avtp_match_a_mux[] = {
1763 AVB_AVTP_MATCH_A_MARK,
1764};
1765static const unsigned int avb_avtp_capture_a_pins[] = {
1766 /* AVB_AVTP_CAPTURE_A */
1767 RCAR_GP_PIN(2, 14),
1768};
1769static const unsigned int avb_avtp_capture_a_mux[] = {
1770 AVB_AVTP_CAPTURE_A_MARK,
1771};
1772static const unsigned int avb_avtp_match_b_pins[] = {
1773 /* AVB_AVTP_MATCH_B */
1774 RCAR_GP_PIN(1, 8),
1775};
1776static const unsigned int avb_avtp_match_b_mux[] = {
1777 AVB_AVTP_MATCH_B_MARK,
1778};
1779static const unsigned int avb_avtp_capture_b_pins[] = {
1780 /* AVB_AVTP_CAPTURE_B */
1781 RCAR_GP_PIN(1, 11),
1782};
1783static const unsigned int avb_avtp_capture_b_mux[] = {
1784 AVB_AVTP_CAPTURE_B_MARK,
1785};
1786
1787/* - CAN ------------------------------------------------------------------ */
1788static const unsigned int can0_data_a_pins[] = {
1789 /* TX, RX */
1790 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1791};
1792static const unsigned int can0_data_a_mux[] = {
1793 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1794};
1795static const unsigned int can0_data_b_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1798};
1799static const unsigned int can0_data_b_mux[] = {
1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1801};
1802static const unsigned int can1_data_pins[] = {
1803 /* TX, RX */
1804 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1805};
1806static const unsigned int can1_data_mux[] = {
1807 CAN1_TX_MARK, CAN1_RX_MARK,
1808};
1809
1810/* - CAN Clock -------------------------------------------------------------- */
1811static const unsigned int can_clk_pins[] = {
1812 /* CLK */
1813 RCAR_GP_PIN(1, 25),
1814};
1815static const unsigned int can_clk_mux[] = {
1816 CAN_CLK_MARK,
1817};
1818
1819/* - CAN FD --------------------------------------------------------------- */
1820static const unsigned int canfd0_data_a_pins[] = {
1821 /* TX, RX */
1822 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1823};
1824static const unsigned int canfd0_data_a_mux[] = {
1825 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1826};
1827static const unsigned int canfd0_data_b_pins[] = {
1828 /* TX, RX */
1829 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1830};
1831static const unsigned int canfd0_data_b_mux[] = {
1832 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1833};
1834static const unsigned int canfd1_data_pins[] = {
1835 /* TX, RX */
1836 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1837};
1838static const unsigned int canfd1_data_mux[] = {
1839 CANFD1_TX_MARK, CANFD1_RX_MARK,
1840};
1841
1842/* - DRIF0 --------------------------------------------------------------- */
1843static const unsigned int drif0_ctrl_a_pins[] = {
1844 /* CLK, SYNC */
1845 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1846};
1847static const unsigned int drif0_ctrl_a_mux[] = {
1848 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1849};
1850static const unsigned int drif0_data0_a_pins[] = {
1851 /* D0 */
1852 RCAR_GP_PIN(6, 10),
1853};
1854static const unsigned int drif0_data0_a_mux[] = {
1855 RIF0_D0_A_MARK,
1856};
1857static const unsigned int drif0_data1_a_pins[] = {
1858 /* D1 */
1859 RCAR_GP_PIN(6, 7),
1860};
1861static const unsigned int drif0_data1_a_mux[] = {
1862 RIF0_D1_A_MARK,
1863};
1864static const unsigned int drif0_ctrl_b_pins[] = {
1865 /* CLK, SYNC */
1866 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1867};
1868static const unsigned int drif0_ctrl_b_mux[] = {
1869 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1870};
1871static const unsigned int drif0_data0_b_pins[] = {
1872 /* D0 */
1873 RCAR_GP_PIN(5, 1),
1874};
1875static const unsigned int drif0_data0_b_mux[] = {
1876 RIF0_D0_B_MARK,
1877};
1878static const unsigned int drif0_data1_b_pins[] = {
1879 /* D1 */
1880 RCAR_GP_PIN(5, 2),
1881};
1882static const unsigned int drif0_data1_b_mux[] = {
1883 RIF0_D1_B_MARK,
1884};
1885static const unsigned int drif0_ctrl_c_pins[] = {
1886 /* CLK, SYNC */
1887 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1888};
1889static const unsigned int drif0_ctrl_c_mux[] = {
1890 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1891};
1892static const unsigned int drif0_data0_c_pins[] = {
1893 /* D0 */
1894 RCAR_GP_PIN(5, 13),
1895};
1896static const unsigned int drif0_data0_c_mux[] = {
1897 RIF0_D0_C_MARK,
1898};
1899static const unsigned int drif0_data1_c_pins[] = {
1900 /* D1 */
1901 RCAR_GP_PIN(5, 14),
1902};
1903static const unsigned int drif0_data1_c_mux[] = {
1904 RIF0_D1_C_MARK,
1905};
1906/* - DRIF1 --------------------------------------------------------------- */
1907static const unsigned int drif1_ctrl_a_pins[] = {
1908 /* CLK, SYNC */
1909 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1910};
1911static const unsigned int drif1_ctrl_a_mux[] = {
1912 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1913};
1914static const unsigned int drif1_data0_a_pins[] = {
1915 /* D0 */
1916 RCAR_GP_PIN(6, 19),
1917};
1918static const unsigned int drif1_data0_a_mux[] = {
1919 RIF1_D0_A_MARK,
1920};
1921static const unsigned int drif1_data1_a_pins[] = {
1922 /* D1 */
1923 RCAR_GP_PIN(6, 20),
1924};
1925static const unsigned int drif1_data1_a_mux[] = {
1926 RIF1_D1_A_MARK,
1927};
1928static const unsigned int drif1_ctrl_b_pins[] = {
1929 /* CLK, SYNC */
1930 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1931};
1932static const unsigned int drif1_ctrl_b_mux[] = {
1933 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1934};
1935static const unsigned int drif1_data0_b_pins[] = {
1936 /* D0 */
1937 RCAR_GP_PIN(5, 7),
1938};
1939static const unsigned int drif1_data0_b_mux[] = {
1940 RIF1_D0_B_MARK,
1941};
1942static const unsigned int drif1_data1_b_pins[] = {
1943 /* D1 */
1944 RCAR_GP_PIN(5, 8),
1945};
1946static const unsigned int drif1_data1_b_mux[] = {
1947 RIF1_D1_B_MARK,
1948};
1949static const unsigned int drif1_ctrl_c_pins[] = {
1950 /* CLK, SYNC */
1951 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1952};
1953static const unsigned int drif1_ctrl_c_mux[] = {
1954 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1955};
1956static const unsigned int drif1_data0_c_pins[] = {
1957 /* D0 */
1958 RCAR_GP_PIN(5, 6),
1959};
1960static const unsigned int drif1_data0_c_mux[] = {
1961 RIF1_D0_C_MARK,
1962};
1963static const unsigned int drif1_data1_c_pins[] = {
1964 /* D1 */
1965 RCAR_GP_PIN(5, 10),
1966};
1967static const unsigned int drif1_data1_c_mux[] = {
1968 RIF1_D1_C_MARK,
1969};
1970/* - DRIF2 --------------------------------------------------------------- */
1971static const unsigned int drif2_ctrl_a_pins[] = {
1972 /* CLK, SYNC */
1973 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1974};
1975static const unsigned int drif2_ctrl_a_mux[] = {
1976 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1977};
1978static const unsigned int drif2_data0_a_pins[] = {
1979 /* D0 */
1980 RCAR_GP_PIN(6, 7),
1981};
1982static const unsigned int drif2_data0_a_mux[] = {
1983 RIF2_D0_A_MARK,
1984};
1985static const unsigned int drif2_data1_a_pins[] = {
1986 /* D1 */
1987 RCAR_GP_PIN(6, 10),
1988};
1989static const unsigned int drif2_data1_a_mux[] = {
1990 RIF2_D1_A_MARK,
1991};
1992static const unsigned int drif2_ctrl_b_pins[] = {
1993 /* CLK, SYNC */
1994 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1995};
1996static const unsigned int drif2_ctrl_b_mux[] = {
1997 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1998};
1999static const unsigned int drif2_data0_b_pins[] = {
2000 /* D0 */
2001 RCAR_GP_PIN(6, 30),
2002};
2003static const unsigned int drif2_data0_b_mux[] = {
2004 RIF2_D0_B_MARK,
2005};
2006static const unsigned int drif2_data1_b_pins[] = {
2007 /* D1 */
2008 RCAR_GP_PIN(6, 31),
2009};
2010static const unsigned int drif2_data1_b_mux[] = {
2011 RIF2_D1_B_MARK,
2012};
2013/* - DRIF3 --------------------------------------------------------------- */
2014static const unsigned int drif3_ctrl_a_pins[] = {
2015 /* CLK, SYNC */
2016 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2017};
2018static const unsigned int drif3_ctrl_a_mux[] = {
2019 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2020};
2021static const unsigned int drif3_data0_a_pins[] = {
2022 /* D0 */
2023 RCAR_GP_PIN(6, 19),
2024};
2025static const unsigned int drif3_data0_a_mux[] = {
2026 RIF3_D0_A_MARK,
2027};
2028static const unsigned int drif3_data1_a_pins[] = {
2029 /* D1 */
2030 RCAR_GP_PIN(6, 20),
2031};
2032static const unsigned int drif3_data1_a_mux[] = {
2033 RIF3_D1_A_MARK,
2034};
2035static const unsigned int drif3_ctrl_b_pins[] = {
2036 /* CLK, SYNC */
2037 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2038};
2039static const unsigned int drif3_ctrl_b_mux[] = {
2040 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2041};
2042static const unsigned int drif3_data0_b_pins[] = {
2043 /* D0 */
2044 RCAR_GP_PIN(6, 28),
2045};
2046static const unsigned int drif3_data0_b_mux[] = {
2047 RIF3_D0_B_MARK,
2048};
2049static const unsigned int drif3_data1_b_pins[] = {
2050 /* D1 */
2051 RCAR_GP_PIN(6, 29),
2052};
2053static const unsigned int drif3_data1_b_mux[] = {
2054 RIF3_D1_B_MARK,
2055};
2056
2057/* - DU --------------------------------------------------------------------- */
2058static const unsigned int du_rgb666_pins[] = {
2059 /* R[7:2], G[7:2], B[7:2] */
2060 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2061 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2062 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2063 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2064 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2065 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2066};
2067static const unsigned int du_rgb666_mux[] = {
2068 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2069 DU_DR3_MARK, DU_DR2_MARK,
2070 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2071 DU_DG3_MARK, DU_DG2_MARK,
2072 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2073 DU_DB3_MARK, DU_DB2_MARK,
2074};
2075static const unsigned int du_rgb888_pins[] = {
2076 /* R[7:0], G[7:0], B[7:0] */
2077 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2078 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2079 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2080 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2081 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2082 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2083 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2084 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2085 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2086};
2087static const unsigned int du_rgb888_mux[] = {
2088 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2089 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2090 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2091 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2092 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2093 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2094};
2095static const unsigned int du_clk_out_0_pins[] = {
2096 /* CLKOUT */
2097 RCAR_GP_PIN(1, 27),
2098};
2099static const unsigned int du_clk_out_0_mux[] = {
2100 DU_DOTCLKOUT0_MARK
2101};
2102static const unsigned int du_clk_out_1_pins[] = {
2103 /* CLKOUT */
2104 RCAR_GP_PIN(2, 3),
2105};
2106static const unsigned int du_clk_out_1_mux[] = {
2107 DU_DOTCLKOUT1_MARK
2108};
2109static const unsigned int du_sync_pins[] = {
2110 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2111 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2112};
2113static const unsigned int du_sync_mux[] = {
2114 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2115};
2116static const unsigned int du_oddf_pins[] = {
2117 /* EXDISP/EXODDF/EXCDE */
2118 RCAR_GP_PIN(2, 2),
2119};
2120static const unsigned int du_oddf_mux[] = {
2121 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2122};
2123static const unsigned int du_cde_pins[] = {
2124 /* CDE */
2125 RCAR_GP_PIN(2, 0),
2126};
2127static const unsigned int du_cde_mux[] = {
2128 DU_CDE_MARK,
2129};
2130static const unsigned int du_disp_pins[] = {
2131 /* DISP */
2132 RCAR_GP_PIN(2, 1),
2133};
2134static const unsigned int du_disp_mux[] = {
2135 DU_DISP_MARK,
2136};
2137
2138/* - HSCIF0 ----------------------------------------------------------------- */
2139static const unsigned int hscif0_data_pins[] = {
2140 /* RX, TX */
2141 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2142};
2143static const unsigned int hscif0_data_mux[] = {
2144 HRX0_MARK, HTX0_MARK,
2145};
2146static const unsigned int hscif0_clk_pins[] = {
2147 /* SCK */
2148 RCAR_GP_PIN(5, 12),
2149};
2150static const unsigned int hscif0_clk_mux[] = {
2151 HSCK0_MARK,
2152};
2153static const unsigned int hscif0_ctrl_pins[] = {
2154 /* RTS, CTS */
2155 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2156};
2157static const unsigned int hscif0_ctrl_mux[] = {
2158 HRTS0_N_MARK, HCTS0_N_MARK,
2159};
2160/* - HSCIF1 ----------------------------------------------------------------- */
2161static const unsigned int hscif1_data_a_pins[] = {
2162 /* RX, TX */
2163 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2164};
2165static const unsigned int hscif1_data_a_mux[] = {
2166 HRX1_A_MARK, HTX1_A_MARK,
2167};
2168static const unsigned int hscif1_clk_a_pins[] = {
2169 /* SCK */
2170 RCAR_GP_PIN(6, 21),
2171};
2172static const unsigned int hscif1_clk_a_mux[] = {
2173 HSCK1_A_MARK,
2174};
2175static const unsigned int hscif1_ctrl_a_pins[] = {
2176 /* RTS, CTS */
2177 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2178};
2179static const unsigned int hscif1_ctrl_a_mux[] = {
2180 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2181};
2182
2183static const unsigned int hscif1_data_b_pins[] = {
2184 /* RX, TX */
2185 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2186};
2187static const unsigned int hscif1_data_b_mux[] = {
2188 HRX1_B_MARK, HTX1_B_MARK,
2189};
2190static const unsigned int hscif1_clk_b_pins[] = {
2191 /* SCK */
2192 RCAR_GP_PIN(5, 0),
2193};
2194static const unsigned int hscif1_clk_b_mux[] = {
2195 HSCK1_B_MARK,
2196};
2197static const unsigned int hscif1_ctrl_b_pins[] = {
2198 /* RTS, CTS */
2199 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2200};
2201static const unsigned int hscif1_ctrl_b_mux[] = {
2202 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2203};
2204/* - HSCIF2 ----------------------------------------------------------------- */
2205static const unsigned int hscif2_data_a_pins[] = {
2206 /* RX, TX */
2207 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2208};
2209static const unsigned int hscif2_data_a_mux[] = {
2210 HRX2_A_MARK, HTX2_A_MARK,
2211};
2212static const unsigned int hscif2_clk_a_pins[] = {
2213 /* SCK */
2214 RCAR_GP_PIN(6, 10),
2215};
2216static const unsigned int hscif2_clk_a_mux[] = {
2217 HSCK2_A_MARK,
2218};
2219static const unsigned int hscif2_ctrl_a_pins[] = {
2220 /* RTS, CTS */
2221 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2222};
2223static const unsigned int hscif2_ctrl_a_mux[] = {
2224 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2225};
2226
2227static const unsigned int hscif2_data_b_pins[] = {
2228 /* RX, TX */
2229 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2230};
2231static const unsigned int hscif2_data_b_mux[] = {
2232 HRX2_B_MARK, HTX2_B_MARK,
2233};
2234static const unsigned int hscif2_clk_b_pins[] = {
2235 /* SCK */
2236 RCAR_GP_PIN(6, 21),
2237};
2238static const unsigned int hscif2_clk_b_mux[] = {
2239 HSCK2_B_MARK,
2240};
2241static const unsigned int hscif2_ctrl_b_pins[] = {
2242 /* RTS, CTS */
2243 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2244};
2245static const unsigned int hscif2_ctrl_b_mux[] = {
2246 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2247};
2248
2249static const unsigned int hscif2_data_c_pins[] = {
2250 /* RX, TX */
2251 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2252};
2253static const unsigned int hscif2_data_c_mux[] = {
2254 HRX2_C_MARK, HTX2_C_MARK,
2255};
2256static const unsigned int hscif2_clk_c_pins[] = {
2257 /* SCK */
2258 RCAR_GP_PIN(6, 24),
2259};
2260static const unsigned int hscif2_clk_c_mux[] = {
2261 HSCK2_C_MARK,
2262};
2263static const unsigned int hscif2_ctrl_c_pins[] = {
2264 /* RTS, CTS */
2265 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2266};
2267static const unsigned int hscif2_ctrl_c_mux[] = {
2268 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2269};
2270/* - HSCIF3 ----------------------------------------------------------------- */
2271static const unsigned int hscif3_data_a_pins[] = {
2272 /* RX, TX */
2273 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2274};
2275static const unsigned int hscif3_data_a_mux[] = {
2276 HRX3_A_MARK, HTX3_A_MARK,
2277};
2278static const unsigned int hscif3_clk_pins[] = {
2279 /* SCK */
2280 RCAR_GP_PIN(1, 22),
2281};
2282static const unsigned int hscif3_clk_mux[] = {
2283 HSCK3_MARK,
2284};
2285static const unsigned int hscif3_ctrl_pins[] = {
2286 /* RTS, CTS */
2287 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2288};
2289static const unsigned int hscif3_ctrl_mux[] = {
2290 HRTS3_N_MARK, HCTS3_N_MARK,
2291};
2292
2293static const unsigned int hscif3_data_b_pins[] = {
2294 /* RX, TX */
2295 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2296};
2297static const unsigned int hscif3_data_b_mux[] = {
2298 HRX3_B_MARK, HTX3_B_MARK,
2299};
2300static const unsigned int hscif3_data_c_pins[] = {
2301 /* RX, TX */
2302 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2303};
2304static const unsigned int hscif3_data_c_mux[] = {
2305 HRX3_C_MARK, HTX3_C_MARK,
2306};
2307static const unsigned int hscif3_data_d_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2310};
2311static const unsigned int hscif3_data_d_mux[] = {
2312 HRX3_D_MARK, HTX3_D_MARK,
2313};
2314/* - HSCIF4 ----------------------------------------------------------------- */
2315static const unsigned int hscif4_data_a_pins[] = {
2316 /* RX, TX */
2317 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2318};
2319static const unsigned int hscif4_data_a_mux[] = {
2320 HRX4_A_MARK, HTX4_A_MARK,
2321};
2322static const unsigned int hscif4_clk_pins[] = {
2323 /* SCK */
2324 RCAR_GP_PIN(1, 11),
2325};
2326static const unsigned int hscif4_clk_mux[] = {
2327 HSCK4_MARK,
2328};
2329static const unsigned int hscif4_ctrl_pins[] = {
2330 /* RTS, CTS */
2331 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2332};
2333static const unsigned int hscif4_ctrl_mux[] = {
2334 HRTS4_N_MARK, HCTS4_N_MARK,
2335};
2336
2337static const unsigned int hscif4_data_b_pins[] = {
2338 /* RX, TX */
2339 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2340};
2341static const unsigned int hscif4_data_b_mux[] = {
2342 HRX4_B_MARK, HTX4_B_MARK,
2343};
2344
2345/* - I2C -------------------------------------------------------------------- */
2346static const unsigned int i2c0_pins[] = {
2347 /* SCL, SDA */
2348 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2349};
2350
2351static const unsigned int i2c0_mux[] = {
2352 SCL0_MARK, SDA0_MARK,
2353};
2354
2355static const unsigned int i2c1_a_pins[] = {
2356 /* SDA, SCL */
2357 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2358};
2359static const unsigned int i2c1_a_mux[] = {
2360 SDA1_A_MARK, SCL1_A_MARK,
2361};
2362static const unsigned int i2c1_b_pins[] = {
2363 /* SDA, SCL */
2364 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2365};
2366static const unsigned int i2c1_b_mux[] = {
2367 SDA1_B_MARK, SCL1_B_MARK,
2368};
2369static const unsigned int i2c2_a_pins[] = {
2370 /* SDA, SCL */
2371 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2372};
2373static const unsigned int i2c2_a_mux[] = {
2374 SDA2_A_MARK, SCL2_A_MARK,
2375};
2376static const unsigned int i2c2_b_pins[] = {
2377 /* SDA, SCL */
2378 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2379};
2380static const unsigned int i2c2_b_mux[] = {
2381 SDA2_B_MARK, SCL2_B_MARK,
2382};
2383
2384static const unsigned int i2c3_pins[] = {
2385 /* SCL, SDA */
2386 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2387};
2388
2389static const unsigned int i2c3_mux[] = {
2390 SCL3_MARK, SDA3_MARK,
2391};
2392
2393static const unsigned int i2c5_pins[] = {
2394 /* SCL, SDA */
2395 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2396};
2397
2398static const unsigned int i2c5_mux[] = {
2399 SCL5_MARK, SDA5_MARK,
2400};
2401
2402static const unsigned int i2c6_a_pins[] = {
2403 /* SDA, SCL */
2404 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2405};
2406static const unsigned int i2c6_a_mux[] = {
2407 SDA6_A_MARK, SCL6_A_MARK,
2408};
2409static const unsigned int i2c6_b_pins[] = {
2410 /* SDA, SCL */
2411 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2412};
2413static const unsigned int i2c6_b_mux[] = {
2414 SDA6_B_MARK, SCL6_B_MARK,
2415};
2416static const unsigned int i2c6_c_pins[] = {
2417 /* SDA, SCL */
2418 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2419};
2420static const unsigned int i2c6_c_mux[] = {
2421 SDA6_C_MARK, SCL6_C_MARK,
2422};
2423
2424/* - INTC-EX ---------------------------------------------------------------- */
2425static const unsigned int intc_ex_irq0_pins[] = {
2426 /* IRQ0 */
2427 RCAR_GP_PIN(2, 0),
2428};
2429static const unsigned int intc_ex_irq0_mux[] = {
2430 IRQ0_MARK,
2431};
2432static const unsigned int intc_ex_irq1_pins[] = {
2433 /* IRQ1 */
2434 RCAR_GP_PIN(2, 1),
2435};
2436static const unsigned int intc_ex_irq1_mux[] = {
2437 IRQ1_MARK,
2438};
2439static const unsigned int intc_ex_irq2_pins[] = {
2440 /* IRQ2 */
2441 RCAR_GP_PIN(2, 2),
2442};
2443static const unsigned int intc_ex_irq2_mux[] = {
2444 IRQ2_MARK,
2445};
2446static const unsigned int intc_ex_irq3_pins[] = {
2447 /* IRQ3 */
2448 RCAR_GP_PIN(2, 3),
2449};
2450static const unsigned int intc_ex_irq3_mux[] = {
2451 IRQ3_MARK,
2452};
2453static const unsigned int intc_ex_irq4_pins[] = {
2454 /* IRQ4 */
2455 RCAR_GP_PIN(2, 4),
2456};
2457static const unsigned int intc_ex_irq4_mux[] = {
2458 IRQ4_MARK,
2459};
2460static const unsigned int intc_ex_irq5_pins[] = {
2461 /* IRQ5 */
2462 RCAR_GP_PIN(2, 5),
2463};
2464static const unsigned int intc_ex_irq5_mux[] = {
2465 IRQ5_MARK,
2466};
2467
2468/* - MSIOF0 ----------------------------------------------------------------- */
2469static const unsigned int msiof0_clk_pins[] = {
2470 /* SCK */
2471 RCAR_GP_PIN(5, 17),
2472};
2473static const unsigned int msiof0_clk_mux[] = {
2474 MSIOF0_SCK_MARK,
2475};
2476static const unsigned int msiof0_sync_pins[] = {
2477 /* SYNC */
2478 RCAR_GP_PIN(5, 18),
2479};
2480static const unsigned int msiof0_sync_mux[] = {
2481 MSIOF0_SYNC_MARK,
2482};
2483static const unsigned int msiof0_ss1_pins[] = {
2484 /* SS1 */
2485 RCAR_GP_PIN(5, 19),
2486};
2487static const unsigned int msiof0_ss1_mux[] = {
2488 MSIOF0_SS1_MARK,
2489};
2490static const unsigned int msiof0_ss2_pins[] = {
2491 /* SS2 */
2492 RCAR_GP_PIN(5, 21),
2493};
2494static const unsigned int msiof0_ss2_mux[] = {
2495 MSIOF0_SS2_MARK,
2496};
2497static const unsigned int msiof0_txd_pins[] = {
2498 /* TXD */
2499 RCAR_GP_PIN(5, 20),
2500};
2501static const unsigned int msiof0_txd_mux[] = {
2502 MSIOF0_TXD_MARK,
2503};
2504static const unsigned int msiof0_rxd_pins[] = {
2505 /* RXD */
2506 RCAR_GP_PIN(5, 22),
2507};
2508static const unsigned int msiof0_rxd_mux[] = {
2509 MSIOF0_RXD_MARK,
2510};
2511/* - MSIOF1 ----------------------------------------------------------------- */
2512static const unsigned int msiof1_clk_a_pins[] = {
2513 /* SCK */
2514 RCAR_GP_PIN(6, 8),
2515};
2516static const unsigned int msiof1_clk_a_mux[] = {
2517 MSIOF1_SCK_A_MARK,
2518};
2519static const unsigned int msiof1_sync_a_pins[] = {
2520 /* SYNC */
2521 RCAR_GP_PIN(6, 9),
2522};
2523static const unsigned int msiof1_sync_a_mux[] = {
2524 MSIOF1_SYNC_A_MARK,
2525};
2526static const unsigned int msiof1_ss1_a_pins[] = {
2527 /* SS1 */
2528 RCAR_GP_PIN(6, 5),
2529};
2530static const unsigned int msiof1_ss1_a_mux[] = {
2531 MSIOF1_SS1_A_MARK,
2532};
2533static const unsigned int msiof1_ss2_a_pins[] = {
2534 /* SS2 */
2535 RCAR_GP_PIN(6, 6),
2536};
2537static const unsigned int msiof1_ss2_a_mux[] = {
2538 MSIOF1_SS2_A_MARK,
2539};
2540static const unsigned int msiof1_txd_a_pins[] = {
2541 /* TXD */
2542 RCAR_GP_PIN(6, 7),
2543};
2544static const unsigned int msiof1_txd_a_mux[] = {
2545 MSIOF1_TXD_A_MARK,
2546};
2547static const unsigned int msiof1_rxd_a_pins[] = {
2548 /* RXD */
2549 RCAR_GP_PIN(6, 10),
2550};
2551static const unsigned int msiof1_rxd_a_mux[] = {
2552 MSIOF1_RXD_A_MARK,
2553};
2554static const unsigned int msiof1_clk_b_pins[] = {
2555 /* SCK */
2556 RCAR_GP_PIN(5, 9),
2557};
2558static const unsigned int msiof1_clk_b_mux[] = {
2559 MSIOF1_SCK_B_MARK,
2560};
2561static const unsigned int msiof1_sync_b_pins[] = {
2562 /* SYNC */
2563 RCAR_GP_PIN(5, 3),
2564};
2565static const unsigned int msiof1_sync_b_mux[] = {
2566 MSIOF1_SYNC_B_MARK,
2567};
2568static const unsigned int msiof1_ss1_b_pins[] = {
2569 /* SS1 */
2570 RCAR_GP_PIN(5, 4),
2571};
2572static const unsigned int msiof1_ss1_b_mux[] = {
2573 MSIOF1_SS1_B_MARK,
2574};
2575static const unsigned int msiof1_ss2_b_pins[] = {
2576 /* SS2 */
2577 RCAR_GP_PIN(5, 0),
2578};
2579static const unsigned int msiof1_ss2_b_mux[] = {
2580 MSIOF1_SS2_B_MARK,
2581};
2582static const unsigned int msiof1_txd_b_pins[] = {
2583 /* TXD */
2584 RCAR_GP_PIN(5, 8),
2585};
2586static const unsigned int msiof1_txd_b_mux[] = {
2587 MSIOF1_TXD_B_MARK,
2588};
2589static const unsigned int msiof1_rxd_b_pins[] = {
2590 /* RXD */
2591 RCAR_GP_PIN(5, 7),
2592};
2593static const unsigned int msiof1_rxd_b_mux[] = {
2594 MSIOF1_RXD_B_MARK,
2595};
2596static const unsigned int msiof1_clk_c_pins[] = {
2597 /* SCK */
2598 RCAR_GP_PIN(6, 17),
2599};
2600static const unsigned int msiof1_clk_c_mux[] = {
2601 MSIOF1_SCK_C_MARK,
2602};
2603static const unsigned int msiof1_sync_c_pins[] = {
2604 /* SYNC */
2605 RCAR_GP_PIN(6, 18),
2606};
2607static const unsigned int msiof1_sync_c_mux[] = {
2608 MSIOF1_SYNC_C_MARK,
2609};
2610static const unsigned int msiof1_ss1_c_pins[] = {
2611 /* SS1 */
2612 RCAR_GP_PIN(6, 21),
2613};
2614static const unsigned int msiof1_ss1_c_mux[] = {
2615 MSIOF1_SS1_C_MARK,
2616};
2617static const unsigned int msiof1_ss2_c_pins[] = {
2618 /* SS2 */
2619 RCAR_GP_PIN(6, 27),
2620};
2621static const unsigned int msiof1_ss2_c_mux[] = {
2622 MSIOF1_SS2_C_MARK,
2623};
2624static const unsigned int msiof1_txd_c_pins[] = {
2625 /* TXD */
2626 RCAR_GP_PIN(6, 20),
2627};
2628static const unsigned int msiof1_txd_c_mux[] = {
2629 MSIOF1_TXD_C_MARK,
2630};
2631static const unsigned int msiof1_rxd_c_pins[] = {
2632 /* RXD */
2633 RCAR_GP_PIN(6, 19),
2634};
2635static const unsigned int msiof1_rxd_c_mux[] = {
2636 MSIOF1_RXD_C_MARK,
2637};
2638static const unsigned int msiof1_clk_d_pins[] = {
2639 /* SCK */
2640 RCAR_GP_PIN(5, 12),
2641};
2642static const unsigned int msiof1_clk_d_mux[] = {
2643 MSIOF1_SCK_D_MARK,
2644};
2645static const unsigned int msiof1_sync_d_pins[] = {
2646 /* SYNC */
2647 RCAR_GP_PIN(5, 15),
2648};
2649static const unsigned int msiof1_sync_d_mux[] = {
2650 MSIOF1_SYNC_D_MARK,
2651};
2652static const unsigned int msiof1_ss1_d_pins[] = {
2653 /* SS1 */
2654 RCAR_GP_PIN(5, 16),
2655};
2656static const unsigned int msiof1_ss1_d_mux[] = {
2657 MSIOF1_SS1_D_MARK,
2658};
2659static const unsigned int msiof1_ss2_d_pins[] = {
2660 /* SS2 */
2661 RCAR_GP_PIN(5, 21),
2662};
2663static const unsigned int msiof1_ss2_d_mux[] = {
2664 MSIOF1_SS2_D_MARK,
2665};
2666static const unsigned int msiof1_txd_d_pins[] = {
2667 /* TXD */
2668 RCAR_GP_PIN(5, 14),
2669};
2670static const unsigned int msiof1_txd_d_mux[] = {
2671 MSIOF1_TXD_D_MARK,
2672};
2673static const unsigned int msiof1_rxd_d_pins[] = {
2674 /* RXD */
2675 RCAR_GP_PIN(5, 13),
2676};
2677static const unsigned int msiof1_rxd_d_mux[] = {
2678 MSIOF1_RXD_D_MARK,
2679};
2680static const unsigned int msiof1_clk_e_pins[] = {
2681 /* SCK */
2682 RCAR_GP_PIN(3, 0),
2683};
2684static const unsigned int msiof1_clk_e_mux[] = {
2685 MSIOF1_SCK_E_MARK,
2686};
2687static const unsigned int msiof1_sync_e_pins[] = {
2688 /* SYNC */
2689 RCAR_GP_PIN(3, 1),
2690};
2691static const unsigned int msiof1_sync_e_mux[] = {
2692 MSIOF1_SYNC_E_MARK,
2693};
2694static const unsigned int msiof1_ss1_e_pins[] = {
2695 /* SS1 */
2696 RCAR_GP_PIN(3, 4),
2697};
2698static const unsigned int msiof1_ss1_e_mux[] = {
2699 MSIOF1_SS1_E_MARK,
2700};
2701static const unsigned int msiof1_ss2_e_pins[] = {
2702 /* SS2 */
2703 RCAR_GP_PIN(3, 5),
2704};
2705static const unsigned int msiof1_ss2_e_mux[] = {
2706 MSIOF1_SS2_E_MARK,
2707};
2708static const unsigned int msiof1_txd_e_pins[] = {
2709 /* TXD */
2710 RCAR_GP_PIN(3, 3),
2711};
2712static const unsigned int msiof1_txd_e_mux[] = {
2713 MSIOF1_TXD_E_MARK,
2714};
2715static const unsigned int msiof1_rxd_e_pins[] = {
2716 /* RXD */
2717 RCAR_GP_PIN(3, 2),
2718};
2719static const unsigned int msiof1_rxd_e_mux[] = {
2720 MSIOF1_RXD_E_MARK,
2721};
2722static const unsigned int msiof1_clk_f_pins[] = {
2723 /* SCK */
2724 RCAR_GP_PIN(5, 23),
2725};
2726static const unsigned int msiof1_clk_f_mux[] = {
2727 MSIOF1_SCK_F_MARK,
2728};
2729static const unsigned int msiof1_sync_f_pins[] = {
2730 /* SYNC */
2731 RCAR_GP_PIN(5, 24),
2732};
2733static const unsigned int msiof1_sync_f_mux[] = {
2734 MSIOF1_SYNC_F_MARK,
2735};
2736static const unsigned int msiof1_ss1_f_pins[] = {
2737 /* SS1 */
2738 RCAR_GP_PIN(6, 1),
2739};
2740static const unsigned int msiof1_ss1_f_mux[] = {
2741 MSIOF1_SS1_F_MARK,
2742};
2743static const unsigned int msiof1_ss2_f_pins[] = {
2744 /* SS2 */
2745 RCAR_GP_PIN(6, 2),
2746};
2747static const unsigned int msiof1_ss2_f_mux[] = {
2748 MSIOF1_SS2_F_MARK,
2749};
2750static const unsigned int msiof1_txd_f_pins[] = {
2751 /* TXD */
2752 RCAR_GP_PIN(6, 0),
2753};
2754static const unsigned int msiof1_txd_f_mux[] = {
2755 MSIOF1_TXD_F_MARK,
2756};
2757static const unsigned int msiof1_rxd_f_pins[] = {
2758 /* RXD */
2759 RCAR_GP_PIN(5, 25),
2760};
2761static const unsigned int msiof1_rxd_f_mux[] = {
2762 MSIOF1_RXD_F_MARK,
2763};
2764static const unsigned int msiof1_clk_g_pins[] = {
2765 /* SCK */
2766 RCAR_GP_PIN(3, 6),
2767};
2768static const unsigned int msiof1_clk_g_mux[] = {
2769 MSIOF1_SCK_G_MARK,
2770};
2771static const unsigned int msiof1_sync_g_pins[] = {
2772 /* SYNC */
2773 RCAR_GP_PIN(3, 7),
2774};
2775static const unsigned int msiof1_sync_g_mux[] = {
2776 MSIOF1_SYNC_G_MARK,
2777};
2778static const unsigned int msiof1_ss1_g_pins[] = {
2779 /* SS1 */
2780 RCAR_GP_PIN(3, 10),
2781};
2782static const unsigned int msiof1_ss1_g_mux[] = {
2783 MSIOF1_SS1_G_MARK,
2784};
2785static const unsigned int msiof1_ss2_g_pins[] = {
2786 /* SS2 */
2787 RCAR_GP_PIN(3, 11),
2788};
2789static const unsigned int msiof1_ss2_g_mux[] = {
2790 MSIOF1_SS2_G_MARK,
2791};
2792static const unsigned int msiof1_txd_g_pins[] = {
2793 /* TXD */
2794 RCAR_GP_PIN(3, 9),
2795};
2796static const unsigned int msiof1_txd_g_mux[] = {
2797 MSIOF1_TXD_G_MARK,
2798};
2799static const unsigned int msiof1_rxd_g_pins[] = {
2800 /* RXD */
2801 RCAR_GP_PIN(3, 8),
2802};
2803static const unsigned int msiof1_rxd_g_mux[] = {
2804 MSIOF1_RXD_G_MARK,
2805};
2806/* - MSIOF2 ----------------------------------------------------------------- */
2807static const unsigned int msiof2_clk_a_pins[] = {
2808 /* SCK */
2809 RCAR_GP_PIN(1, 9),
2810};
2811static const unsigned int msiof2_clk_a_mux[] = {
2812 MSIOF2_SCK_A_MARK,
2813};
2814static const unsigned int msiof2_sync_a_pins[] = {
2815 /* SYNC */
2816 RCAR_GP_PIN(1, 8),
2817};
2818static const unsigned int msiof2_sync_a_mux[] = {
2819 MSIOF2_SYNC_A_MARK,
2820};
2821static const unsigned int msiof2_ss1_a_pins[] = {
2822 /* SS1 */
2823 RCAR_GP_PIN(1, 6),
2824};
2825static const unsigned int msiof2_ss1_a_mux[] = {
2826 MSIOF2_SS1_A_MARK,
2827};
2828static const unsigned int msiof2_ss2_a_pins[] = {
2829 /* SS2 */
2830 RCAR_GP_PIN(1, 7),
2831};
2832static const unsigned int msiof2_ss2_a_mux[] = {
2833 MSIOF2_SS2_A_MARK,
2834};
2835static const unsigned int msiof2_txd_a_pins[] = {
2836 /* TXD */
2837 RCAR_GP_PIN(1, 11),
2838};
2839static const unsigned int msiof2_txd_a_mux[] = {
2840 MSIOF2_TXD_A_MARK,
2841};
2842static const unsigned int msiof2_rxd_a_pins[] = {
2843 /* RXD */
2844 RCAR_GP_PIN(1, 10),
2845};
2846static const unsigned int msiof2_rxd_a_mux[] = {
2847 MSIOF2_RXD_A_MARK,
2848};
2849static const unsigned int msiof2_clk_b_pins[] = {
2850 /* SCK */
2851 RCAR_GP_PIN(0, 4),
2852};
2853static const unsigned int msiof2_clk_b_mux[] = {
2854 MSIOF2_SCK_B_MARK,
2855};
2856static const unsigned int msiof2_sync_b_pins[] = {
2857 /* SYNC */
2858 RCAR_GP_PIN(0, 5),
2859};
2860static const unsigned int msiof2_sync_b_mux[] = {
2861 MSIOF2_SYNC_B_MARK,
2862};
2863static const unsigned int msiof2_ss1_b_pins[] = {
2864 /* SS1 */
2865 RCAR_GP_PIN(0, 0),
2866};
2867static const unsigned int msiof2_ss1_b_mux[] = {
2868 MSIOF2_SS1_B_MARK,
2869};
2870static const unsigned int msiof2_ss2_b_pins[] = {
2871 /* SS2 */
2872 RCAR_GP_PIN(0, 1),
2873};
2874static const unsigned int msiof2_ss2_b_mux[] = {
2875 MSIOF2_SS2_B_MARK,
2876};
2877static const unsigned int msiof2_txd_b_pins[] = {
2878 /* TXD */
2879 RCAR_GP_PIN(0, 7),
2880};
2881static const unsigned int msiof2_txd_b_mux[] = {
2882 MSIOF2_TXD_B_MARK,
2883};
2884static const unsigned int msiof2_rxd_b_pins[] = {
2885 /* RXD */
2886 RCAR_GP_PIN(0, 6),
2887};
2888static const unsigned int msiof2_rxd_b_mux[] = {
2889 MSIOF2_RXD_B_MARK,
2890};
2891static const unsigned int msiof2_clk_c_pins[] = {
2892 /* SCK */
2893 RCAR_GP_PIN(2, 12),
2894};
2895static const unsigned int msiof2_clk_c_mux[] = {
2896 MSIOF2_SCK_C_MARK,
2897};
2898static const unsigned int msiof2_sync_c_pins[] = {
2899 /* SYNC */
2900 RCAR_GP_PIN(2, 11),
2901};
2902static const unsigned int msiof2_sync_c_mux[] = {
2903 MSIOF2_SYNC_C_MARK,
2904};
2905static const unsigned int msiof2_ss1_c_pins[] = {
2906 /* SS1 */
2907 RCAR_GP_PIN(2, 10),
2908};
2909static const unsigned int msiof2_ss1_c_mux[] = {
2910 MSIOF2_SS1_C_MARK,
2911};
2912static const unsigned int msiof2_ss2_c_pins[] = {
2913 /* SS2 */
2914 RCAR_GP_PIN(2, 9),
2915};
2916static const unsigned int msiof2_ss2_c_mux[] = {
2917 MSIOF2_SS2_C_MARK,
2918};
2919static const unsigned int msiof2_txd_c_pins[] = {
2920 /* TXD */
2921 RCAR_GP_PIN(2, 14),
2922};
2923static const unsigned int msiof2_txd_c_mux[] = {
2924 MSIOF2_TXD_C_MARK,
2925};
2926static const unsigned int msiof2_rxd_c_pins[] = {
2927 /* RXD */
2928 RCAR_GP_PIN(2, 13),
2929};
2930static const unsigned int msiof2_rxd_c_mux[] = {
2931 MSIOF2_RXD_C_MARK,
2932};
2933static const unsigned int msiof2_clk_d_pins[] = {
2934 /* SCK */
2935 RCAR_GP_PIN(0, 8),
2936};
2937static const unsigned int msiof2_clk_d_mux[] = {
2938 MSIOF2_SCK_D_MARK,
2939};
2940static const unsigned int msiof2_sync_d_pins[] = {
2941 /* SYNC */
2942 RCAR_GP_PIN(0, 9),
2943};
2944static const unsigned int msiof2_sync_d_mux[] = {
2945 MSIOF2_SYNC_D_MARK,
2946};
2947static const unsigned int msiof2_ss1_d_pins[] = {
2948 /* SS1 */
2949 RCAR_GP_PIN(0, 12),
2950};
2951static const unsigned int msiof2_ss1_d_mux[] = {
2952 MSIOF2_SS1_D_MARK,
2953};
2954static const unsigned int msiof2_ss2_d_pins[] = {
2955 /* SS2 */
2956 RCAR_GP_PIN(0, 13),
2957};
2958static const unsigned int msiof2_ss2_d_mux[] = {
2959 MSIOF2_SS2_D_MARK,
2960};
2961static const unsigned int msiof2_txd_d_pins[] = {
2962 /* TXD */
2963 RCAR_GP_PIN(0, 11),
2964};
2965static const unsigned int msiof2_txd_d_mux[] = {
2966 MSIOF2_TXD_D_MARK,
2967};
2968static const unsigned int msiof2_rxd_d_pins[] = {
2969 /* RXD */
2970 RCAR_GP_PIN(0, 10),
2971};
2972static const unsigned int msiof2_rxd_d_mux[] = {
2973 MSIOF2_RXD_D_MARK,
2974};
2975/* - MSIOF3 ----------------------------------------------------------------- */
2976static const unsigned int msiof3_clk_a_pins[] = {
2977 /* SCK */
2978 RCAR_GP_PIN(0, 0),
2979};
2980static const unsigned int msiof3_clk_a_mux[] = {
2981 MSIOF3_SCK_A_MARK,
2982};
2983static const unsigned int msiof3_sync_a_pins[] = {
2984 /* SYNC */
2985 RCAR_GP_PIN(0, 1),
2986};
2987static const unsigned int msiof3_sync_a_mux[] = {
2988 MSIOF3_SYNC_A_MARK,
2989};
2990static const unsigned int msiof3_ss1_a_pins[] = {
2991 /* SS1 */
2992 RCAR_GP_PIN(0, 14),
2993};
2994static const unsigned int msiof3_ss1_a_mux[] = {
2995 MSIOF3_SS1_A_MARK,
2996};
2997static const unsigned int msiof3_ss2_a_pins[] = {
2998 /* SS2 */
2999 RCAR_GP_PIN(0, 15),
3000};
3001static const unsigned int msiof3_ss2_a_mux[] = {
3002 MSIOF3_SS2_A_MARK,
3003};
3004static const unsigned int msiof3_txd_a_pins[] = {
3005 /* TXD */
3006 RCAR_GP_PIN(0, 3),
3007};
3008static const unsigned int msiof3_txd_a_mux[] = {
3009 MSIOF3_TXD_A_MARK,
3010};
3011static const unsigned int msiof3_rxd_a_pins[] = {
3012 /* RXD */
3013 RCAR_GP_PIN(0, 2),
3014};
3015static const unsigned int msiof3_rxd_a_mux[] = {
3016 MSIOF3_RXD_A_MARK,
3017};
3018static const unsigned int msiof3_clk_b_pins[] = {
3019 /* SCK */
3020 RCAR_GP_PIN(1, 2),
3021};
3022static const unsigned int msiof3_clk_b_mux[] = {
3023 MSIOF3_SCK_B_MARK,
3024};
3025static const unsigned int msiof3_sync_b_pins[] = {
3026 /* SYNC */
3027 RCAR_GP_PIN(1, 0),
3028};
3029static const unsigned int msiof3_sync_b_mux[] = {
3030 MSIOF3_SYNC_B_MARK,
3031};
3032static const unsigned int msiof3_ss1_b_pins[] = {
3033 /* SS1 */
3034 RCAR_GP_PIN(1, 4),
3035};
3036static const unsigned int msiof3_ss1_b_mux[] = {
3037 MSIOF3_SS1_B_MARK,
3038};
3039static const unsigned int msiof3_ss2_b_pins[] = {
3040 /* SS2 */
3041 RCAR_GP_PIN(1, 5),
3042};
3043static const unsigned int msiof3_ss2_b_mux[] = {
3044 MSIOF3_SS2_B_MARK,
3045};
3046static const unsigned int msiof3_txd_b_pins[] = {
3047 /* TXD */
3048 RCAR_GP_PIN(1, 1),
3049};
3050static const unsigned int msiof3_txd_b_mux[] = {
3051 MSIOF3_TXD_B_MARK,
3052};
3053static const unsigned int msiof3_rxd_b_pins[] = {
3054 /* RXD */
3055 RCAR_GP_PIN(1, 3),
3056};
3057static const unsigned int msiof3_rxd_b_mux[] = {
3058 MSIOF3_RXD_B_MARK,
3059};
3060static const unsigned int msiof3_clk_c_pins[] = {
3061 /* SCK */
3062 RCAR_GP_PIN(1, 12),
3063};
3064static const unsigned int msiof3_clk_c_mux[] = {
3065 MSIOF3_SCK_C_MARK,
3066};
3067static const unsigned int msiof3_sync_c_pins[] = {
3068 /* SYNC */
3069 RCAR_GP_PIN(1, 13),
3070};
3071static const unsigned int msiof3_sync_c_mux[] = {
3072 MSIOF3_SYNC_C_MARK,
3073};
3074static const unsigned int msiof3_txd_c_pins[] = {
3075 /* TXD */
3076 RCAR_GP_PIN(1, 15),
3077};
3078static const unsigned int msiof3_txd_c_mux[] = {
3079 MSIOF3_TXD_C_MARK,
3080};
3081static const unsigned int msiof3_rxd_c_pins[] = {
3082 /* RXD */
3083 RCAR_GP_PIN(1, 14),
3084};
3085static const unsigned int msiof3_rxd_c_mux[] = {
3086 MSIOF3_RXD_C_MARK,
3087};
3088static const unsigned int msiof3_clk_d_pins[] = {
3089 /* SCK */
3090 RCAR_GP_PIN(1, 22),
3091};
3092static const unsigned int msiof3_clk_d_mux[] = {
3093 MSIOF3_SCK_D_MARK,
3094};
3095static const unsigned int msiof3_sync_d_pins[] = {
3096 /* SYNC */
3097 RCAR_GP_PIN(1, 23),
3098};
3099static const unsigned int msiof3_sync_d_mux[] = {
3100 MSIOF3_SYNC_D_MARK,
3101};
3102static const unsigned int msiof3_ss1_d_pins[] = {
3103 /* SS1 */
3104 RCAR_GP_PIN(1, 26),
3105};
3106static const unsigned int msiof3_ss1_d_mux[] = {
3107 MSIOF3_SS1_D_MARK,
3108};
3109static const unsigned int msiof3_txd_d_pins[] = {
3110 /* TXD */
3111 RCAR_GP_PIN(1, 25),
3112};
3113static const unsigned int msiof3_txd_d_mux[] = {
3114 MSIOF3_TXD_D_MARK,
3115};
3116static const unsigned int msiof3_rxd_d_pins[] = {
3117 /* RXD */
3118 RCAR_GP_PIN(1, 24),
3119};
3120static const unsigned int msiof3_rxd_d_mux[] = {
3121 MSIOF3_RXD_D_MARK,
3122};
3123
3124static const unsigned int msiof3_clk_e_pins[] = {
3125 /* SCK */
3126 RCAR_GP_PIN(2, 3),
3127};
3128static const unsigned int msiof3_clk_e_mux[] = {
3129 MSIOF3_SCK_E_MARK,
3130};
3131static const unsigned int msiof3_sync_e_pins[] = {
3132 /* SYNC */
3133 RCAR_GP_PIN(2, 2),
3134};
3135static const unsigned int msiof3_sync_e_mux[] = {
3136 MSIOF3_SYNC_E_MARK,
3137};
3138static const unsigned int msiof3_ss1_e_pins[] = {
3139 /* SS1 */
3140 RCAR_GP_PIN(2, 1),
3141};
3142static const unsigned int msiof3_ss1_e_mux[] = {
3143 MSIOF3_SS1_E_MARK,
3144};
3145static const unsigned int msiof3_ss2_e_pins[] = {
3146 /* SS2 */
3147 RCAR_GP_PIN(2, 0),
3148};
3149static const unsigned int msiof3_ss2_e_mux[] = {
3150 MSIOF3_SS2_E_MARK,
3151};
3152static const unsigned int msiof3_txd_e_pins[] = {
3153 /* TXD */
3154 RCAR_GP_PIN(2, 5),
3155};
3156static const unsigned int msiof3_txd_e_mux[] = {
3157 MSIOF3_TXD_E_MARK,
3158};
3159static const unsigned int msiof3_rxd_e_pins[] = {
3160 /* RXD */
3161 RCAR_GP_PIN(2, 4),
3162};
3163static const unsigned int msiof3_rxd_e_mux[] = {
3164 MSIOF3_RXD_E_MARK,
3165};
3166
3167/* - PWM0 --------------------------------------------------------------------*/
3168static const unsigned int pwm0_pins[] = {
3169 /* PWM */
3170 RCAR_GP_PIN(2, 6),
3171};
3172static const unsigned int pwm0_mux[] = {
3173 PWM0_MARK,
3174};
3175/* - PWM1 --------------------------------------------------------------------*/
3176static const unsigned int pwm1_a_pins[] = {
3177 /* PWM */
3178 RCAR_GP_PIN(2, 7),
3179};
3180static const unsigned int pwm1_a_mux[] = {
3181 PWM1_A_MARK,
3182};
3183static const unsigned int pwm1_b_pins[] = {
3184 /* PWM */
3185 RCAR_GP_PIN(1, 8),
3186};
3187static const unsigned int pwm1_b_mux[] = {
3188 PWM1_B_MARK,
3189};
3190/* - PWM2 --------------------------------------------------------------------*/
3191static const unsigned int pwm2_a_pins[] = {
3192 /* PWM */
3193 RCAR_GP_PIN(2, 8),
3194};
3195static const unsigned int pwm2_a_mux[] = {
3196 PWM2_A_MARK,
3197};
3198static const unsigned int pwm2_b_pins[] = {
3199 /* PWM */
3200 RCAR_GP_PIN(1, 11),
3201};
3202static const unsigned int pwm2_b_mux[] = {
3203 PWM2_B_MARK,
3204};
3205/* - PWM3 --------------------------------------------------------------------*/
3206static const unsigned int pwm3_a_pins[] = {
3207 /* PWM */
3208 RCAR_GP_PIN(1, 0),
3209};
3210static const unsigned int pwm3_a_mux[] = {
3211 PWM3_A_MARK,
3212};
3213static const unsigned int pwm3_b_pins[] = {
3214 /* PWM */
3215 RCAR_GP_PIN(2, 2),
3216};
3217static const unsigned int pwm3_b_mux[] = {
3218 PWM3_B_MARK,
3219};
3220/* - PWM4 --------------------------------------------------------------------*/
3221static const unsigned int pwm4_a_pins[] = {
3222 /* PWM */
3223 RCAR_GP_PIN(1, 1),
3224};
3225static const unsigned int pwm4_a_mux[] = {
3226 PWM4_A_MARK,
3227};
3228static const unsigned int pwm4_b_pins[] = {
3229 /* PWM */
3230 RCAR_GP_PIN(2, 3),
3231};
3232static const unsigned int pwm4_b_mux[] = {
3233 PWM4_B_MARK,
3234};
3235/* - PWM5 --------------------------------------------------------------------*/
3236static const unsigned int pwm5_a_pins[] = {
3237 /* PWM */
3238 RCAR_GP_PIN(1, 2),
3239};
3240static const unsigned int pwm5_a_mux[] = {
3241 PWM5_A_MARK,
3242};
3243static const unsigned int pwm5_b_pins[] = {
3244 /* PWM */
3245 RCAR_GP_PIN(2, 4),
3246};
3247static const unsigned int pwm5_b_mux[] = {
3248 PWM5_B_MARK,
3249};
3250/* - PWM6 --------------------------------------------------------------------*/
3251static const unsigned int pwm6_a_pins[] = {
3252 /* PWM */
3253 RCAR_GP_PIN(1, 3),
3254};
3255static const unsigned int pwm6_a_mux[] = {
3256 PWM6_A_MARK,
3257};
3258static const unsigned int pwm6_b_pins[] = {
3259 /* PWM */
3260 RCAR_GP_PIN(2, 5),
3261};
3262static const unsigned int pwm6_b_mux[] = {
3263 PWM6_B_MARK,
3264};
3265
3266/* - SCIF0 ------------------------------------------------------------------ */
3267static const unsigned int scif0_data_pins[] = {
3268 /* RX, TX */
3269 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3270};
3271static const unsigned int scif0_data_mux[] = {
3272 RX0_MARK, TX0_MARK,
3273};
3274static const unsigned int scif0_clk_pins[] = {
3275 /* SCK */
3276 RCAR_GP_PIN(5, 0),
3277};
3278static const unsigned int scif0_clk_mux[] = {
3279 SCK0_MARK,
3280};
3281static const unsigned int scif0_ctrl_pins[] = {
3282 /* RTS, CTS */
3283 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3284};
3285static const unsigned int scif0_ctrl_mux[] = {
3286 RTS0_N_MARK, CTS0_N_MARK,
3287};
3288/* - SCIF1 ------------------------------------------------------------------ */
3289static const unsigned int scif1_data_a_pins[] = {
3290 /* RX, TX */
3291 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3292};
3293static const unsigned int scif1_data_a_mux[] = {
3294 RX1_A_MARK, TX1_A_MARK,
3295};
3296static const unsigned int scif1_clk_pins[] = {
3297 /* SCK */
3298 RCAR_GP_PIN(6, 21),
3299};
3300static const unsigned int scif1_clk_mux[] = {
3301 SCK1_MARK,
3302};
3303static const unsigned int scif1_ctrl_pins[] = {
3304 /* RTS, CTS */
3305 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3306};
3307static const unsigned int scif1_ctrl_mux[] = {
3308 RTS1_N_MARK, CTS1_N_MARK,
3309};
3310
3311static const unsigned int scif1_data_b_pins[] = {
3312 /* RX, TX */
3313 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3314};
3315static const unsigned int scif1_data_b_mux[] = {
3316 RX1_B_MARK, TX1_B_MARK,
3317};
3318/* - SCIF2 ------------------------------------------------------------------ */
3319static const unsigned int scif2_data_a_pins[] = {
3320 /* RX, TX */
3321 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3322};
3323static const unsigned int scif2_data_a_mux[] = {
3324 RX2_A_MARK, TX2_A_MARK,
3325};
3326static const unsigned int scif2_clk_pins[] = {
3327 /* SCK */
3328 RCAR_GP_PIN(5, 9),
3329};
3330static const unsigned int scif2_clk_mux[] = {
3331 SCK2_MARK,
3332};
3333static const unsigned int scif2_data_b_pins[] = {
3334 /* RX, TX */
3335 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3336};
3337static const unsigned int scif2_data_b_mux[] = {
3338 RX2_B_MARK, TX2_B_MARK,
3339};
3340/* - SCIF3 ------------------------------------------------------------------ */
3341static const unsigned int scif3_data_a_pins[] = {
3342 /* RX, TX */
3343 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3344};
3345static const unsigned int scif3_data_a_mux[] = {
3346 RX3_A_MARK, TX3_A_MARK,
3347};
3348static const unsigned int scif3_clk_pins[] = {
3349 /* SCK */
3350 RCAR_GP_PIN(1, 22),
3351};
3352static const unsigned int scif3_clk_mux[] = {
3353 SCK3_MARK,
3354};
3355static const unsigned int scif3_ctrl_pins[] = {
3356 /* RTS, CTS */
3357 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3358};
3359static const unsigned int scif3_ctrl_mux[] = {
3360 RTS3_N_MARK, CTS3_N_MARK,
3361};
3362static const unsigned int scif3_data_b_pins[] = {
3363 /* RX, TX */
3364 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3365};
3366static const unsigned int scif3_data_b_mux[] = {
3367 RX3_B_MARK, TX3_B_MARK,
3368};
3369/* - SCIF4 ------------------------------------------------------------------ */
3370static const unsigned int scif4_data_a_pins[] = {
3371 /* RX, TX */
3372 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3373};
3374static const unsigned int scif4_data_a_mux[] = {
3375 RX4_A_MARK, TX4_A_MARK,
3376};
3377static const unsigned int scif4_clk_a_pins[] = {
3378 /* SCK */
3379 RCAR_GP_PIN(2, 10),
3380};
3381static const unsigned int scif4_clk_a_mux[] = {
3382 SCK4_A_MARK,
3383};
3384static const unsigned int scif4_ctrl_a_pins[] = {
3385 /* RTS, CTS */
3386 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3387};
3388static const unsigned int scif4_ctrl_a_mux[] = {
3389 RTS4_N_A_MARK, CTS4_N_A_MARK,
3390};
3391static const unsigned int scif4_data_b_pins[] = {
3392 /* RX, TX */
3393 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3394};
3395static const unsigned int scif4_data_b_mux[] = {
3396 RX4_B_MARK, TX4_B_MARK,
3397};
3398static const unsigned int scif4_clk_b_pins[] = {
3399 /* SCK */
3400 RCAR_GP_PIN(1, 5),
3401};
3402static const unsigned int scif4_clk_b_mux[] = {
3403 SCK4_B_MARK,
3404};
3405static const unsigned int scif4_ctrl_b_pins[] = {
3406 /* RTS, CTS */
3407 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3408};
3409static const unsigned int scif4_ctrl_b_mux[] = {
3410 RTS4_N_B_MARK, CTS4_N_B_MARK,
3411};
3412static const unsigned int scif4_data_c_pins[] = {
3413 /* RX, TX */
3414 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3415};
3416static const unsigned int scif4_data_c_mux[] = {
3417 RX4_C_MARK, TX4_C_MARK,
3418};
3419static const unsigned int scif4_clk_c_pins[] = {
3420 /* SCK */
3421 RCAR_GP_PIN(0, 8),
3422};
3423static const unsigned int scif4_clk_c_mux[] = {
3424 SCK4_C_MARK,
3425};
3426static const unsigned int scif4_ctrl_c_pins[] = {
3427 /* RTS, CTS */
3428 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3429};
3430static const unsigned int scif4_ctrl_c_mux[] = {
3431 RTS4_N_C_MARK, CTS4_N_C_MARK,
3432};
3433/* - SCIF5 ------------------------------------------------------------------ */
3434static const unsigned int scif5_data_a_pins[] = {
3435 /* RX, TX */
3436 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3437};
3438static const unsigned int scif5_data_a_mux[] = {
3439 RX5_A_MARK, TX5_A_MARK,
3440};
3441static const unsigned int scif5_clk_a_pins[] = {
3442 /* SCK */
3443 RCAR_GP_PIN(6, 21),
3444};
3445static const unsigned int scif5_clk_a_mux[] = {
3446 SCK5_A_MARK,
3447};
3448
3449static const unsigned int scif5_data_b_pins[] = {
3450 /* RX, TX */
3451 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3452};
3453static const unsigned int scif5_data_b_mux[] = {
3454 RX5_B_MARK, TX5_B_MARK,
3455};
3456static const unsigned int scif5_clk_b_pins[] = {
3457 /* SCK */
3458 RCAR_GP_PIN(5, 0),
3459};
3460static const unsigned int scif5_clk_b_mux[] = {
3461 SCK5_B_MARK,
3462};
3463
3464/* - SCIF Clock ------------------------------------------------------------- */
3465static const unsigned int scif_clk_a_pins[] = {
3466 /* SCIF_CLK */
3467 RCAR_GP_PIN(6, 23),
3468};
3469static const unsigned int scif_clk_a_mux[] = {
3470 SCIF_CLK_A_MARK,
3471};
3472static const unsigned int scif_clk_b_pins[] = {
3473 /* SCIF_CLK */
3474 RCAR_GP_PIN(5, 9),
3475};
3476static const unsigned int scif_clk_b_mux[] = {
3477 SCIF_CLK_B_MARK,
3478};
3479
3480/* - SDHI0 ------------------------------------------------------------------ */
3481static const unsigned int sdhi0_data1_pins[] = {
3482 /* D0 */
3483 RCAR_GP_PIN(3, 2),
3484};
3485static const unsigned int sdhi0_data1_mux[] = {
3486 SD0_DAT0_MARK,
3487};
3488static const unsigned int sdhi0_data4_pins[] = {
3489 /* D[0:3] */
3490 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3491 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3492};
3493static const unsigned int sdhi0_data4_mux[] = {
3494 SD0_DAT0_MARK, SD0_DAT1_MARK,
3495 SD0_DAT2_MARK, SD0_DAT3_MARK,
3496};
3497static const unsigned int sdhi0_ctrl_pins[] = {
3498 /* CLK, CMD */
3499 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3500};
3501static const unsigned int sdhi0_ctrl_mux[] = {
3502 SD0_CLK_MARK, SD0_CMD_MARK,
3503};
3504static const unsigned int sdhi0_cd_pins[] = {
3505 /* CD */
3506 RCAR_GP_PIN(3, 12),
3507};
3508static const unsigned int sdhi0_cd_mux[] = {
3509 SD0_CD_MARK,
3510};
3511static const unsigned int sdhi0_wp_pins[] = {
3512 /* WP */
3513 RCAR_GP_PIN(3, 13),
3514};
3515static const unsigned int sdhi0_wp_mux[] = {
3516 SD0_WP_MARK,
3517};
3518/* - SDHI1 ------------------------------------------------------------------ */
3519static const unsigned int sdhi1_data1_pins[] = {
3520 /* D0 */
3521 RCAR_GP_PIN(3, 8),
3522};
3523static const unsigned int sdhi1_data1_mux[] = {
3524 SD1_DAT0_MARK,
3525};
3526static const unsigned int sdhi1_data4_pins[] = {
3527 /* D[0:3] */
3528 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3529 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3530};
3531static const unsigned int sdhi1_data4_mux[] = {
3532 SD1_DAT0_MARK, SD1_DAT1_MARK,
3533 SD1_DAT2_MARK, SD1_DAT3_MARK,
3534};
3535static const unsigned int sdhi1_ctrl_pins[] = {
3536 /* CLK, CMD */
3537 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3538};
3539static const unsigned int sdhi1_ctrl_mux[] = {
3540 SD1_CLK_MARK, SD1_CMD_MARK,
3541};
3542static const unsigned int sdhi1_cd_pins[] = {
3543 /* CD */
3544 RCAR_GP_PIN(3, 14),
3545};
3546static const unsigned int sdhi1_cd_mux[] = {
3547 SD1_CD_MARK,
3548};
3549static const unsigned int sdhi1_wp_pins[] = {
3550 /* WP */
3551 RCAR_GP_PIN(3, 15),
3552};
3553static const unsigned int sdhi1_wp_mux[] = {
3554 SD1_WP_MARK,
3555};
3556/* - SDHI2 ------------------------------------------------------------------ */
3557static const unsigned int sdhi2_data1_pins[] = {
3558 /* D0 */
3559 RCAR_GP_PIN(4, 2),
3560};
3561static const unsigned int sdhi2_data1_mux[] = {
3562 SD2_DAT0_MARK,
3563};
3564static const unsigned int sdhi2_data4_pins[] = {
3565 /* D[0:3] */
3566 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3567 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3568};
3569static const unsigned int sdhi2_data4_mux[] = {
3570 SD2_DAT0_MARK, SD2_DAT1_MARK,
3571 SD2_DAT2_MARK, SD2_DAT3_MARK,
3572};
3573static const unsigned int sdhi2_data8_pins[] = {
3574 /* D[0:7] */
3575 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3576 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3577 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3578 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3579};
3580static const unsigned int sdhi2_data8_mux[] = {
3581 SD2_DAT0_MARK, SD2_DAT1_MARK,
3582 SD2_DAT2_MARK, SD2_DAT3_MARK,
3583 SD2_DAT4_MARK, SD2_DAT5_MARK,
3584 SD2_DAT6_MARK, SD2_DAT7_MARK,
3585};
3586static const unsigned int sdhi2_ctrl_pins[] = {
3587 /* CLK, CMD */
3588 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3589};
3590static const unsigned int sdhi2_ctrl_mux[] = {
3591 SD2_CLK_MARK, SD2_CMD_MARK,
3592};
3593static const unsigned int sdhi2_cd_a_pins[] = {
3594 /* CD */
3595 RCAR_GP_PIN(4, 13),
3596};
3597static const unsigned int sdhi2_cd_a_mux[] = {
3598 SD2_CD_A_MARK,
3599};
3600static const unsigned int sdhi2_cd_b_pins[] = {
3601 /* CD */
3602 RCAR_GP_PIN(5, 10),
3603};
3604static const unsigned int sdhi2_cd_b_mux[] = {
3605 SD2_CD_B_MARK,
3606};
3607static const unsigned int sdhi2_wp_a_pins[] = {
3608 /* WP */
3609 RCAR_GP_PIN(4, 14),
3610};
3611static const unsigned int sdhi2_wp_a_mux[] = {
3612 SD2_WP_A_MARK,
3613};
3614static const unsigned int sdhi2_wp_b_pins[] = {
3615 /* WP */
3616 RCAR_GP_PIN(5, 11),
3617};
3618static const unsigned int sdhi2_wp_b_mux[] = {
3619 SD2_WP_B_MARK,
3620};
3621static const unsigned int sdhi2_ds_pins[] = {
3622 /* DS */
3623 RCAR_GP_PIN(4, 6),
3624};
3625static const unsigned int sdhi2_ds_mux[] = {
3626 SD2_DS_MARK,
3627};
3628/* - SDHI3 ------------------------------------------------------------------ */
3629static const unsigned int sdhi3_data1_pins[] = {
3630 /* D0 */
3631 RCAR_GP_PIN(4, 9),
3632};
3633static const unsigned int sdhi3_data1_mux[] = {
3634 SD3_DAT0_MARK,
3635};
3636static const unsigned int sdhi3_data4_pins[] = {
3637 /* D[0:3] */
3638 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3639 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3640};
3641static const unsigned int sdhi3_data4_mux[] = {
3642 SD3_DAT0_MARK, SD3_DAT1_MARK,
3643 SD3_DAT2_MARK, SD3_DAT3_MARK,
3644};
3645static const unsigned int sdhi3_data8_pins[] = {
3646 /* D[0:7] */
3647 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3648 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3649 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3650 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3651};
3652static const unsigned int sdhi3_data8_mux[] = {
3653 SD3_DAT0_MARK, SD3_DAT1_MARK,
3654 SD3_DAT2_MARK, SD3_DAT3_MARK,
3655 SD3_DAT4_MARK, SD3_DAT5_MARK,
3656 SD3_DAT6_MARK, SD3_DAT7_MARK,
3657};
3658static const unsigned int sdhi3_ctrl_pins[] = {
3659 /* CLK, CMD */
3660 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3661};
3662static const unsigned int sdhi3_ctrl_mux[] = {
3663 SD3_CLK_MARK, SD3_CMD_MARK,
3664};
3665static const unsigned int sdhi3_cd_pins[] = {
3666 /* CD */
3667 RCAR_GP_PIN(4, 15),
3668};
3669static const unsigned int sdhi3_cd_mux[] = {
3670 SD3_CD_MARK,
3671};
3672static const unsigned int sdhi3_wp_pins[] = {
3673 /* WP */
3674 RCAR_GP_PIN(4, 16),
3675};
3676static const unsigned int sdhi3_wp_mux[] = {
3677 SD3_WP_MARK,
3678};
3679static const unsigned int sdhi3_ds_pins[] = {
3680 /* DS */
3681 RCAR_GP_PIN(4, 17),
3682};
3683static const unsigned int sdhi3_ds_mux[] = {
3684 SD3_DS_MARK,
3685};
3686
3687/* - SSI -------------------------------------------------------------------- */
3688static const unsigned int ssi0_data_pins[] = {
3689 /* SDATA */
3690 RCAR_GP_PIN(6, 2),
3691};
3692static const unsigned int ssi0_data_mux[] = {
3693 SSI_SDATA0_MARK,
3694};
3695static const unsigned int ssi01239_ctrl_pins[] = {
3696 /* SCK, WS */
3697 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3698};
3699static const unsigned int ssi01239_ctrl_mux[] = {
3700 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3701};
3702static const unsigned int ssi1_data_a_pins[] = {
3703 /* SDATA */
3704 RCAR_GP_PIN(6, 3),
3705};
3706static const unsigned int ssi1_data_a_mux[] = {
3707 SSI_SDATA1_A_MARK,
3708};
3709static const unsigned int ssi1_data_b_pins[] = {
3710 /* SDATA */
3711 RCAR_GP_PIN(5, 12),
3712};
3713static const unsigned int ssi1_data_b_mux[] = {
3714 SSI_SDATA1_B_MARK,
3715};
3716static const unsigned int ssi1_ctrl_a_pins[] = {
3717 /* SCK, WS */
3718 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3719};
3720static const unsigned int ssi1_ctrl_a_mux[] = {
3721 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3722};
3723static const unsigned int ssi1_ctrl_b_pins[] = {
3724 /* SCK, WS */
3725 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3726};
3727static const unsigned int ssi1_ctrl_b_mux[] = {
3728 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3729};
3730static const unsigned int ssi2_data_a_pins[] = {
3731 /* SDATA */
3732 RCAR_GP_PIN(6, 4),
3733};
3734static const unsigned int ssi2_data_a_mux[] = {
3735 SSI_SDATA2_A_MARK,
3736};
3737static const unsigned int ssi2_data_b_pins[] = {
3738 /* SDATA */
3739 RCAR_GP_PIN(5, 13),
3740};
3741static const unsigned int ssi2_data_b_mux[] = {
3742 SSI_SDATA2_B_MARK,
3743};
3744static const unsigned int ssi2_ctrl_a_pins[] = {
3745 /* SCK, WS */
3746 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3747};
3748static const unsigned int ssi2_ctrl_a_mux[] = {
3749 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3750};
3751static const unsigned int ssi2_ctrl_b_pins[] = {
3752 /* SCK, WS */
3753 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3754};
3755static const unsigned int ssi2_ctrl_b_mux[] = {
3756 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3757};
3758static const unsigned int ssi3_data_pins[] = {
3759 /* SDATA */
3760 RCAR_GP_PIN(6, 7),
3761};
3762static const unsigned int ssi3_data_mux[] = {
3763 SSI_SDATA3_MARK,
3764};
3765static const unsigned int ssi349_ctrl_pins[] = {
3766 /* SCK, WS */
3767 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3768};
3769static const unsigned int ssi349_ctrl_mux[] = {
3770 SSI_SCK349_MARK, SSI_WS349_MARK,
3771};
3772static const unsigned int ssi4_data_pins[] = {
3773 /* SDATA */
3774 RCAR_GP_PIN(6, 10),
3775};
3776static const unsigned int ssi4_data_mux[] = {
3777 SSI_SDATA4_MARK,
3778};
3779static const unsigned int ssi4_ctrl_pins[] = {
3780 /* SCK, WS */
3781 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3782};
3783static const unsigned int ssi4_ctrl_mux[] = {
3784 SSI_SCK4_MARK, SSI_WS4_MARK,
3785};
3786static const unsigned int ssi5_data_pins[] = {
3787 /* SDATA */
3788 RCAR_GP_PIN(6, 13),
3789};
3790static const unsigned int ssi5_data_mux[] = {
3791 SSI_SDATA5_MARK,
3792};
3793static const unsigned int ssi5_ctrl_pins[] = {
3794 /* SCK, WS */
3795 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3796};
3797static const unsigned int ssi5_ctrl_mux[] = {
3798 SSI_SCK5_MARK, SSI_WS5_MARK,
3799};
3800static const unsigned int ssi6_data_pins[] = {
3801 /* SDATA */
3802 RCAR_GP_PIN(6, 16),
3803};
3804static const unsigned int ssi6_data_mux[] = {
3805 SSI_SDATA6_MARK,
3806};
3807static const unsigned int ssi6_ctrl_pins[] = {
3808 /* SCK, WS */
3809 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3810};
3811static const unsigned int ssi6_ctrl_mux[] = {
3812 SSI_SCK6_MARK, SSI_WS6_MARK,
3813};
3814static const unsigned int ssi7_data_pins[] = {
3815 /* SDATA */
3816 RCAR_GP_PIN(6, 19),
3817};
3818static const unsigned int ssi7_data_mux[] = {
3819 SSI_SDATA7_MARK,
3820};
3821static const unsigned int ssi78_ctrl_pins[] = {
3822 /* SCK, WS */
3823 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3824};
3825static const unsigned int ssi78_ctrl_mux[] = {
3826 SSI_SCK78_MARK, SSI_WS78_MARK,
3827};
3828static const unsigned int ssi8_data_pins[] = {
3829 /* SDATA */
3830 RCAR_GP_PIN(6, 20),
3831};
3832static const unsigned int ssi8_data_mux[] = {
3833 SSI_SDATA8_MARK,
3834};
3835static const unsigned int ssi9_data_a_pins[] = {
3836 /* SDATA */
3837 RCAR_GP_PIN(6, 21),
3838};
3839static const unsigned int ssi9_data_a_mux[] = {
3840 SSI_SDATA9_A_MARK,
3841};
3842static const unsigned int ssi9_data_b_pins[] = {
3843 /* SDATA */
3844 RCAR_GP_PIN(5, 14),
3845};
3846static const unsigned int ssi9_data_b_mux[] = {
3847 SSI_SDATA9_B_MARK,
3848};
3849static const unsigned int ssi9_ctrl_a_pins[] = {
3850 /* SCK, WS */
3851 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3852};
3853static const unsigned int ssi9_ctrl_a_mux[] = {
3854 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3855};
3856static const unsigned int ssi9_ctrl_b_pins[] = {
3857 /* SCK, WS */
3858 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3859};
3860static const unsigned int ssi9_ctrl_b_mux[] = {
3861 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3862};
3863
3864/* - TMU -------------------------------------------------------------------- */
3865static const unsigned int tmu_tclk1_a_pins[] = {
3866 /* TCLK */
3867 RCAR_GP_PIN(6, 23),
3868};
3869static const unsigned int tmu_tclk1_a_mux[] = {
3870 TCLK1_A_MARK,
3871};
3872static const unsigned int tmu_tclk1_b_pins[] = {
3873 /* TCLK */
3874 RCAR_GP_PIN(5, 19),
3875};
3876static const unsigned int tmu_tclk1_b_mux[] = {
3877 TCLK1_B_MARK,
3878};
3879static const unsigned int tmu_tclk2_a_pins[] = {
3880 /* TCLK */
3881 RCAR_GP_PIN(6, 19),
3882};
3883static const unsigned int tmu_tclk2_a_mux[] = {
3884 TCLK2_A_MARK,
3885};
3886static const unsigned int tmu_tclk2_b_pins[] = {
3887 /* TCLK */
3888 RCAR_GP_PIN(6, 28),
3889};
3890static const unsigned int tmu_tclk2_b_mux[] = {
3891 TCLK2_B_MARK,
3892};
3893
3894/* - USB0 ------------------------------------------------------------------- */
3895static const unsigned int usb0_pins[] = {
3896 /* PWEN, OVC */
3897 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3898};
3899static const unsigned int usb0_mux[] = {
3900 USB0_PWEN_MARK, USB0_OVC_MARK,
3901};
3902/* - USB1 ------------------------------------------------------------------- */
3903static const unsigned int usb1_pins[] = {
3904 /* PWEN, OVC */
3905 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3906};
3907static const unsigned int usb1_mux[] = {
3908 USB1_PWEN_MARK, USB1_OVC_MARK,
3909};
3910
3911/* - USB30 ------------------------------------------------------------------ */
3912static const unsigned int usb30_pins[] = {
3913 /* PWEN, OVC */
3914 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3915};
3916static const unsigned int usb30_mux[] = {
3917 USB30_PWEN_MARK, USB30_OVC_MARK,
3918};
3919
3920/* - VIN4 ------------------------------------------------------------------- */
3921static const unsigned int vin4_data18_a_pins[] = {
3922 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3923 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3924 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3925 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3926 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3927 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3928 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3929 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3930 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3931};
3932static const unsigned int vin4_data18_a_mux[] = {
3933 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3934 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3935 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3936 VI4_DATA10_MARK, VI4_DATA11_MARK,
3937 VI4_DATA12_MARK, VI4_DATA13_MARK,
3938 VI4_DATA14_MARK, VI4_DATA15_MARK,
3939 VI4_DATA18_MARK, VI4_DATA19_MARK,
3940 VI4_DATA20_MARK, VI4_DATA21_MARK,
3941 VI4_DATA22_MARK, VI4_DATA23_MARK,
3942};
3943static const unsigned int vin4_data18_b_pins[] = {
3944 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3945 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3946 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3947 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3948 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3949 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3950 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3951 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3952 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3953};
3954static const unsigned int vin4_data18_b_mux[] = {
3955 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3956 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3957 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3958 VI4_DATA10_MARK, VI4_DATA11_MARK,
3959 VI4_DATA12_MARK, VI4_DATA13_MARK,
3960 VI4_DATA14_MARK, VI4_DATA15_MARK,
3961 VI4_DATA18_MARK, VI4_DATA19_MARK,
3962 VI4_DATA20_MARK, VI4_DATA21_MARK,
3963 VI4_DATA22_MARK, VI4_DATA23_MARK,
3964};
3965static const union vin_data vin4_data_a_pins = {
3966 .data24 = {
3967 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3968 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3969 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3970 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3971 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3972 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3973 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3974 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3975 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3976 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3977 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3978 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3979 },
3980};
3981static const union vin_data vin4_data_a_mux = {
3982 .data24 = {
3983 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3984 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3985 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3986 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3987 VI4_DATA8_MARK, VI4_DATA9_MARK,
3988 VI4_DATA10_MARK, VI4_DATA11_MARK,
3989 VI4_DATA12_MARK, VI4_DATA13_MARK,
3990 VI4_DATA14_MARK, VI4_DATA15_MARK,
3991 VI4_DATA16_MARK, VI4_DATA17_MARK,
3992 VI4_DATA18_MARK, VI4_DATA19_MARK,
3993 VI4_DATA20_MARK, VI4_DATA21_MARK,
3994 VI4_DATA22_MARK, VI4_DATA23_MARK,
3995 },
3996};
3997static const union vin_data vin4_data_b_pins = {
3998 .data24 = {
3999 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4000 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4001 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4002 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4003 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4004 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4005 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4006 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4007 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4008 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4009 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4010 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4011 },
4012};
4013static const union vin_data vin4_data_b_mux = {
4014 .data24 = {
4015 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4016 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4017 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4018 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4019 VI4_DATA8_MARK, VI4_DATA9_MARK,
4020 VI4_DATA10_MARK, VI4_DATA11_MARK,
4021 VI4_DATA12_MARK, VI4_DATA13_MARK,
4022 VI4_DATA14_MARK, VI4_DATA15_MARK,
4023 VI4_DATA16_MARK, VI4_DATA17_MARK,
4024 VI4_DATA18_MARK, VI4_DATA19_MARK,
4025 VI4_DATA20_MARK, VI4_DATA21_MARK,
4026 VI4_DATA22_MARK, VI4_DATA23_MARK,
4027 },
4028};
4029static const unsigned int vin4_sync_pins[] = {
4030 /* HSYNC#, VSYNC# */
4031 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4032};
4033static const unsigned int vin4_sync_mux[] = {
4034 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4035};
4036static const unsigned int vin4_field_pins[] = {
4037 /* FIELD */
4038 RCAR_GP_PIN(1, 16),
4039};
4040static const unsigned int vin4_field_mux[] = {
4041 VI4_FIELD_MARK,
4042};
4043static const unsigned int vin4_clkenb_pins[] = {
4044 /* CLKENB */
4045 RCAR_GP_PIN(1, 19),
4046};
4047static const unsigned int vin4_clkenb_mux[] = {
4048 VI4_CLKENB_MARK,
4049};
4050static const unsigned int vin4_clk_pins[] = {
4051 /* CLK */
4052 RCAR_GP_PIN(1, 27),
4053};
4054static const unsigned int vin4_clk_mux[] = {
4055 VI4_CLK_MARK,
4056};
4057
4058/* - VIN5 ------------------------------------------------------------------- */
4059static const union vin_data16 vin5_data_pins = {
4060 .data16 = {
4061 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4062 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4063 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4064 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4065 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4066 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4067 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4068 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4069 },
4070};
4071static const union vin_data16 vin5_data_mux = {
4072 .data16 = {
4073 VI5_DATA0_MARK, VI5_DATA1_MARK,
4074 VI5_DATA2_MARK, VI5_DATA3_MARK,
4075 VI5_DATA4_MARK, VI5_DATA5_MARK,
4076 VI5_DATA6_MARK, VI5_DATA7_MARK,
4077 VI5_DATA8_MARK, VI5_DATA9_MARK,
4078 VI5_DATA10_MARK, VI5_DATA11_MARK,
4079 VI5_DATA12_MARK, VI5_DATA13_MARK,
4080 VI5_DATA14_MARK, VI5_DATA15_MARK,
4081 },
4082};
4083static const unsigned int vin5_sync_pins[] = {
4084 /* HSYNC#, VSYNC# */
4085 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4086};
4087static const unsigned int vin5_sync_mux[] = {
4088 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4089};
4090static const unsigned int vin5_field_pins[] = {
4091 RCAR_GP_PIN(1, 11),
4092};
4093static const unsigned int vin5_field_mux[] = {
4094 /* FIELD */
4095 VI5_FIELD_MARK,
4096};
4097static const unsigned int vin5_clkenb_pins[] = {
4098 RCAR_GP_PIN(1, 20),
4099};
4100static const unsigned int vin5_clkenb_mux[] = {
4101 /* CLKENB */
4102 VI5_CLKENB_MARK,
4103};
4104static const unsigned int vin5_clk_pins[] = {
4105 RCAR_GP_PIN(1, 21),
4106};
4107static const unsigned int vin5_clk_mux[] = {
4108 /* CLK */
4109 VI5_CLK_MARK,
4110};
4111
4112static const struct {
4113 struct sh_pfc_pin_group common[312];
4114 struct sh_pfc_pin_group automotive[30];
4115} pinmux_groups = {
4116 .common = {
4117 SH_PFC_PIN_GROUP(audio_clk_a_a),
4118 SH_PFC_PIN_GROUP(audio_clk_a_b),
4119 SH_PFC_PIN_GROUP(audio_clk_a_c),
4120 SH_PFC_PIN_GROUP(audio_clk_b_a),
4121 SH_PFC_PIN_GROUP(audio_clk_b_b),
4122 SH_PFC_PIN_GROUP(audio_clk_c_a),
4123 SH_PFC_PIN_GROUP(audio_clk_c_b),
4124 SH_PFC_PIN_GROUP(audio_clkout_a),
4125 SH_PFC_PIN_GROUP(audio_clkout_b),
4126 SH_PFC_PIN_GROUP(audio_clkout_c),
4127 SH_PFC_PIN_GROUP(audio_clkout_d),
4128 SH_PFC_PIN_GROUP(audio_clkout1_a),
4129 SH_PFC_PIN_GROUP(audio_clkout1_b),
4130 SH_PFC_PIN_GROUP(audio_clkout2_a),
4131 SH_PFC_PIN_GROUP(audio_clkout2_b),
4132 SH_PFC_PIN_GROUP(audio_clkout3_a),
4133 SH_PFC_PIN_GROUP(audio_clkout3_b),
4134 SH_PFC_PIN_GROUP(avb_link),
4135 SH_PFC_PIN_GROUP(avb_magic),
4136 SH_PFC_PIN_GROUP(avb_phy_int),
4137 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4138 SH_PFC_PIN_GROUP(avb_mdio),
4139 SH_PFC_PIN_GROUP(avb_mii),
4140 SH_PFC_PIN_GROUP(avb_avtp_pps),
4141 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4142 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4143 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4144 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4145 SH_PFC_PIN_GROUP(can0_data_a),
4146 SH_PFC_PIN_GROUP(can0_data_b),
4147 SH_PFC_PIN_GROUP(can1_data),
4148 SH_PFC_PIN_GROUP(can_clk),
4149 SH_PFC_PIN_GROUP(canfd0_data_a),
4150 SH_PFC_PIN_GROUP(canfd0_data_b),
4151 SH_PFC_PIN_GROUP(canfd1_data),
4152 SH_PFC_PIN_GROUP(du_rgb666),
4153 SH_PFC_PIN_GROUP(du_rgb888),
4154 SH_PFC_PIN_GROUP(du_clk_out_0),
4155 SH_PFC_PIN_GROUP(du_clk_out_1),
4156 SH_PFC_PIN_GROUP(du_sync),
4157 SH_PFC_PIN_GROUP(du_oddf),
4158 SH_PFC_PIN_GROUP(du_cde),
4159 SH_PFC_PIN_GROUP(du_disp),
4160 SH_PFC_PIN_GROUP(hscif0_data),
4161 SH_PFC_PIN_GROUP(hscif0_clk),
4162 SH_PFC_PIN_GROUP(hscif0_ctrl),
4163 SH_PFC_PIN_GROUP(hscif1_data_a),
4164 SH_PFC_PIN_GROUP(hscif1_clk_a),
4165 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4166 SH_PFC_PIN_GROUP(hscif1_data_b),
4167 SH_PFC_PIN_GROUP(hscif1_clk_b),
4168 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4169 SH_PFC_PIN_GROUP(hscif2_data_a),
4170 SH_PFC_PIN_GROUP(hscif2_clk_a),
4171 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4172 SH_PFC_PIN_GROUP(hscif2_data_b),
4173 SH_PFC_PIN_GROUP(hscif2_clk_b),
4174 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4175 SH_PFC_PIN_GROUP(hscif2_data_c),
4176 SH_PFC_PIN_GROUP(hscif2_clk_c),
4177 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4178 SH_PFC_PIN_GROUP(hscif3_data_a),
4179 SH_PFC_PIN_GROUP(hscif3_clk),
4180 SH_PFC_PIN_GROUP(hscif3_ctrl),
4181 SH_PFC_PIN_GROUP(hscif3_data_b),
4182 SH_PFC_PIN_GROUP(hscif3_data_c),
4183 SH_PFC_PIN_GROUP(hscif3_data_d),
4184 SH_PFC_PIN_GROUP(hscif4_data_a),
4185 SH_PFC_PIN_GROUP(hscif4_clk),
4186 SH_PFC_PIN_GROUP(hscif4_ctrl),
4187 SH_PFC_PIN_GROUP(hscif4_data_b),
4188 SH_PFC_PIN_GROUP(i2c0),
4189 SH_PFC_PIN_GROUP(i2c1_a),
4190 SH_PFC_PIN_GROUP(i2c1_b),
4191 SH_PFC_PIN_GROUP(i2c2_a),
4192 SH_PFC_PIN_GROUP(i2c2_b),
4193 SH_PFC_PIN_GROUP(i2c3),
4194 SH_PFC_PIN_GROUP(i2c5),
4195 SH_PFC_PIN_GROUP(i2c6_a),
4196 SH_PFC_PIN_GROUP(i2c6_b),
4197 SH_PFC_PIN_GROUP(i2c6_c),
4198 SH_PFC_PIN_GROUP(intc_ex_irq0),
4199 SH_PFC_PIN_GROUP(intc_ex_irq1),
4200 SH_PFC_PIN_GROUP(intc_ex_irq2),
4201 SH_PFC_PIN_GROUP(intc_ex_irq3),
4202 SH_PFC_PIN_GROUP(intc_ex_irq4),
4203 SH_PFC_PIN_GROUP(intc_ex_irq5),
4204 SH_PFC_PIN_GROUP(msiof0_clk),
4205 SH_PFC_PIN_GROUP(msiof0_sync),
4206 SH_PFC_PIN_GROUP(msiof0_ss1),
4207 SH_PFC_PIN_GROUP(msiof0_ss2),
4208 SH_PFC_PIN_GROUP(msiof0_txd),
4209 SH_PFC_PIN_GROUP(msiof0_rxd),
4210 SH_PFC_PIN_GROUP(msiof1_clk_a),
4211 SH_PFC_PIN_GROUP(msiof1_sync_a),
4212 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4213 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4214 SH_PFC_PIN_GROUP(msiof1_txd_a),
4215 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4216 SH_PFC_PIN_GROUP(msiof1_clk_b),
4217 SH_PFC_PIN_GROUP(msiof1_sync_b),
4218 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4219 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4220 SH_PFC_PIN_GROUP(msiof1_txd_b),
4221 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4222 SH_PFC_PIN_GROUP(msiof1_clk_c),
4223 SH_PFC_PIN_GROUP(msiof1_sync_c),
4224 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4225 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4226 SH_PFC_PIN_GROUP(msiof1_txd_c),
4227 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4228 SH_PFC_PIN_GROUP(msiof1_clk_d),
4229 SH_PFC_PIN_GROUP(msiof1_sync_d),
4230 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4231 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4232 SH_PFC_PIN_GROUP(msiof1_txd_d),
4233 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4234 SH_PFC_PIN_GROUP(msiof1_clk_e),
4235 SH_PFC_PIN_GROUP(msiof1_sync_e),
4236 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4237 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4238 SH_PFC_PIN_GROUP(msiof1_txd_e),
4239 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4240 SH_PFC_PIN_GROUP(msiof1_clk_f),
4241 SH_PFC_PIN_GROUP(msiof1_sync_f),
4242 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4243 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4244 SH_PFC_PIN_GROUP(msiof1_txd_f),
4245 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4246 SH_PFC_PIN_GROUP(msiof1_clk_g),
4247 SH_PFC_PIN_GROUP(msiof1_sync_g),
4248 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4249 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4250 SH_PFC_PIN_GROUP(msiof1_txd_g),
4251 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4252 SH_PFC_PIN_GROUP(msiof2_clk_a),
4253 SH_PFC_PIN_GROUP(msiof2_sync_a),
4254 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4255 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4256 SH_PFC_PIN_GROUP(msiof2_txd_a),
4257 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4258 SH_PFC_PIN_GROUP(msiof2_clk_b),
4259 SH_PFC_PIN_GROUP(msiof2_sync_b),
4260 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4261 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4262 SH_PFC_PIN_GROUP(msiof2_txd_b),
4263 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4264 SH_PFC_PIN_GROUP(msiof2_clk_c),
4265 SH_PFC_PIN_GROUP(msiof2_sync_c),
4266 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4267 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4268 SH_PFC_PIN_GROUP(msiof2_txd_c),
4269 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4270 SH_PFC_PIN_GROUP(msiof2_clk_d),
4271 SH_PFC_PIN_GROUP(msiof2_sync_d),
4272 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4273 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4274 SH_PFC_PIN_GROUP(msiof2_txd_d),
4275 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4276 SH_PFC_PIN_GROUP(msiof3_clk_a),
4277 SH_PFC_PIN_GROUP(msiof3_sync_a),
4278 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4279 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4280 SH_PFC_PIN_GROUP(msiof3_txd_a),
4281 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4282 SH_PFC_PIN_GROUP(msiof3_clk_b),
4283 SH_PFC_PIN_GROUP(msiof3_sync_b),
4284 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4285 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4286 SH_PFC_PIN_GROUP(msiof3_txd_b),
4287 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4288 SH_PFC_PIN_GROUP(msiof3_clk_c),
4289 SH_PFC_PIN_GROUP(msiof3_sync_c),
4290 SH_PFC_PIN_GROUP(msiof3_txd_c),
4291 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4292 SH_PFC_PIN_GROUP(msiof3_clk_d),
4293 SH_PFC_PIN_GROUP(msiof3_sync_d),
4294 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4295 SH_PFC_PIN_GROUP(msiof3_txd_d),
4296 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4297 SH_PFC_PIN_GROUP(msiof3_clk_e),
4298 SH_PFC_PIN_GROUP(msiof3_sync_e),
4299 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4300 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4301 SH_PFC_PIN_GROUP(msiof3_txd_e),
4302 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4303 SH_PFC_PIN_GROUP(pwm0),
4304 SH_PFC_PIN_GROUP(pwm1_a),
4305 SH_PFC_PIN_GROUP(pwm1_b),
4306 SH_PFC_PIN_GROUP(pwm2_a),
4307 SH_PFC_PIN_GROUP(pwm2_b),
4308 SH_PFC_PIN_GROUP(pwm3_a),
4309 SH_PFC_PIN_GROUP(pwm3_b),
4310 SH_PFC_PIN_GROUP(pwm4_a),
4311 SH_PFC_PIN_GROUP(pwm4_b),
4312 SH_PFC_PIN_GROUP(pwm5_a),
4313 SH_PFC_PIN_GROUP(pwm5_b),
4314 SH_PFC_PIN_GROUP(pwm6_a),
4315 SH_PFC_PIN_GROUP(pwm6_b),
4316 SH_PFC_PIN_GROUP(scif0_data),
4317 SH_PFC_PIN_GROUP(scif0_clk),
4318 SH_PFC_PIN_GROUP(scif0_ctrl),
4319 SH_PFC_PIN_GROUP(scif1_data_a),
4320 SH_PFC_PIN_GROUP(scif1_clk),
4321 SH_PFC_PIN_GROUP(scif1_ctrl),
4322 SH_PFC_PIN_GROUP(scif1_data_b),
4323 SH_PFC_PIN_GROUP(scif2_data_a),
4324 SH_PFC_PIN_GROUP(scif2_clk),
4325 SH_PFC_PIN_GROUP(scif2_data_b),
4326 SH_PFC_PIN_GROUP(scif3_data_a),
4327 SH_PFC_PIN_GROUP(scif3_clk),
4328 SH_PFC_PIN_GROUP(scif3_ctrl),
4329 SH_PFC_PIN_GROUP(scif3_data_b),
4330 SH_PFC_PIN_GROUP(scif4_data_a),
4331 SH_PFC_PIN_GROUP(scif4_clk_a),
4332 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4333 SH_PFC_PIN_GROUP(scif4_data_b),
4334 SH_PFC_PIN_GROUP(scif4_clk_b),
4335 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4336 SH_PFC_PIN_GROUP(scif4_data_c),
4337 SH_PFC_PIN_GROUP(scif4_clk_c),
4338 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4339 SH_PFC_PIN_GROUP(scif5_data_a),
4340 SH_PFC_PIN_GROUP(scif5_clk_a),
4341 SH_PFC_PIN_GROUP(scif5_data_b),
4342 SH_PFC_PIN_GROUP(scif5_clk_b),
4343 SH_PFC_PIN_GROUP(scif_clk_a),
4344 SH_PFC_PIN_GROUP(scif_clk_b),
4345 SH_PFC_PIN_GROUP(sdhi0_data1),
4346 SH_PFC_PIN_GROUP(sdhi0_data4),
4347 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4348 SH_PFC_PIN_GROUP(sdhi0_cd),
4349 SH_PFC_PIN_GROUP(sdhi0_wp),
4350 SH_PFC_PIN_GROUP(sdhi1_data1),
4351 SH_PFC_PIN_GROUP(sdhi1_data4),
4352 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4353 SH_PFC_PIN_GROUP(sdhi1_cd),
4354 SH_PFC_PIN_GROUP(sdhi1_wp),
4355 SH_PFC_PIN_GROUP(sdhi2_data1),
4356 SH_PFC_PIN_GROUP(sdhi2_data4),
4357 SH_PFC_PIN_GROUP(sdhi2_data8),
4358 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4359 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4360 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4361 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4362 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4363 SH_PFC_PIN_GROUP(sdhi2_ds),
4364 SH_PFC_PIN_GROUP(sdhi3_data1),
4365 SH_PFC_PIN_GROUP(sdhi3_data4),
4366 SH_PFC_PIN_GROUP(sdhi3_data8),
4367 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4368 SH_PFC_PIN_GROUP(sdhi3_cd),
4369 SH_PFC_PIN_GROUP(sdhi3_wp),
4370 SH_PFC_PIN_GROUP(sdhi3_ds),
4371 SH_PFC_PIN_GROUP(ssi0_data),
4372 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4373 SH_PFC_PIN_GROUP(ssi1_data_a),
4374 SH_PFC_PIN_GROUP(ssi1_data_b),
4375 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4376 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4377 SH_PFC_PIN_GROUP(ssi2_data_a),
4378 SH_PFC_PIN_GROUP(ssi2_data_b),
4379 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4380 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4381 SH_PFC_PIN_GROUP(ssi3_data),
4382 SH_PFC_PIN_GROUP(ssi349_ctrl),
4383 SH_PFC_PIN_GROUP(ssi4_data),
4384 SH_PFC_PIN_GROUP(ssi4_ctrl),
4385 SH_PFC_PIN_GROUP(ssi5_data),
4386 SH_PFC_PIN_GROUP(ssi5_ctrl),
4387 SH_PFC_PIN_GROUP(ssi6_data),
4388 SH_PFC_PIN_GROUP(ssi6_ctrl),
4389 SH_PFC_PIN_GROUP(ssi7_data),
4390 SH_PFC_PIN_GROUP(ssi78_ctrl),
4391 SH_PFC_PIN_GROUP(ssi8_data),
4392 SH_PFC_PIN_GROUP(ssi9_data_a),
4393 SH_PFC_PIN_GROUP(ssi9_data_b),
4394 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4395 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4396 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4397 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4398 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4399 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4400 SH_PFC_PIN_GROUP(usb0),
4401 SH_PFC_PIN_GROUP(usb1),
4402 SH_PFC_PIN_GROUP(usb30),
4403 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4404 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4405 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4406 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4407 SH_PFC_PIN_GROUP(vin4_data18_a),
4408 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4409 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4410 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4411 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4412 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4413 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4414 SH_PFC_PIN_GROUP(vin4_data18_b),
4415 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4416 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4417 SH_PFC_PIN_GROUP(vin4_sync),
4418 SH_PFC_PIN_GROUP(vin4_field),
4419 SH_PFC_PIN_GROUP(vin4_clkenb),
4420 SH_PFC_PIN_GROUP(vin4_clk),
4421 VIN_DATA_PIN_GROUP(vin5_data, 8),
4422 VIN_DATA_PIN_GROUP(vin5_data, 10),
4423 VIN_DATA_PIN_GROUP(vin5_data, 12),
4424 VIN_DATA_PIN_GROUP(vin5_data, 16),
4425 SH_PFC_PIN_GROUP(vin5_sync),
4426 SH_PFC_PIN_GROUP(vin5_field),
4427 SH_PFC_PIN_GROUP(vin5_clkenb),
4428 SH_PFC_PIN_GROUP(vin5_clk),
4429 },
4430 .automotive = {
4431 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4432 SH_PFC_PIN_GROUP(drif0_data0_a),
4433 SH_PFC_PIN_GROUP(drif0_data1_a),
4434 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4435 SH_PFC_PIN_GROUP(drif0_data0_b),
4436 SH_PFC_PIN_GROUP(drif0_data1_b),
4437 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4438 SH_PFC_PIN_GROUP(drif0_data0_c),
4439 SH_PFC_PIN_GROUP(drif0_data1_c),
4440 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4441 SH_PFC_PIN_GROUP(drif1_data0_a),
4442 SH_PFC_PIN_GROUP(drif1_data1_a),
4443 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4444 SH_PFC_PIN_GROUP(drif1_data0_b),
4445 SH_PFC_PIN_GROUP(drif1_data1_b),
4446 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4447 SH_PFC_PIN_GROUP(drif1_data0_c),
4448 SH_PFC_PIN_GROUP(drif1_data1_c),
4449 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4450 SH_PFC_PIN_GROUP(drif2_data0_a),
4451 SH_PFC_PIN_GROUP(drif2_data1_a),
4452 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4453 SH_PFC_PIN_GROUP(drif2_data0_b),
4454 SH_PFC_PIN_GROUP(drif2_data1_b),
4455 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4456 SH_PFC_PIN_GROUP(drif3_data0_a),
4457 SH_PFC_PIN_GROUP(drif3_data1_a),
4458 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4459 SH_PFC_PIN_GROUP(drif3_data0_b),
4460 SH_PFC_PIN_GROUP(drif3_data1_b),
4461 }
4462};
4463
4464static const char * const audio_clk_groups[] = {
4465 "audio_clk_a_a",
4466 "audio_clk_a_b",
4467 "audio_clk_a_c",
4468 "audio_clk_b_a",
4469 "audio_clk_b_b",
4470 "audio_clk_c_a",
4471 "audio_clk_c_b",
4472 "audio_clkout_a",
4473 "audio_clkout_b",
4474 "audio_clkout_c",
4475 "audio_clkout_d",
4476 "audio_clkout1_a",
4477 "audio_clkout1_b",
4478 "audio_clkout2_a",
4479 "audio_clkout2_b",
4480 "audio_clkout3_a",
4481 "audio_clkout3_b",
4482};
4483
4484static const char * const avb_groups[] = {
4485 "avb_link",
4486 "avb_magic",
4487 "avb_phy_int",
4488 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4489 "avb_mdio",
4490 "avb_mii",
4491 "avb_avtp_pps",
4492 "avb_avtp_match_a",
4493 "avb_avtp_capture_a",
4494 "avb_avtp_match_b",
4495 "avb_avtp_capture_b",
4496};
4497
4498static const char * const can0_groups[] = {
4499 "can0_data_a",
4500 "can0_data_b",
4501};
4502
4503static const char * const can1_groups[] = {
4504 "can1_data",
4505};
4506
4507static const char * const can_clk_groups[] = {
4508 "can_clk",
4509};
4510
4511static const char * const canfd0_groups[] = {
4512 "canfd0_data_a",
4513 "canfd0_data_b",
4514};
4515
4516static const char * const canfd1_groups[] = {
4517 "canfd1_data",
4518};
4519
4520static const char * const drif0_groups[] = {
4521 "drif0_ctrl_a",
4522 "drif0_data0_a",
4523 "drif0_data1_a",
4524 "drif0_ctrl_b",
4525 "drif0_data0_b",
4526 "drif0_data1_b",
4527 "drif0_ctrl_c",
4528 "drif0_data0_c",
4529 "drif0_data1_c",
4530};
4531
4532static const char * const drif1_groups[] = {
4533 "drif1_ctrl_a",
4534 "drif1_data0_a",
4535 "drif1_data1_a",
4536 "drif1_ctrl_b",
4537 "drif1_data0_b",
4538 "drif1_data1_b",
4539 "drif1_ctrl_c",
4540 "drif1_data0_c",
4541 "drif1_data1_c",
4542};
4543
4544static const char * const drif2_groups[] = {
4545 "drif2_ctrl_a",
4546 "drif2_data0_a",
4547 "drif2_data1_a",
4548 "drif2_ctrl_b",
4549 "drif2_data0_b",
4550 "drif2_data1_b",
4551};
4552
4553static const char * const drif3_groups[] = {
4554 "drif3_ctrl_a",
4555 "drif3_data0_a",
4556 "drif3_data1_a",
4557 "drif3_ctrl_b",
4558 "drif3_data0_b",
4559 "drif3_data1_b",
4560};
4561
4562static const char * const du_groups[] = {
4563 "du_rgb666",
4564 "du_rgb888",
4565 "du_clk_out_0",
4566 "du_clk_out_1",
4567 "du_sync",
4568 "du_oddf",
4569 "du_cde",
4570 "du_disp",
4571};
4572
4573static const char * const hscif0_groups[] = {
4574 "hscif0_data",
4575 "hscif0_clk",
4576 "hscif0_ctrl",
4577};
4578
4579static const char * const hscif1_groups[] = {
4580 "hscif1_data_a",
4581 "hscif1_clk_a",
4582 "hscif1_ctrl_a",
4583 "hscif1_data_b",
4584 "hscif1_clk_b",
4585 "hscif1_ctrl_b",
4586};
4587
4588static const char * const hscif2_groups[] = {
4589 "hscif2_data_a",
4590 "hscif2_clk_a",
4591 "hscif2_ctrl_a",
4592 "hscif2_data_b",
4593 "hscif2_clk_b",
4594 "hscif2_ctrl_b",
4595 "hscif2_data_c",
4596 "hscif2_clk_c",
4597 "hscif2_ctrl_c",
4598};
4599
4600static const char * const hscif3_groups[] = {
4601 "hscif3_data_a",
4602 "hscif3_clk",
4603 "hscif3_ctrl",
4604 "hscif3_data_b",
4605 "hscif3_data_c",
4606 "hscif3_data_d",
4607};
4608
4609static const char * const hscif4_groups[] = {
4610 "hscif4_data_a",
4611 "hscif4_clk",
4612 "hscif4_ctrl",
4613 "hscif4_data_b",
4614};
4615
4616static const char * const i2c0_groups[] = {
4617 "i2c0",
4618};
4619
4620static const char * const i2c1_groups[] = {
4621 "i2c1_a",
4622 "i2c1_b",
4623};
4624
4625static const char * const i2c2_groups[] = {
4626 "i2c2_a",
4627 "i2c2_b",
4628};
4629
4630static const char * const i2c3_groups[] = {
4631 "i2c3",
4632};
4633
4634static const char * const i2c5_groups[] = {
4635 "i2c5",
4636};
4637
4638static const char * const i2c6_groups[] = {
4639 "i2c6_a",
4640 "i2c6_b",
4641 "i2c6_c",
4642};
4643
4644static const char * const intc_ex_groups[] = {
4645 "intc_ex_irq0",
4646 "intc_ex_irq1",
4647 "intc_ex_irq2",
4648 "intc_ex_irq3",
4649 "intc_ex_irq4",
4650 "intc_ex_irq5",
4651};
4652
4653static const char * const msiof0_groups[] = {
4654 "msiof0_clk",
4655 "msiof0_sync",
4656 "msiof0_ss1",
4657 "msiof0_ss2",
4658 "msiof0_txd",
4659 "msiof0_rxd",
4660};
4661
4662static const char * const msiof1_groups[] = {
4663 "msiof1_clk_a",
4664 "msiof1_sync_a",
4665 "msiof1_ss1_a",
4666 "msiof1_ss2_a",
4667 "msiof1_txd_a",
4668 "msiof1_rxd_a",
4669 "msiof1_clk_b",
4670 "msiof1_sync_b",
4671 "msiof1_ss1_b",
4672 "msiof1_ss2_b",
4673 "msiof1_txd_b",
4674 "msiof1_rxd_b",
4675 "msiof1_clk_c",
4676 "msiof1_sync_c",
4677 "msiof1_ss1_c",
4678 "msiof1_ss2_c",
4679 "msiof1_txd_c",
4680 "msiof1_rxd_c",
4681 "msiof1_clk_d",
4682 "msiof1_sync_d",
4683 "msiof1_ss1_d",
4684 "msiof1_ss2_d",
4685 "msiof1_txd_d",
4686 "msiof1_rxd_d",
4687 "msiof1_clk_e",
4688 "msiof1_sync_e",
4689 "msiof1_ss1_e",
4690 "msiof1_ss2_e",
4691 "msiof1_txd_e",
4692 "msiof1_rxd_e",
4693 "msiof1_clk_f",
4694 "msiof1_sync_f",
4695 "msiof1_ss1_f",
4696 "msiof1_ss2_f",
4697 "msiof1_txd_f",
4698 "msiof1_rxd_f",
4699 "msiof1_clk_g",
4700 "msiof1_sync_g",
4701 "msiof1_ss1_g",
4702 "msiof1_ss2_g",
4703 "msiof1_txd_g",
4704 "msiof1_rxd_g",
4705};
4706
4707static const char * const msiof2_groups[] = {
4708 "msiof2_clk_a",
4709 "msiof2_sync_a",
4710 "msiof2_ss1_a",
4711 "msiof2_ss2_a",
4712 "msiof2_txd_a",
4713 "msiof2_rxd_a",
4714 "msiof2_clk_b",
4715 "msiof2_sync_b",
4716 "msiof2_ss1_b",
4717 "msiof2_ss2_b",
4718 "msiof2_txd_b",
4719 "msiof2_rxd_b",
4720 "msiof2_clk_c",
4721 "msiof2_sync_c",
4722 "msiof2_ss1_c",
4723 "msiof2_ss2_c",
4724 "msiof2_txd_c",
4725 "msiof2_rxd_c",
4726 "msiof2_clk_d",
4727 "msiof2_sync_d",
4728 "msiof2_ss1_d",
4729 "msiof2_ss2_d",
4730 "msiof2_txd_d",
4731 "msiof2_rxd_d",
4732};
4733
4734static const char * const msiof3_groups[] = {
4735 "msiof3_clk_a",
4736 "msiof3_sync_a",
4737 "msiof3_ss1_a",
4738 "msiof3_ss2_a",
4739 "msiof3_txd_a",
4740 "msiof3_rxd_a",
4741 "msiof3_clk_b",
4742 "msiof3_sync_b",
4743 "msiof3_ss1_b",
4744 "msiof3_ss2_b",
4745 "msiof3_txd_b",
4746 "msiof3_rxd_b",
4747 "msiof3_clk_c",
4748 "msiof3_sync_c",
4749 "msiof3_txd_c",
4750 "msiof3_rxd_c",
4751 "msiof3_clk_d",
4752 "msiof3_sync_d",
4753 "msiof3_ss1_d",
4754 "msiof3_txd_d",
4755 "msiof3_rxd_d",
4756 "msiof3_clk_e",
4757 "msiof3_sync_e",
4758 "msiof3_ss1_e",
4759 "msiof3_ss2_e",
4760 "msiof3_txd_e",
4761 "msiof3_rxd_e",
4762};
4763
4764static const char * const pwm0_groups[] = {
4765 "pwm0",
4766};
4767
4768static const char * const pwm1_groups[] = {
4769 "pwm1_a",
4770 "pwm1_b",
4771};
4772
4773static const char * const pwm2_groups[] = {
4774 "pwm2_a",
4775 "pwm2_b",
4776};
4777
4778static const char * const pwm3_groups[] = {
4779 "pwm3_a",
4780 "pwm3_b",
4781};
4782
4783static const char * const pwm4_groups[] = {
4784 "pwm4_a",
4785 "pwm4_b",
4786};
4787
4788static const char * const pwm5_groups[] = {
4789 "pwm5_a",
4790 "pwm5_b",
4791};
4792
4793static const char * const pwm6_groups[] = {
4794 "pwm6_a",
4795 "pwm6_b",
4796};
4797
4798static const char * const scif0_groups[] = {
4799 "scif0_data",
4800 "scif0_clk",
4801 "scif0_ctrl",
4802};
4803
4804static const char * const scif1_groups[] = {
4805 "scif1_data_a",
4806 "scif1_clk",
4807 "scif1_ctrl",
4808 "scif1_data_b",
4809};
4810
4811static const char * const scif2_groups[] = {
4812 "scif2_data_a",
4813 "scif2_clk",
4814 "scif2_data_b",
4815};
4816
4817static const char * const scif3_groups[] = {
4818 "scif3_data_a",
4819 "scif3_clk",
4820 "scif3_ctrl",
4821 "scif3_data_b",
4822};
4823
4824static const char * const scif4_groups[] = {
4825 "scif4_data_a",
4826 "scif4_clk_a",
4827 "scif4_ctrl_a",
4828 "scif4_data_b",
4829 "scif4_clk_b",
4830 "scif4_ctrl_b",
4831 "scif4_data_c",
4832 "scif4_clk_c",
4833 "scif4_ctrl_c",
4834};
4835
4836static const char * const scif5_groups[] = {
4837 "scif5_data_a",
4838 "scif5_clk_a",
4839 "scif5_data_b",
4840 "scif5_clk_b",
4841};
4842
4843static const char * const scif_clk_groups[] = {
4844 "scif_clk_a",
4845 "scif_clk_b",
4846};
4847
4848static const char * const sdhi0_groups[] = {
4849 "sdhi0_data1",
4850 "sdhi0_data4",
4851 "sdhi0_ctrl",
4852 "sdhi0_cd",
4853 "sdhi0_wp",
4854};
4855
4856static const char * const sdhi1_groups[] = {
4857 "sdhi1_data1",
4858 "sdhi1_data4",
4859 "sdhi1_ctrl",
4860 "sdhi1_cd",
4861 "sdhi1_wp",
4862};
4863
4864static const char * const sdhi2_groups[] = {
4865 "sdhi2_data1",
4866 "sdhi2_data4",
4867 "sdhi2_data8",
4868 "sdhi2_ctrl",
4869 "sdhi2_cd_a",
4870 "sdhi2_wp_a",
4871 "sdhi2_cd_b",
4872 "sdhi2_wp_b",
4873 "sdhi2_ds",
4874};
4875
4876static const char * const sdhi3_groups[] = {
4877 "sdhi3_data1",
4878 "sdhi3_data4",
4879 "sdhi3_data8",
4880 "sdhi3_ctrl",
4881 "sdhi3_cd",
4882 "sdhi3_wp",
4883 "sdhi3_ds",
4884};
4885
4886static const char * const ssi_groups[] = {
4887 "ssi0_data",
4888 "ssi01239_ctrl",
4889 "ssi1_data_a",
4890 "ssi1_data_b",
4891 "ssi1_ctrl_a",
4892 "ssi1_ctrl_b",
4893 "ssi2_data_a",
4894 "ssi2_data_b",
4895 "ssi2_ctrl_a",
4896 "ssi2_ctrl_b",
4897 "ssi3_data",
4898 "ssi349_ctrl",
4899 "ssi4_data",
4900 "ssi4_ctrl",
4901 "ssi5_data",
4902 "ssi5_ctrl",
4903 "ssi6_data",
4904 "ssi6_ctrl",
4905 "ssi7_data",
4906 "ssi78_ctrl",
4907 "ssi8_data",
4908 "ssi9_data_a",
4909 "ssi9_data_b",
4910 "ssi9_ctrl_a",
4911 "ssi9_ctrl_b",
4912};
4913
4914static const char * const tmu_groups[] = {
4915 "tmu_tclk1_a",
4916 "tmu_tclk1_b",
4917 "tmu_tclk2_a",
4918 "tmu_tclk2_b",
4919};
4920
4921static const char * const usb0_groups[] = {
4922 "usb0",
4923};
4924
4925static const char * const usb1_groups[] = {
4926 "usb1",
4927};
4928
4929static const char * const usb30_groups[] = {
4930 "usb30",
4931};
4932
4933static const char * const vin4_groups[] = {
4934 "vin4_data8_a",
4935 "vin4_data10_a",
4936 "vin4_data12_a",
4937 "vin4_data16_a",
4938 "vin4_data18_a",
4939 "vin4_data20_a",
4940 "vin4_data24_a",
4941 "vin4_data8_b",
4942 "vin4_data10_b",
4943 "vin4_data12_b",
4944 "vin4_data16_b",
4945 "vin4_data18_b",
4946 "vin4_data20_b",
4947 "vin4_data24_b",
4948 "vin4_sync",
4949 "vin4_field",
4950 "vin4_clkenb",
4951 "vin4_clk",
4952};
4953
4954static const char * const vin5_groups[] = {
4955 "vin5_data8",
4956 "vin5_data10",
4957 "vin5_data12",
4958 "vin5_data16",
4959 "vin5_sync",
4960 "vin5_field",
4961 "vin5_clkenb",
4962 "vin5_clk",
4963};
4964
4965static const struct {
4966 struct sh_pfc_function common[49];
4967 struct sh_pfc_function automotive[4];
4968} pinmux_functions = {
4969 .common = {
4970 SH_PFC_FUNCTION(audio_clk),
4971 SH_PFC_FUNCTION(avb),
4972 SH_PFC_FUNCTION(can0),
4973 SH_PFC_FUNCTION(can1),
4974 SH_PFC_FUNCTION(can_clk),
4975 SH_PFC_FUNCTION(canfd0),
4976 SH_PFC_FUNCTION(canfd1),
4977 SH_PFC_FUNCTION(du),
4978 SH_PFC_FUNCTION(hscif0),
4979 SH_PFC_FUNCTION(hscif1),
4980 SH_PFC_FUNCTION(hscif2),
4981 SH_PFC_FUNCTION(hscif3),
4982 SH_PFC_FUNCTION(hscif4),
4983 SH_PFC_FUNCTION(i2c0),
4984 SH_PFC_FUNCTION(i2c1),
4985 SH_PFC_FUNCTION(i2c2),
4986 SH_PFC_FUNCTION(i2c3),
4987 SH_PFC_FUNCTION(i2c5),
4988 SH_PFC_FUNCTION(i2c6),
4989 SH_PFC_FUNCTION(intc_ex),
4990 SH_PFC_FUNCTION(msiof0),
4991 SH_PFC_FUNCTION(msiof1),
4992 SH_PFC_FUNCTION(msiof2),
4993 SH_PFC_FUNCTION(msiof3),
4994 SH_PFC_FUNCTION(pwm0),
4995 SH_PFC_FUNCTION(pwm1),
4996 SH_PFC_FUNCTION(pwm2),
4997 SH_PFC_FUNCTION(pwm3),
4998 SH_PFC_FUNCTION(pwm4),
4999 SH_PFC_FUNCTION(pwm5),
5000 SH_PFC_FUNCTION(pwm6),
5001 SH_PFC_FUNCTION(scif0),
5002 SH_PFC_FUNCTION(scif1),
5003 SH_PFC_FUNCTION(scif2),
5004 SH_PFC_FUNCTION(scif3),
5005 SH_PFC_FUNCTION(scif4),
5006 SH_PFC_FUNCTION(scif5),
5007 SH_PFC_FUNCTION(scif_clk),
5008 SH_PFC_FUNCTION(sdhi0),
5009 SH_PFC_FUNCTION(sdhi1),
5010 SH_PFC_FUNCTION(sdhi2),
5011 SH_PFC_FUNCTION(sdhi3),
5012 SH_PFC_FUNCTION(ssi),
5013 SH_PFC_FUNCTION(tmu),
5014 SH_PFC_FUNCTION(usb0),
5015 SH_PFC_FUNCTION(usb1),
5016 SH_PFC_FUNCTION(usb30),
5017 SH_PFC_FUNCTION(vin4),
5018 SH_PFC_FUNCTION(vin5),
5019 },
5020 .automotive = {
5021 SH_PFC_FUNCTION(drif0),
5022 SH_PFC_FUNCTION(drif1),
5023 SH_PFC_FUNCTION(drif2),
5024 SH_PFC_FUNCTION(drif3),
5025 }
5026};
5027
5028static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5029#define F_(x, y) FN_##y
5030#define FM(x) FN_##x
5031 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5032 0, 0,
5033 0, 0,
5034 0, 0,
5035 0, 0,
5036 0, 0,
5037 0, 0,
5038 0, 0,
5039 0, 0,
5040 0, 0,
5041 0, 0,
5042 0, 0,
5043 0, 0,
5044 0, 0,
5045 0, 0,
5046 0, 0,
5047 0, 0,
5048 GP_0_15_FN, GPSR0_15,
5049 GP_0_14_FN, GPSR0_14,
5050 GP_0_13_FN, GPSR0_13,
5051 GP_0_12_FN, GPSR0_12,
5052 GP_0_11_FN, GPSR0_11,
5053 GP_0_10_FN, GPSR0_10,
5054 GP_0_9_FN, GPSR0_9,
5055 GP_0_8_FN, GPSR0_8,
5056 GP_0_7_FN, GPSR0_7,
5057 GP_0_6_FN, GPSR0_6,
5058 GP_0_5_FN, GPSR0_5,
5059 GP_0_4_FN, GPSR0_4,
5060 GP_0_3_FN, GPSR0_3,
5061 GP_0_2_FN, GPSR0_2,
5062 GP_0_1_FN, GPSR0_1,
5063 GP_0_0_FN, GPSR0_0, ))
5064 },
5065 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5066 0, 0,
5067 0, 0,
5068 0, 0,
5069 GP_1_28_FN, GPSR1_28,
5070 GP_1_27_FN, GPSR1_27,
5071 GP_1_26_FN, GPSR1_26,
5072 GP_1_25_FN, GPSR1_25,
5073 GP_1_24_FN, GPSR1_24,
5074 GP_1_23_FN, GPSR1_23,
5075 GP_1_22_FN, GPSR1_22,
5076 GP_1_21_FN, GPSR1_21,
5077 GP_1_20_FN, GPSR1_20,
5078 GP_1_19_FN, GPSR1_19,
5079 GP_1_18_FN, GPSR1_18,
5080 GP_1_17_FN, GPSR1_17,
5081 GP_1_16_FN, GPSR1_16,
5082 GP_1_15_FN, GPSR1_15,
5083 GP_1_14_FN, GPSR1_14,
5084 GP_1_13_FN, GPSR1_13,
5085 GP_1_12_FN, GPSR1_12,
5086 GP_1_11_FN, GPSR1_11,
5087 GP_1_10_FN, GPSR1_10,
5088 GP_1_9_FN, GPSR1_9,
5089 GP_1_8_FN, GPSR1_8,
5090 GP_1_7_FN, GPSR1_7,
5091 GP_1_6_FN, GPSR1_6,
5092 GP_1_5_FN, GPSR1_5,
5093 GP_1_4_FN, GPSR1_4,
5094 GP_1_3_FN, GPSR1_3,
5095 GP_1_2_FN, GPSR1_2,
5096 GP_1_1_FN, GPSR1_1,
5097 GP_1_0_FN, GPSR1_0, ))
5098 },
5099 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5100 0, 0,
5101 0, 0,
5102 0, 0,
5103 0, 0,
5104 0, 0,
5105 0, 0,
5106 0, 0,
5107 0, 0,
5108 0, 0,
5109 0, 0,
5110 0, 0,
5111 0, 0,
5112 0, 0,
5113 0, 0,
5114 0, 0,
5115 0, 0,
5116 0, 0,
5117 GP_2_14_FN, GPSR2_14,
5118 GP_2_13_FN, GPSR2_13,
5119 GP_2_12_FN, GPSR2_12,
5120 GP_2_11_FN, GPSR2_11,
5121 GP_2_10_FN, GPSR2_10,
5122 GP_2_9_FN, GPSR2_9,
5123 GP_2_8_FN, GPSR2_8,
5124 GP_2_7_FN, GPSR2_7,
5125 GP_2_6_FN, GPSR2_6,
5126 GP_2_5_FN, GPSR2_5,
5127 GP_2_4_FN, GPSR2_4,
5128 GP_2_3_FN, GPSR2_3,
5129 GP_2_2_FN, GPSR2_2,
5130 GP_2_1_FN, GPSR2_1,
5131 GP_2_0_FN, GPSR2_0, ))
5132 },
5133 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5134 0, 0,
5135 0, 0,
5136 0, 0,
5137 0, 0,
5138 0, 0,
5139 0, 0,
5140 0, 0,
5141 0, 0,
5142 0, 0,
5143 0, 0,
5144 0, 0,
5145 0, 0,
5146 0, 0,
5147 0, 0,
5148 0, 0,
5149 0, 0,
5150 GP_3_15_FN, GPSR3_15,
5151 GP_3_14_FN, GPSR3_14,
5152 GP_3_13_FN, GPSR3_13,
5153 GP_3_12_FN, GPSR3_12,
5154 GP_3_11_FN, GPSR3_11,
5155 GP_3_10_FN, GPSR3_10,
5156 GP_3_9_FN, GPSR3_9,
5157 GP_3_8_FN, GPSR3_8,
5158 GP_3_7_FN, GPSR3_7,
5159 GP_3_6_FN, GPSR3_6,
5160 GP_3_5_FN, GPSR3_5,
5161 GP_3_4_FN, GPSR3_4,
5162 GP_3_3_FN, GPSR3_3,
5163 GP_3_2_FN, GPSR3_2,
5164 GP_3_1_FN, GPSR3_1,
5165 GP_3_0_FN, GPSR3_0, ))
5166 },
5167 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5168 0, 0,
5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 0, 0,
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 0, 0,
5178 0, 0,
5179 0, 0,
5180 0, 0,
5181 0, 0,
5182 GP_4_17_FN, GPSR4_17,
5183 GP_4_16_FN, GPSR4_16,
5184 GP_4_15_FN, GPSR4_15,
5185 GP_4_14_FN, GPSR4_14,
5186 GP_4_13_FN, GPSR4_13,
5187 GP_4_12_FN, GPSR4_12,
5188 GP_4_11_FN, GPSR4_11,
5189 GP_4_10_FN, GPSR4_10,
5190 GP_4_9_FN, GPSR4_9,
5191 GP_4_8_FN, GPSR4_8,
5192 GP_4_7_FN, GPSR4_7,
5193 GP_4_6_FN, GPSR4_6,
5194 GP_4_5_FN, GPSR4_5,
5195 GP_4_4_FN, GPSR4_4,
5196 GP_4_3_FN, GPSR4_3,
5197 GP_4_2_FN, GPSR4_2,
5198 GP_4_1_FN, GPSR4_1,
5199 GP_4_0_FN, GPSR4_0, ))
5200 },
5201 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 GP_5_25_FN, GPSR5_25,
5209 GP_5_24_FN, GPSR5_24,
5210 GP_5_23_FN, GPSR5_23,
5211 GP_5_22_FN, GPSR5_22,
5212 GP_5_21_FN, GPSR5_21,
5213 GP_5_20_FN, GPSR5_20,
5214 GP_5_19_FN, GPSR5_19,
5215 GP_5_18_FN, GPSR5_18,
5216 GP_5_17_FN, GPSR5_17,
5217 GP_5_16_FN, GPSR5_16,
5218 GP_5_15_FN, GPSR5_15,
5219 GP_5_14_FN, GPSR5_14,
5220 GP_5_13_FN, GPSR5_13,
5221 GP_5_12_FN, GPSR5_12,
5222 GP_5_11_FN, GPSR5_11,
5223 GP_5_10_FN, GPSR5_10,
5224 GP_5_9_FN, GPSR5_9,
5225 GP_5_8_FN, GPSR5_8,
5226 GP_5_7_FN, GPSR5_7,
5227 GP_5_6_FN, GPSR5_6,
5228 GP_5_5_FN, GPSR5_5,
5229 GP_5_4_FN, GPSR5_4,
5230 GP_5_3_FN, GPSR5_3,
5231 GP_5_2_FN, GPSR5_2,
5232 GP_5_1_FN, GPSR5_1,
5233 GP_5_0_FN, GPSR5_0, ))
5234 },
5235 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5236 GP_6_31_FN, GPSR6_31,
5237 GP_6_30_FN, GPSR6_30,
5238 GP_6_29_FN, GPSR6_29,
5239 GP_6_28_FN, GPSR6_28,
5240 GP_6_27_FN, GPSR6_27,
5241 GP_6_26_FN, GPSR6_26,
5242 GP_6_25_FN, GPSR6_25,
5243 GP_6_24_FN, GPSR6_24,
5244 GP_6_23_FN, GPSR6_23,
5245 GP_6_22_FN, GPSR6_22,
5246 GP_6_21_FN, GPSR6_21,
5247 GP_6_20_FN, GPSR6_20,
5248 GP_6_19_FN, GPSR6_19,
5249 GP_6_18_FN, GPSR6_18,
5250 GP_6_17_FN, GPSR6_17,
5251 GP_6_16_FN, GPSR6_16,
5252 GP_6_15_FN, GPSR6_15,
5253 GP_6_14_FN, GPSR6_14,
5254 GP_6_13_FN, GPSR6_13,
5255 GP_6_12_FN, GPSR6_12,
5256 GP_6_11_FN, GPSR6_11,
5257 GP_6_10_FN, GPSR6_10,
5258 GP_6_9_FN, GPSR6_9,
5259 GP_6_8_FN, GPSR6_8,
5260 GP_6_7_FN, GPSR6_7,
5261 GP_6_6_FN, GPSR6_6,
5262 GP_6_5_FN, GPSR6_5,
5263 GP_6_4_FN, GPSR6_4,
5264 GP_6_3_FN, GPSR6_3,
5265 GP_6_2_FN, GPSR6_2,
5266 GP_6_1_FN, GPSR6_1,
5267 GP_6_0_FN, GPSR6_0, ))
5268 },
5269 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 0, 0,
5274 0, 0,
5275 0, 0,
5276 0, 0,
5277 0, 0,
5278 0, 0,
5279 0, 0,
5280 0, 0,
5281 0, 0,
5282 0, 0,
5283 0, 0,
5284 0, 0,
5285 0, 0,
5286 0, 0,
5287 0, 0,
5288 0, 0,
5289 0, 0,
5290 0, 0,
5291 0, 0,
5292 0, 0,
5293 0, 0,
5294 0, 0,
5295 0, 0,
5296 0, 0,
5297 0, 0,
5298 GP_7_3_FN, GPSR7_3,
5299 GP_7_2_FN, GPSR7_2,
5300 GP_7_1_FN, GPSR7_1,
5301 GP_7_0_FN, GPSR7_0, ))
5302 },
5303#undef F_
5304#undef FM
5305
5306#define F_(x, y) x,
5307#define FM(x) FN_##x,
5308 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5309 IP0_31_28
5310 IP0_27_24
5311 IP0_23_20
5312 IP0_19_16
5313 IP0_15_12
5314 IP0_11_8
5315 IP0_7_4
5316 IP0_3_0 ))
5317 },
5318 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5319 IP1_31_28
5320 IP1_27_24
5321 IP1_23_20
5322 IP1_19_16
5323 IP1_15_12
5324 IP1_11_8
5325 IP1_7_4
5326 IP1_3_0 ))
5327 },
5328 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5329 IP2_31_28
5330 IP2_27_24
5331 IP2_23_20
5332 IP2_19_16
5333 IP2_15_12
5334 IP2_11_8
5335 IP2_7_4
5336 IP2_3_0 ))
5337 },
5338 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5339 IP3_31_28
5340 IP3_27_24
5341 IP3_23_20
5342 IP3_19_16
5343 IP3_15_12
5344 IP3_11_8
5345 IP3_7_4
5346 IP3_3_0 ))
5347 },
5348 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5349 IP4_31_28
5350 IP4_27_24
5351 IP4_23_20
5352 IP4_19_16
5353 IP4_15_12
5354 IP4_11_8
5355 IP4_7_4
5356 IP4_3_0 ))
5357 },
5358 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5359 IP5_31_28
5360 IP5_27_24
5361 IP5_23_20
5362 IP5_19_16
5363 IP5_15_12
5364 IP5_11_8
5365 IP5_7_4
5366 IP5_3_0 ))
5367 },
5368 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5369 IP6_31_28
5370 IP6_27_24
5371 IP6_23_20
5372 IP6_19_16
5373 IP6_15_12
5374 IP6_11_8
5375 IP6_7_4
5376 IP6_3_0 ))
5377 },
5378 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5379 IP7_31_28
5380 IP7_27_24
5381 IP7_23_20
5382 IP7_19_16
5383 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5384 IP7_11_8
5385 IP7_7_4
5386 IP7_3_0 ))
5387 },
5388 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5389 IP8_31_28
5390 IP8_27_24
5391 IP8_23_20
5392 IP8_19_16
5393 IP8_15_12
5394 IP8_11_8
5395 IP8_7_4
5396 IP8_3_0 ))
5397 },
5398 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5399 IP9_31_28
5400 IP9_27_24
5401 IP9_23_20
5402 IP9_19_16
5403 IP9_15_12
5404 IP9_11_8
5405 IP9_7_4
5406 IP9_3_0 ))
5407 },
5408 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5409 IP10_31_28
5410 IP10_27_24
5411 IP10_23_20
5412 IP10_19_16
5413 IP10_15_12
5414 IP10_11_8
5415 IP10_7_4
5416 IP10_3_0 ))
5417 },
5418 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5419 IP11_31_28
5420 IP11_27_24
5421 IP11_23_20
5422 IP11_19_16
5423 IP11_15_12
5424 IP11_11_8
5425 IP11_7_4
5426 IP11_3_0 ))
5427 },
5428 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5429 IP12_31_28
5430 IP12_27_24
5431 IP12_23_20
5432 IP12_19_16
5433 IP12_15_12
5434 IP12_11_8
5435 IP12_7_4
5436 IP12_3_0 ))
5437 },
5438 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5439 IP13_31_28
5440 IP13_27_24
5441 IP13_23_20
5442 IP13_19_16
5443 IP13_15_12
5444 IP13_11_8
5445 IP13_7_4
5446 IP13_3_0 ))
5447 },
5448 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5449 IP14_31_28
5450 IP14_27_24
5451 IP14_23_20
5452 IP14_19_16
5453 IP14_15_12
5454 IP14_11_8
5455 IP14_7_4
5456 IP14_3_0 ))
5457 },
5458 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5459 IP15_31_28
5460 IP15_27_24
5461 IP15_23_20
5462 IP15_19_16
5463 IP15_15_12
5464 IP15_11_8
5465 IP15_7_4
5466 IP15_3_0 ))
5467 },
5468 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5469 IP16_31_28
5470 IP16_27_24
5471 IP16_23_20
5472 IP16_19_16
5473 IP16_15_12
5474 IP16_11_8
5475 IP16_7_4
5476 IP16_3_0 ))
5477 },
5478 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5479 IP17_31_28
5480 IP17_27_24
5481 IP17_23_20
5482 IP17_19_16
5483 IP17_15_12
5484 IP17_11_8
5485 IP17_7_4
5486 IP17_3_0 ))
5487 },
5488 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5489 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5490 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5491 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5492 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5493 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5494 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5495 IP18_7_4
5496 IP18_3_0 ))
5497 },
5498#undef F_
5499#undef FM
5500
5501#define F_(x, y) x,
5502#define FM(x) FN_##x,
5503 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5504 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5505 1, 1, 1, 2, 2, 1, 2, 3),
5506 GROUP(
5507 MOD_SEL0_31_30_29
5508 MOD_SEL0_28_27
5509 MOD_SEL0_26_25_24
5510 MOD_SEL0_23
5511 MOD_SEL0_22
5512 MOD_SEL0_21
5513 MOD_SEL0_20
5514 MOD_SEL0_19
5515 MOD_SEL0_18_17
5516 MOD_SEL0_16
5517 0, 0, /* RESERVED 15 */
5518 MOD_SEL0_14_13
5519 MOD_SEL0_12
5520 MOD_SEL0_11
5521 MOD_SEL0_10
5522 MOD_SEL0_9_8
5523 MOD_SEL0_7_6
5524 MOD_SEL0_5
5525 MOD_SEL0_4_3
5526 /* RESERVED 2, 1, 0 */
5527 0, 0, 0, 0, 0, 0, 0, 0 ))
5528 },
5529 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5530 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5531 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5532 GROUP(
5533 MOD_SEL1_31_30
5534 MOD_SEL1_29_28_27
5535 MOD_SEL1_26
5536 MOD_SEL1_25_24
5537 MOD_SEL1_23_22_21
5538 MOD_SEL1_20
5539 MOD_SEL1_19
5540 MOD_SEL1_18_17
5541 MOD_SEL1_16
5542 MOD_SEL1_15_14
5543 MOD_SEL1_13
5544 MOD_SEL1_12
5545 MOD_SEL1_11
5546 MOD_SEL1_10
5547 MOD_SEL1_9
5548 0, 0, 0, 0, /* RESERVED 8, 7 */
5549 MOD_SEL1_6
5550 MOD_SEL1_5
5551 MOD_SEL1_4
5552 MOD_SEL1_3
5553 MOD_SEL1_2
5554 MOD_SEL1_1
5555 MOD_SEL1_0 ))
5556 },
5557 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5558 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5559 1, 4, 4, 4, 3, 1),
5560 GROUP(
5561 MOD_SEL2_31
5562 MOD_SEL2_30
5563 MOD_SEL2_29
5564 MOD_SEL2_28_27
5565 MOD_SEL2_26
5566 MOD_SEL2_25_24_23
5567 MOD_SEL2_22
5568 MOD_SEL2_21
5569 MOD_SEL2_20
5570 MOD_SEL2_19
5571 MOD_SEL2_18
5572 MOD_SEL2_17
5573 /* RESERVED 16 */
5574 0, 0,
5575 /* RESERVED 15, 14, 13, 12 */
5576 0, 0, 0, 0, 0, 0, 0, 0,
5577 0, 0, 0, 0, 0, 0, 0, 0,
5578 /* RESERVED 11, 10, 9, 8 */
5579 0, 0, 0, 0, 0, 0, 0, 0,
5580 0, 0, 0, 0, 0, 0, 0, 0,
5581 /* RESERVED 7, 6, 5, 4 */
5582 0, 0, 0, 0, 0, 0, 0, 0,
5583 0, 0, 0, 0, 0, 0, 0, 0,
5584 /* RESERVED 3, 2, 1 */
5585 0, 0, 0, 0, 0, 0, 0, 0,
5586 MOD_SEL2_0 ))
5587 },
5588 { },
5589};
5590
5591static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5592 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5593 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5594 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5595 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5596 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5597 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5598 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5599 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5600 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5601 } },
5602 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5603 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5604 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5605 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5606 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5607 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5608 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5609 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5610 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5611 } },
5612 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5613 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5614 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5615 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5616 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5617 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5618 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5619 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5620 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5621 } },
5622 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5623 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5624 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5625 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5626 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5627 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5628 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5629 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5630 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5631 } },
5632 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5633 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5634 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5635 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5636 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5637 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5638 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5639 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5640 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5641 } },
5642 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5643 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5644 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5645 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5646 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5647 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5648 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5649 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5650 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5651 } },
5652 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5653 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5654 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5655 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5656 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5657 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5658 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5659 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5660 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5661 } },
5662 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5663 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5664 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5665 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5666 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5667 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5668 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5669 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5670 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5671 } },
5672 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5673 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5674 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5675 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5676 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5677 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5678 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5679 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5680 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5681 } },
5682 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5683 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5684 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5685 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5686 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5687 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5688 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5689 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5690 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5691 } },
5692 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5693 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5694 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5695 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5696 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5697 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5698 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5699 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5700 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5701 } },
5702 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5703 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5704 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5705 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5706 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5707 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5708 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5709 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5710 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5711 } },
5712 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5713 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5714 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5715 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5716 } },
5717 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5718 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5719 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5720 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5721 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5722 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5723 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5724 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5725 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5726 } },
5727 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5728 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5729 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5730 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5731 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5732 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5733 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5734 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5735 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5736 } },
5737 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5738 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5739 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5740 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5741 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5742 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5743 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5744 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5745 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5746 } },
5747 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5748 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5749 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5750 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5751 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5752 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5753 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5754 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5755 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5756 } },
5757 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5758 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5759 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5760 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5761 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5762 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5763 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5764 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5765 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5766 } },
5767 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5768 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5769 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5770 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5771 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5772 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5773 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5774 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5775 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5776 } },
5777 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5778 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5779 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5780 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5781 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5782 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5783 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5784 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5785 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5786 } },
5787 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5788 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5789 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5790 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5791 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5792 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5793 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5794 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5795 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5796 } },
5797 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5798 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5799 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5800 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5801 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5802 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5803 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5804 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5805 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5806 } },
5807 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5808 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5809 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5810 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5811 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5812 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5813 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5814 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5815 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5816 } },
5817 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5818 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5819 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5820 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5821 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5822 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5823 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5824 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5825 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5826 } },
5827 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5828 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5829 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5830 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5831 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5832 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5833 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5834 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5835 } },
5836 { },
5837};
5838
5839enum ioctrl_regs {
5840 POCCTRL,
5841 TDSELCTRL,
5842};
5843
5844static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5845 [POCCTRL] = { 0xe6060380, },
5846 [TDSELCTRL] = { 0xe60603c0, },
5847 { /* sentinel */ },
5848};
5849
5850static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5851{
5852 int bit = -EINVAL;
5853
5854 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5855
5856 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5857 bit = pin & 0x1f;
5858
5859 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5860 bit = (pin & 0x1f) + 12;
5861
5862 return bit;
5863}
5864
5865static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5866 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5867 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5868 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5869 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5870 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5871 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5872 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5873 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5874 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5875 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5876 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5877 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5878 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5879 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5880 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5881 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5882 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5883 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5884 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5885 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5886 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5887 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5888 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5889 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5890 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5891 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5892 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5893 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5894 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5895 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5896 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5897 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5898 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5899 } },
5900 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5901 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5902 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5903 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5904 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5905 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5906 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5907 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5908 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5909 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5910 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5911 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5912 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5913 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5914 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5915 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5916 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5917 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5918 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5919 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5920 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5921 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5922 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5923 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5924 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5925 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5926 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5927 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5928 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5929 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5930 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5931 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5932 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5933 } },
5934 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5935 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5936 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5937 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5938 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5939 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5940 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5941 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5942 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5943 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5944 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5945 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5946 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5947 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5948 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5949 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5950 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5951 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5952 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5953 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5954 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5955 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5956 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5957 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5958 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5959 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5960 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5961 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5962 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5963 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5964 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5965 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5966 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5967 } },
5968 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5969 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5970 [ 1] = PIN_NONE,
5971 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5972 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5973 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5974 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5975 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5976 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5977 [ 8] = PIN_NONE,
5978 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5979 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5980 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5981 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5982 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5983 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5984 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5985 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5986 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5987 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5988 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5989 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5990 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5991 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5992 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5993 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5994 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5995 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5996 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5997 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5998 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5999 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6000 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6001 } },
6002 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6003 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6004 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6005 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6006 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6007 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6008 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6009 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6010 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6011 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6012 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6013 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6014 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6015 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6016 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6017 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6018 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6019 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6020 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6021 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6022 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6023 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6024 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6025 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6026 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6027 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6028 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6029 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6030 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6031 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6032 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6033 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6034 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6035 } },
6036 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6037 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6038 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6039 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6040 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6041 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6042 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6043 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6044 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6045 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6046 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6047 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6048 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6049 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6050 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6051 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6052 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6053 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6054 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6055 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6056 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6057 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6058 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6059 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6060 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6061 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6062 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6063 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6064 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6065 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6066 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6067 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6068 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6069 } },
6070 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6071 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6072 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6073 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6074 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6075 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6076 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6077 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6078 [ 7] = PIN_NONE,
6079 [ 8] = PIN_NONE,
6080 [ 9] = PIN_NONE,
6081 [10] = PIN_NONE,
6082 [11] = PIN_NONE,
6083 [12] = PIN_NONE,
6084 [13] = PIN_NONE,
6085 [14] = PIN_NONE,
6086 [15] = PIN_NONE,
6087 [16] = PIN_NONE,
6088 [17] = PIN_NONE,
6089 [18] = PIN_NONE,
6090 [19] = PIN_NONE,
6091 [20] = PIN_NONE,
6092 [21] = PIN_NONE,
6093 [22] = PIN_NONE,
6094 [23] = PIN_NONE,
6095 [24] = PIN_NONE,
6096 [25] = PIN_NONE,
6097 [26] = PIN_NONE,
6098 [27] = PIN_NONE,
6099 [28] = PIN_NONE,
6100 [29] = PIN_NONE,
6101 [30] = PIN_NONE,
6102 [31] = PIN_NONE,
6103 } },
6104 { /* sentinel */ },
6105};
6106
6107static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
6108 unsigned int pin)
6109{
6110 const struct pinmux_bias_reg *reg;
6111 unsigned int bit;
6112
6113 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6114 if (!reg)
6115 return PIN_CONFIG_BIAS_DISABLE;
6116
6117 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6118 return PIN_CONFIG_BIAS_DISABLE;
6119 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6120 return PIN_CONFIG_BIAS_PULL_UP;
6121 else
6122 return PIN_CONFIG_BIAS_PULL_DOWN;
6123}
6124
6125static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6126 unsigned int bias)
6127{
6128 const struct pinmux_bias_reg *reg;
6129 u32 enable, updown;
6130 unsigned int bit;
6131
6132 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6133 if (!reg)
6134 return;
6135
6136 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6137 if (bias != PIN_CONFIG_BIAS_DISABLE)
6138 enable |= BIT(bit);
6139
6140 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6141 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6142 updown |= BIT(bit);
6143
6144 sh_pfc_write(pfc, reg->pud, updown);
6145 sh_pfc_write(pfc, reg->puen, enable);
6146}
6147
6148static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6149 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6150 .get_bias = r8a7796_pinmux_get_bias,
6151 .set_bias = r8a7796_pinmux_set_bias,
6152};
6153
6154#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6155const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6156 .name = "r8a774a1_pfc",
6157 .ops = &r8a7796_pinmux_ops,
6158 .unlock_reg = 0xe6060000, /* PMMR */
6159
6160 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6161
6162 .pins = pinmux_pins,
6163 .nr_pins = ARRAY_SIZE(pinmux_pins),
6164 .groups = pinmux_groups.common,
6165 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6166 .functions = pinmux_functions.common,
6167 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6168
6169 .cfg_regs = pinmux_config_regs,
6170 .drive_regs = pinmux_drive_regs,
6171 .bias_regs = pinmux_bias_regs,
6172 .ioctrl_regs = pinmux_ioctrl_regs,
6173
6174 .pinmux_data = pinmux_data,
6175 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6176};
6177#endif
6178
6179#ifdef CONFIG_PINCTRL_PFC_R8A7796
6180const struct sh_pfc_soc_info r8a7796_pinmux_info = {
6181 .name = "r8a77960_pfc",
6182 .ops = &r8a7796_pinmux_ops,
6183 .unlock_reg = 0xe6060000, /* PMMR */
6184
6185 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6186
6187 .pins = pinmux_pins,
6188 .nr_pins = ARRAY_SIZE(pinmux_pins),
6189 .groups = pinmux_groups.common,
6190 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6191 ARRAY_SIZE(pinmux_groups.automotive),
6192 .functions = pinmux_functions.common,
6193 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6194 ARRAY_SIZE(pinmux_functions.automotive),
6195
6196 .cfg_regs = pinmux_config_regs,
6197 .drive_regs = pinmux_drive_regs,
6198 .bias_regs = pinmux_bias_regs,
6199 .ioctrl_regs = pinmux_ioctrl_regs,
6200
6201 .pinmux_data = pinmux_data,
6202 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6203};
6204#endif