tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6#ifndef _MEI_HW_MEI_REGS_H_
7#define _MEI_HW_MEI_REGS_H_
8
9/*
10 * MEI device IDs
11 */
12#define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
13#define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
14#define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
15#define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
16
17#define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
18#define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
19
20#define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
21#define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
22#define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
23#define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
24#define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
25
26#define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
27#define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
28#define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
29#define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
30#define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
31
32#define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
33#define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
34#define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
35#define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
36
37#define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
38#define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
39#define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
40#define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
41
42#define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
43#define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
44
45#define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
46#define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */
47
48#define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
49#define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
50#define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
51
52#define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */
53#define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */
54#define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */
55#define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */
56
57#define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */
58#define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */
59
60#define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */
61#define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */
62#define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */
63#define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */
64
65#define MEI_DEV_ID_LBG 0xA1BA /* Lewisburg (SPT) */
66
67#define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */
68#define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */
69
70#define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton IE */
71
72#define MEI_DEV_ID_GLK 0x319A /* Gemini Lake */
73
74#define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */
75#define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */
76
77#define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */
78#define MEI_DEV_ID_CNP_LP_4 0x9DE4 /* Cannon Point LP 4 (iTouch) */
79#define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */
80#define MEI_DEV_ID_CNP_H_4 0xA364 /* Cannon Point H 4 (iTouch) */
81
82#define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */
83
84/*
85 * MEI HW Section
86 */
87
88/* Host Firmware Status Registers in PCI Config Space */
89#define PCI_CFG_HFS_1 0x40
90# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
91#define PCI_CFG_HFS_2 0x48
92#define PCI_CFG_HFS_3 0x60
93#define PCI_CFG_HFS_4 0x64
94#define PCI_CFG_HFS_5 0x68
95#define PCI_CFG_HFS_6 0x6C
96
97/* MEI registers */
98/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
99#define H_CB_WW 0
100/* H_CSR - Host Control Status register */
101#define H_CSR 4
102/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
103#define ME_CB_RW 8
104/* ME_CSR_HA - ME Control Status Host Access register (read only) */
105#define ME_CSR_HA 0xC
106/* H_HGC_CSR - PGI register */
107#define H_HPG_CSR 0x10
108/* H_D0I3C - D0I3 Control */
109#define H_D0I3C 0x800
110
111/* register bits of H_CSR (Host Control Status register) */
112/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
113#define H_CBD 0xFF000000
114/* Host Circular Buffer Write Pointer */
115#define H_CBWP 0x00FF0000
116/* Host Circular Buffer Read Pointer */
117#define H_CBRP 0x0000FF00
118/* Host Reset */
119#define H_RST 0x00000010
120/* Host Ready */
121#define H_RDY 0x00000008
122/* Host Interrupt Generate */
123#define H_IG 0x00000004
124/* Host Interrupt Status */
125#define H_IS 0x00000002
126/* Host Interrupt Enable */
127#define H_IE 0x00000001
128/* Host D0I3 Interrupt Enable */
129#define H_D0I3C_IE 0x00000020
130/* Host D0I3 Interrupt Status */
131#define H_D0I3C_IS 0x00000040
132
133/* H_CSR masks */
134#define H_CSR_IE_MASK (H_IE | H_D0I3C_IE)
135#define H_CSR_IS_MASK (H_IS | H_D0I3C_IS)
136
137/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
138/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
139access to ME_CBD */
140#define ME_CBD_HRA 0xFF000000
141/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
142#define ME_CBWP_HRA 0x00FF0000
143/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
144#define ME_CBRP_HRA 0x0000FF00
145/* ME Power Gate Isolation Capability HRA - host ready only access */
146#define ME_PGIC_HRA 0x00000040
147/* ME Reset HRA - host read only access to ME_RST */
148#define ME_RST_HRA 0x00000010
149/* ME Ready HRA - host read only access to ME_RDY */
150#define ME_RDY_HRA 0x00000008
151/* ME Interrupt Generate HRA - host read only access to ME_IG */
152#define ME_IG_HRA 0x00000004
153/* ME Interrupt Status HRA - host read only access to ME_IS */
154#define ME_IS_HRA 0x00000002
155/* ME Interrupt Enable HRA - host read only access to ME_IE */
156#define ME_IE_HRA 0x00000001
157
158
159/* H_HPG_CSR register bits */
160#define H_HPG_CSR_PGIHEXR 0x00000001
161#define H_HPG_CSR_PGI 0x00000002
162
163/* H_D0I3C register bits */
164#define H_D0I3C_CIP 0x00000001
165#define H_D0I3C_IR 0x00000002
166#define H_D0I3C_I3 0x00000004
167#define H_D0I3C_RR 0x00000008
168
169#endif /* _MEI_HW_MEI_REGS_H_ */